Search results for "MoSiS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
75	César A. Piña	Evolution Of The Mosis VLSI Educational Program.	DELTA	2002	DBLP DOI BibTeX RDF
60	César A. Piña	Low Cost IC Prototyping from the MOSIS Service.	MSE	1999	DBLP DOI BibTeX RDF
45	Andrzej Rucinski 0002, Barrett Stetson, S. T. P. Brundavani	A DOT1 & DOT4 MOSIS - Compatible Library.	MSE	2003	DBLP DOI BibTeX RDF
43	Charles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau	A FIFO Ring Performance Experiment.	ASYNC	1997	DBLP DOI BibTeX RDF	FIFO ring performance experiment, high-speed FIFO circuit, asynchronous FIFO, clocked shift register, pulse-like protocol, two-phase clocked design, MOSIS, internal FIFO stages, 3.3 V, 1.67 to 4.8 V, 0.6 micron, pipeline, SPICE, data path, hSpice, circuit delays
43	Mark R. Greenstreet	Implementing a STARI chip.	ICCD	1995	DBLP DOI BibTeX RDF	STARI chip, high-speed signaling technique, MOSIS 2/spl mu/ CMOS process, self-timed FIFO, robust compensation, clock skew, digital signal processing chips, CMOS digital integrated circuits, self-timed circuits, synchronous circuits, 2 micron, timing circuits
43	Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III	A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.	ARVLSI	1995	DBLP DOI BibTeX RDF	high-speed fine-resolution pattern generation, data signals, edge placement, matched delays, MOSIS CMOS technology, 100 ps, 833 Mbit/s, architecture, delays, test pattern generators, network interfaces, CMOS digital integrated circuits, 1.2 micron
43	Jason P. Hurst, Adit D. Singh	A differential built-in current sensor design for high speed IDDQ testing.	VLSI Design	1995	DBLP DOI BibTeX RDF	built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices
43	Yann Disser, Nils Mosis	A unified worst case for classical simplex and policy iteration pivot rules.	CoRR	2023	DBLP DOI BibTeX RDF
43	Yann Disser, Nils Mosis	A Unified Worst Case for Classical Simplex and Policy Iteration Pivot Rules.	ISAAC	2023	DBLP DOI BibTeX RDF
43	Júlia Baligács, Yann Disser, Nils Mosis, David Weckbecker	An Improved Algorithm for Open Online Dial-a-Ride.	CoRR	2022	DBLP DOI BibTeX RDF
43	Júlia Baligács, Yann Disser, Nils Mosis, David Weckbecker	An Improved Algorithm for Open Online Dial-a-Ride.	WAOA	2022	DBLP DOI BibTeX RDF
43	Sandra Vosbergen, Ersen B. Colkesen, Joyca Lacroix, Georgio Mosis, Pieter Jan Stappers, Roderik A. Kraaijenhagen, Niels Peek	Assessment of user needs for self-management services in coronary heart disease: a designerly approach.	ECCE	2010	DBLP DOI BibTeX RDF
43	Georgio Mosis, Albert E. Vlug, Mees Mosseveld, Jeanne P. Dieleman, Bruno C. Stricker, Johan van der Lei, Miriam C. J. M. Sturkenboom	Application of Information Technology: A Technical Infrastructure to Conduct Randomized Database Studies Facilitated by a General Practice Research Database.	J. Am. Medical Informatics Assoc.	2005	DBLP DOI BibTeX RDF
31	Tainá Thomassim Guimarães, Diego Henrique Diemmer Mariani, Lucas Silveira Kupssinskü, Pedro Rossa, Rafael Kenji Horota, Rafael de Freitas, Luiz Roupinha, Branda Eloá Weppo, Aline Weschenfelder, André Luiz Durante Spigolon, Luiz Gonzaga 0001, Maurício Roberto Veronez	Mosis Lab Hyperspectral - Visualization and Correlation of Hyperspectral Data on Immersive Virtual Reality.	IGARSS	2021	DBLP DOI BibTeX RDF
31	Pedro Rossa, Julia Boesing Ponticelli, Luiz Gonzaga da Silveira Jr., Maurício Roberto Veronez, Caroline Lessio Cazarin, Rafael Kenji Horota, Alysson Soares Aires, Ademir Marques Jr., Eniuce Menezes De Souza, Gabriel Lanzer Kannenberg, Jean Luca de Fraga, Leonardo Santana, Demetrius Nunes Alves	MOSIS V2: Immersive Virtual Outcrop Models.	IGARSS	2019	DBLP DOI BibTeX RDF
31	Pedro Rossa, Rafael Kenji Horota, Ademir Marques Junior, Alysson Soares Aires, Eniuce Menezes De Souza, Gabriel Lanzer Kannenberg, Jean Luca de Fraga, Leonardo Gomes Santana, Demetrius Nunes Alves, Julia Boesing, Luiz Gonzaga Jr., Maurício Roberto Veronez, Caroline Lessio Cazarin	MOSIS: Immersive Virtual Field Environments for Earth Sciences.	VR	2019	DBLP DOI BibTeX RDF
31	Bahram Javidi, Xin Shen, Adam S. Markman, Pedro Latorre Carmona, Adolfo Martínez Usó, José Martínez Sotoca, Filiberto Pla, Manuel Martínez-Corral, Genaro Saavedra, Yi-Pai Huang, Adrian Stern	Multidimensional Optical Sensing and Imaging System (MOSIS): From Macroscales to Microscales.	Proc. IEEE	2017	DBLP DOI BibTeX RDF
31	Luiz Gonzaga Jr., Maurício Roberto Veronez, Demetrius Nunes Alves, Fabiane Bordin, Gabriel Lanzer Kannenberg, Fernando P. Marson, Francisco M. W. Tognoli, Leonardo Campos Inocencio	MOSIS - Multi-outcrop sharing & interpretation system.	IGARSS	2017	DBLP DOI BibTeX RDF
31	Grzegorz Deptuch	3DIC multi-project fabrication run being organized by CMC/CMP/MOSIS and Tezzaron.	3DIC	2010	DBLP DOI BibTeX RDF
31	Hans Petter Dahle	MOSIS project data.	Combining the Advantages of Product Lines and Open Source	2008	DBLP BibTeX RDF
31	César A. Piña	MOSIS: IC Prototyping and Low Volume Production Service.	MSE	2001	DBLP DOI BibTeX RDF
31	Toby Schaffer, Andy Stanaski, Alan Glaser, Paul D. Franzon	The NCSU Cadence Design Kit for IC Fabrication through MOSIS.	MSE	1999	DBLP DOI BibTeX RDF
31	Ronald F. Ayres	A narrative history and description of MOSIS software.	J. Syst. Softw.	1998	DBLP DOI BibTeX RDF
31	M. Weatherford	MOSIS eyes the future.	IEEE Micro	1997	DBLP DOI BibTeX RDF
31	Jennifer Peltier, Wes Hansford	Low cost, prototype ASIC and MCM fabrication and assembly from the MOSIS service.	MSE	1997	DBLP DOI BibTeX RDF
31	John Staudhammer	Educational use of MOSIS.	MSE	1997	DBLP DOI BibTeX RDF
31	Felix Breitenecker, G. Schuster	Modular Parallelization in the Simulation Project HYBSYS - The Mosis System.	EUROSIM	1992	DBLP BibTeX RDF
31	Yehuda Afek, Ronald F. Ayres, David Booth, Danny Cohen, Kathie Fry, Rick Gillespie, Joel Goldberg, Joe Green, David Hollenberg, George Lewicki, Terri Lewis, Lee Richardson, Barden Smith, Victoria Svoboda, Vance Tyree, Jasmin Witthoft	Chips and Boards Through MOSIS.	COMPCON	1985	DBLP BibTeX RDF
29	James E. Stine, Johannes Grad, Ivan D. Castellanos, Jeff M. Blank, Vibhuti B. Dave, Mallika Prakash, Nick Iliev, Nathan Jachimiec	A Framework for High-Level Synthesis of System-on-Chip Designs.	MSE	2005	DBLP DOI BibTeX RDF
29	Paul E. Hasler, AiChen Low	Programmable Low Dropout Voltage Regulator.	IWSOC	2005	DBLP DOI BibTeX RDF
29	Johannes Grad, James E. Stine	A Standard Cell Library for Student Projects.	MSE	2003	DBLP DOI BibTeX RDF
28	Andreas Svendsen, Gøran K. Olsen, Jan Endresen, Thomas Moen, Erik Carlson, Kjell-Joar Alme, Øystein Haugen	The Future of Train Signaling.	MoDELS	2008	DBLP DOI BibTeX RDF	MoSiS, Train, model-driven development, signaling, DSL, interlocking
15	Eduardo Conrad Jr., Fernando da Rocha Paixão Cortes, Sergio Bampi, Alessandro Girardi	Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors.	SBCCI	2008	DBLP DOI BibTeX RDF	TAT, TST, association of transistors, measurements, device modeling
15	Fernando da Rocha Paixão Cortes, Sergio Bampi	A 40mhz 70db gain variable gain amplifier design using the gm/id design method.	SBCCI	2008	DBLP DOI BibTeX RDF	Variable Gain Amplifier (VGA), cmos analog design, rf front-end, amplifier
15	Bradley A. Minch	A simple class-AB transconductor in CMOS.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Jaime Ramírez-Angulo, Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Sri Raga Sudha Garimella, Antonio J. López-Martín, Ramón González Carvajal	An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators.	VLSI Design	2008	DBLP DOI BibTeX RDF
15	Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang 0009, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips	A MIPS R2000 implementation.	DAC	2008	DBLP DOI BibTeX RDF	RISC, MIPS
15	César Augusto Prior, Cesar Ramos Rodrigues, João Baptista dos Santos Martins, André Luiz Aita, Filipe Costa Beber Vieira	Design of an integrated low power high CMRR instrumentation amplifier for biomedical applications.	SBCCI	2007	DBLP DOI BibTeX RDF	higth CMRR, low power, analog integrated circuits, current mode, instrumentation amplifier
15	Alexander Fish, Tomer Rothschild, Avichay Hodes, Yonatan Shoshan, Orly Yadid-Pecht	Low Power CMOS Image Sensors Employing Adaptive Bulk Biasing Control (AB2C) Approach.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Bradley A. Minch	Low-Voltage Wilson Current Mirrors in CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Paul E. Hasler, Christopher M. Twigg	An OTA-based Large-Scale Field Programmable Analog Array (FPAA) for faster On-Chip Communication and Computation.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Hisako Adachi, Shinji Nakamura	Efficient Designs for Adder Comparator.	CISS	2007	DBLP DOI BibTeX RDF
15	Koichi Itoh, Masashi Yamazaki, Shinji Nakamura, Yasuo Nagazumi	An Attempt Towards Charge-Domain Logic (CDL).	CISS	2007	DBLP DOI BibTeX RDF
15	Sridhar Rajagopal, Joseph R. Cavallaro	Truncated Online Arithmetic with Applications to Communication Systems.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Dynamic truncation, finite precision, communication systems, online arithmetic
15	James Moritz, Yichuang Sun	100MHz, 6th order, leap-frog gm-C high Q bandpass filter and on-chip tuning scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Byungsub Kim, Soumyajit Mandal, Rahul Sarpeshkar	Power-adaptive operational amplifier with positive-feedback self biasing.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Volnei A. Pedroni, Ricardo U. Pedroni	PLL-less clock multiplier with self-adjusting phase symmetry.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Jesús Ezequiel Molinar-Solís, Felipe Gomez-Castañeda, Jose A. Moreno-Cadenas, Víctor Hugo Ponce Ponce	Very fast programmable CNN based on FG-inverter.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Timothy D. Strong, Steven M. Martin, Robert F. Franklin, Richard B. Brown	Integrated electrochemical neurosensors.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Montree Siripruchyanun	A Low-Voltage, Low-Power Current-mode Automatic Gain Control (AGC) for Battery-Powered Equipment.	DELTA	2006	DBLP DOI BibTeX RDF
15	Shweta Chary, Michael L. Bushnell	Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
15	Jianwen Zhu, Fang Fang, Qianying Tang	Calligrapher: a new layout-migration engine for hard intellectual property libraries.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
15	Shinji Nakamura, Yasuo Nagazumi	Programmable matched filter by charge-domain operation.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
15	Vishal Gupta 0003, Gabriel A. Rincón-Mora	A low dropout, CMOS regulator with high PSR over wideband frequencies.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
15	Gaurav Gulati, Erik Brunvand	Design of a cell library for asynchronous microengines.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	CMOS cell library, microprogramed control, asynchronous control, self-timed systems
15	Qianying Tang, Jianwen Zhu	Two-Dimensional Layout Migration by Soft Constraint Satisfaction.	ISQED	2005	DBLP DOI BibTeX RDF
15	Fang Fang, Jianwen Zhu	Automatic process migration of datapath hard IP libraries.	ASP-DAC	2004	DBLP DOI BibTeX RDF
15	Arunkumar Balasundaram, Angelo Pereira, Jun-Cheol Park, Vincent John Mooney III	Golay and wavelet error control codes in VLSI.	ASP-DAC	2004	DBLP DOI BibTeX RDF
15	Ravi Chawla, Guillermo J. Serrano, Daniel J. Allen, Angelo W. Pereira, Paul E. Hasler	Fully differential floating-gate programmable OTAs with novel common-mode feedback.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
15	Ravi Chawla, Haw-Jing Lo, Arindam Basu, Paul E. Hasler, Bradley A. Minch	A fully programmable log-domain bandpass filter using multiple-input translinear elements.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
15	Paul D. Smith, David W. Graham, Ravi Chawla, Paul E. Hasler	A five-transistor bandpass filter element.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
15	Fang Fang, Jianwen Zhu	Calligrapher: A New Layout Migration Engine Based on Geometric Closeness.	ISQED	2004	DBLP DOI BibTeX RDF
15	Donald W. Bouldin, Adam Miller, Chandra Tan	Teaching Custom Integrated Circuit Design and Verification.	MSE	2003	DBLP DOI BibTeX RDF
15	Gary H. Bernstein, Jay B. Brockman, Peter M. Kogge, Gregory L. Snider, Barbara E. Walvoord	From Bits to Chips: A Multidisciplinary Curriculum for Microelectronics System Design Education.	MSE	2003	DBLP DOI BibTeX RDF
15	Tetsuya Fujiwara, Yoshihiko Horio, Kazuyuki Aihara	An integrated multi-scroll circuit with floating-gate MOSFETs.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
15	Timothy Kuan-Ta Lu, Michael W. Baker, Christopher D. Salthouse, Ji-Jon Sit, Serhii M. Zhak, Rahul Sarpeshkar	A micropower analog VLSI processing channel for bionic ears and speech-recognition front ends.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
15	Han Jung Song, John G. Harris	A CMOS neural oscillator using negative resistance.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
15	Haihua Yan, Adit D. Singh	Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die.	ITC	2003	DBLP DOI BibTeX RDF
15	Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy 0001	Skewed CMOS: noise-tolerant high-performance low-power static circuit family.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
15	Marcos Ferretti, Peter A. Beerel	Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding.	DATE	2002	DBLP DOI BibTeX RDF
15	Albert H. Titus, Anand Gopalan	A differential summing amplifier for analog VLSI systems.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
15	Alex Yoondong Park, Steve H. Jen, Bing J. Sheu, Heesook Yoon, In Gyeom Kim	An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
15	Paul D. Smith, Matt Kucic, Richard Ellis, Paul E. Hasler, David V. Anderson	Mel-frequency cepstrum encoding in analog floating-gate circuitry.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
15	Yi-Cheng Chang, Edwin W. Greeneich	CMOS auto-ranging PLL for low-voltage wideband systems.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
15	Andrzej Rucinski 0002, Barbara Dziurla-Rucinska	Boundary Scan as a Test Solution in Microelectronics Curricula.	DELTA	2002	DBLP DOI BibTeX RDF	IEEE 1149.4 standard, Education, Boundary scan
15	Richard J. Blaikie, Maan M. Alkaisi, Steven M. Durbin, David R. S. Cumming	Teaching Integrated Circuit and Semiconductor Device Design in New Zealand: The University of Canterbury Approach.	DELTA	2002	DBLP DOI BibTeX RDF	Semiconductor Devices, Education, Integrated Circuit
15	Jo C. Ebergen	Squaring the FIFO in GasP.	ASYNC	2001	DBLP DOI BibTeX RDF
15	Kinya Matsuda, Yoshihiko Horio, Kazuyuki Aihara	A simulated LC oscillator using multi-input floating-gate MOSFETS.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
15	Gin Yee, Carl Sechen	Clock-delayed domino for dynamic circuit design.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
15	Victor Varshavsky, Vyacheslav Marakhovsky	Beta-CMOS Artificial Neuron and Implementability Limits.	IWANN (2)	1999	DBLP DOI BibTeX RDF
15	Bill Coates 0001, Jo C. Ebergen, Jon K. Lexau, Scott Fairbanks, Ian W. Jones, Alex Ridgway, David Money Harris, Ivan E. Sutherland	A Counterflow Pipeline Experiment.	ASYNC	1999	DBLP DOI BibTeX RDF
15	Alexandre F. Tenca, Milos D. Ercegovac	On the Design of High-Radix On-Line Division for Long Precision.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
15	Zhen Luo, Margaret Martonosi, Pranav Ashar	An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking.	FCCM	1999	DBLP DOI BibTeX RDF	Scanline Algorithm, Configurable Hardware, FPGA, DRC
15	Jing Shen, Koichi Tanno, Okihiko Ishizuka	Down Literal Circuit with Neuron-MOS Transistors and Its Applications.	ISMVL	1999	DBLP DOI BibTeX RDF
15	Yoshihiko Horio, Izumi Kobayashi, Masato Kawakami, Hiroshi Hayashi, Kazuyuki Aihara	Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
15	A. Rasmussen, Mona E. Zaghloul	The design and fabrication of microfluidic flow sensors.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
15	Louiza Sellami, Robert W. Newcomb	A MOSFET bridge fluid biosensor.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
15	Kai He, Gert Cauwenberghs	An area-efficient analog VLSI architecture for state-parallel Viterbi decoding.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
15	Wuping Chen, Hongwei Duan, S. H. Jones	Integrated 1.2 um CMOS photodiodes, transimpedance amplifier, 12 bits A/D converter, and DSP interface for microinstrument applications.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
15	Octavio A. González, Gunhee Han, José Pineda de Gyvez, Edgar Sánchez-Sinencio	CMOS cryptosystem using a Lorenz chaotic oscillator.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
15	Roman Genov, Gert Cauwenberghs	16-channel single-chip current-mode track-and-hold acquisition system with 100 dB dynamic range.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
15	Hoda S. Abdel-Aty-Zohdy, Mahmoud Al-Nsour	Reinforcement learning neural network circuits for electronic nose.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
15	Lim Chu Aun, S. M. Rezaul Hasan	An all Digital BiCMOS Phase Lock Loop for VLSI Processors.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
15	Hoda S. Abdel-Aty-Zohdy, Mahmoud Al-Nsour	Digital Neural Processing Unit for Electronic Nose.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Neural Networks, Reinforcement Learning, ASIC, Digital Design, Electronic Nose
15	Robert L. Coultrip	A CMOS binary pattern classifier based on Parzen's method.	IEEE Trans. Neural Networks	1998	DBLP DOI BibTeX RDF
15	William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, Ivan E. Sutherland	A FIFO Data Switch Design Experiment.	ASYNC	1998	DBLP DOI BibTeX RDF	Data Switch, P**3, Asynchronous, FIFO
15	Ross Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang	An Asynchronous 2-D Discrete Cosine Transform Chip.	ASYNC	1998	DBLP DOI BibTeX RDF	DCT, asynchronous, threshold logic, bit-serial
15	Suhwan Kim, Marios C. Papaefthymiou	True single-phase energy-recovering logic for low-power, high-speed VLSI.	ISLPED	1998	DBLP DOI BibTeX RDF
15	Tamara I. Ahrens, Thomas H. Lee	A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances.	ISLPED	1998	DBLP DOI BibTeX RDF
15	Robert H. Caverly	Development of a CMOS Cell Library for RF Wireless and Telecommunications Applications.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF