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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 397 occurrences of 269 keywords
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Results
Found 1116 publication records. Showing 1053 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
192 | Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan |
New MVL-PLA Structures Based on Current-Mode CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 98-103, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic |
127 | Kenneth Yan |
Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 231-234, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
115 | Yanbing Xu, Mostafa I. H. Abd-El-Barr, Carl McCrosky |
Graph-based output phase assignment for PLA minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5), pp. 613-622, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
103 | Jie Pan, Zhenqing Hou, Peijuan Zhu, Yange Wang, Qian Wang, Qiqing Zhang |
Optimization of Production of PLA Microbubble Ultrasound Contrast Agents for Hydroxycamptothecin Delivery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMEI (1) ![In: Proceedings of the 2008 International Conference on BioMedical Engineering and Informatics, BMEI 2008, May 28-30, 2008, Sanya, Hainan, China - Volume 1, pp. 400-406, 2008, IEEE Computer Society, 978-0-7695-3118-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Ultrasound contrast agent, Poly |
103 | Christos A. Papachristou, Anil L. Pandya |
A design scheme for PLA-based control tables with reduced area and time-delay cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5), pp. 453-472, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
97 | Chunduri Rama Mohan, Partha Pratim Chakrabarti |
Combined optimization of area and testability during state assignment of PLA-based FSM's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 408-413, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization |
91 | Maciej J. Ciesielski, Seiyang Yang |
PLADE: a two-stage PLA decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(8), pp. 943-954, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
91 | Che W. Chiou, Ted C. Yang |
Fully testable PLA design with minimal extra input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 633-638, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
79 | Stanislaw J. Piestrak |
Design of minimal-level PLA self-testing checkers for m-out-of-n codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(2), pp. 264-272, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
68 | Michiel M. Ligthart, Emile H. L. Aarts, Frans P. M. Beenker |
Design-for-testability of PLA's using statistical cooling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 339-345, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
PLA testing, statistical cooling, design-for-testability, PLA |
67 | Ireneusz Czarnowski, Piotr Jedrzejowicz |
An Agent-Based PLA for the Cascade Correlation Learning Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANN (2) ![In: Artificial Neural Networks: Formal Models and Their Applications - ICANN 2005, 15th International Conference, Warsaw, Poland, September 11-15, 2005, Proceedings, Part II, pp. 197-202, 2005, Springer, 3-540-28755-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
67 | Chunduri Rama Mohan, Partha Pratim Chakrabarti |
EARTH: combined state assignment of PLA-based FSM's targeting area and testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7), pp. 727-731, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
67 | Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya |
BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 385-391, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
62 | Suganth Paul, Rajesh Garg, Sunil P. Khatri |
Pipelined network of PLA based circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 213-218, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
synchronous, pipelining, PLA |
62 | Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada |
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 166-171, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
logic synthesis, PLA |
62 | Dong Sam Ha, Sudhakar M. Reddy |
On the design of random pattern testable PLA based on weighted random pattern testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(2), pp. 149-157, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
built-in self-test, PLA, testable design, random pattern testability |
61 | Reinhard Rauscher, Andreas Krause 0007 |
A System for Heuristic Modifications on PLA - Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 267-274, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
heuristic modifications, PLA-specifications, numerical exactness, implicated deviation, optimization tool, HOPE, ESPRESSO, programmable logic arrays, binary coding |
60 | Scott A. Hendrickson, Swaminathan Subramanian, André van der Hoek |
Multi-tiered design rationale for change set based product line architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SHARK ![In: Proceedings of the 3rd International Workshop on Sharing and Reusing Architectural Knowledge, SHARK 2008, Leipzig, Germany, May 13, 2008, pp. 41-44, 2008, ACM, 978-1-60558-038-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
design rationale, architectural knowledge, product line architectures |
60 | Ben I. Hounsell, Tughrul Arslan, Robert Thomson 0003 |
Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Soft Comput. ![In: Soft Comput. 8(5), pp. 307-317, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Robust hardware, Finite impulse response filters, Genetic algorithms, Fault tolerant, Programmable logic arrays, PLAs, FIR filters, Evolvable hardware |
60 | Ben I. Hounsell, Tughrul Arslan |
Evolutionary Design And Adaptation Of Digital Filters Within An Embedded Fault Tolerant Hardware Platform . ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 3rd NASA / DoD Workshop on Evolvable Hardware (EH 2001), 12-14 July 2001, Long Beach, CA, USA, pp. 127-135, 2001, IEEE Computer Society, 0-7695-1180-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
60 | Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu |
A graph representation for programmable logic arrays to facilitate testing and logic design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10), pp. 1030-1043, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
60 | Kye S. Hedlund |
Electrical optimization of PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 681-687, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
55 | K. Vijayan Asari, C. Eswaran |
An Optimization Technique for the Design of Multiple Valued PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(1), pp. 118-122, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
multiple valued PLA design, output encoding, binary output, multiple function literal circuits, PLA size, encoding, minimization, programmable logic arrays, adders, adder, many-valued logics, minimisation, multiple valued logic, logic arrays, optimization technique, network synthesis |
55 | Scott A. Hendrickson, Yang Wang 0005, André van der Hoek, Richard N. Taylor, Alfred Kobsa |
Modeling PLA variation of privacy-enhancing personalized systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPLC ![In: Software Product Lines, 13th International Conference, SPLC 2009, San Francisco, California, USA, August 24-28, 2009, Proceedings, pp. 71-80, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
55 | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang |
Crosstalk Minimization in Logic Synthesis for PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 790-795, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
55 | Mirjam Steger, Christian Tischer 0002, Birgit Boss, Andreas Müller 0014, Oliver Pertler, Wolfgang Stolz, Stefan Ferber |
Introducing PLA at Bosch Gasoline Systems: Experiences and Practices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPLC ![In: Software Product Lines, Third International Conference, SPLC 2004, Boston, MA, USA, August 30-September 2, 2004, Proceedings, pp. 34-50, 2004, Springer, 3-540-22918-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
55 | Fan Mo, Robert K. Brayton |
PLA-based regular structures and their synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6), pp. 723-729, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
55 | Kaamran Raahemifar, Majid Ahmadi |
An efficient 0-1 linear programming for optimal PLA folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 581-584, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
55 | Alireza Kaviani, Stephen Dean Brown |
Technology mapping issues for an FPGA with lookup tables and PLA-like blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 60-66, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
55 | Gwo-Haur Hwang, Wen-Zen Shen |
Restructuring and logic minimization for testable PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4), pp. 488-496, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
55 | Chun-Yeh Liu, Kewal K. Saluja |
An efficient algorithm for bipartite PLA folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12), pp. 1839-1847, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
55 | Claudio Arbib |
Two Polynomial Problems in PLA Folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WG ![In: Graph-Theoretic Concepts in Computer Science, 16rd International Workshop, WG '90, Berlin, Germany, June 20-22, 1990, Proceedings, pp. 119-129, 1990, Springer, 3-540-53832-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
55 | J. E. (Ned) Lecky, O. J. Murphy, Richard Absher |
Graph theoretic algorithms for the PLA folding problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(9), pp. 1014-1021, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
55 | Pierre G. Paulin |
Horizontal Partitioning of PLA-based Finite State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 333-338, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
55 | Norbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth |
A Defect-Tolerant and Fully Testable PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 22-33, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
55 | M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli |
Programmable logic circuits based on ambipolar CNFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 339-340, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CNFET, FPGA, PLA, carbon nanotube |
55 | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang |
Crosstalk minimization in logic synthesis for PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(4), pp. 890-915, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
synthesis, Crosstalk, PLA, domino logic |
55 | Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri |
A design flow to optimize circuit delay by using standard cells and PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 217-222, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
PLA, standard cell |
55 | Sudhakar Bobba, Ibrahim N. Hajj |
Maximum Current Estimation in Programmable Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 301-306, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
maximum current, PLA |
55 | Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell |
Functional test generation for path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 339-345, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults |
54 | Saied Bozorgui-Nesbat, Edward J. McCluskey |
Lower Overhead Design for Testability of Programmable Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(4), pp. 379-383, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
test generation for PLA's, PLA testing, Design for testability, programmable logic arrays (PLA) |
54 | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang |
Performance-driven mapping for CPLD architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 39-47, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
PLA-style logic cells, FPGA, technology mapping, CPLD, delay optimization |
54 | Anzhela Yu. Matrosova, Sergey Ostanin |
Self-Checking FSM Design with Observing only FSM Outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 153-154, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Self-checking design, unidirectional fault, PLA description, multilevel synthesis, FSM |
50 | Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri |
A PLA based asynchronous micropipelining approach for subthreshold circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 419-424, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
micro-pipelining, asynchronous, PLA, sub-threshold |
48 | Yang Wang 0005, Alfred Kobsa |
Performance Evaluation of a Privacy-Enhancing Framework for Personalized Websites. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UMAP ![In: User Modeling, Adaptation, and Personalization, 17th International Conference, UMAP 2009, formerly UM and AH, Trento, Italy, June 22-26, 2009. Proceedings, pp. 78-89, 2009, Springer, 978-3-642-02246-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
48 | Patrick H. S. Brito, Cecília M. F. Rubira, Rogério de Lemos |
Verifying architectural variabilities in software fault tolerance techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WICSA/ECSA ![In: Joint Working IEEE/IFIP Conference on Software Architecture 2009 and European Conference on Software Architecture 2009, WICSA/ECSA 2009, Cambridge, UK, 14-17 September 2009, pp. 231-240, 2009, IEEE Computer Society, 978-1-4244-4984-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
48 | Pedro O. Rossel, Daniel Perovich, M. Cecilia Bastarrica |
Reuse of Architectural Knowledge in SPL Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSR ![In: Formal Foundations of Reuse and Domain Engineering, 11th International Conference on Software Reuse, ICSR 2009, Falls Church, VA, USA, September 27-30, 2009. Proceedings, pp. 191-200, 2009, Springer, 978-3-642-04210-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
48 | Joanna Jedrzejowicz, Piotr Jedrzejowicz |
Agent-Based Approach to Solving Difficult Scheduling Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE ![In: Advances in Applied Artificial Intelligence, 19th International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2006, Annecy, France, June 27-30, 2006, Proceedings, pp. 24-33, 2006, Springer, 3-540-35453-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Weishan Zhang, Stan Jarzabek |
Reuse without Compromising Performance: Industrial Experience from RPG Software Product Line for Mobile Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPLC ![In: Software Product Lines, 9th International Conference, SPLC 2005, Rennes, France, September 26-29, 2005, Proceedings, pp. 57-69, 2005, Springer, 3-540-28936-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
48 | Claudia Fritsch, Ralf Hahn |
Product Line Potential Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPLC ![In: Software Product Lines, Third International Conference, SPLC 2004, Boston, MA, USA, August 30-September 2, 2004, Proceedings, pp. 228-237, 2004, Springer, 3-540-22918-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal |
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 514-515, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
48 | Shambhu J. Upadhyaya, Kewal K. Saluja |
A new approach to the design of built-in self-testing PLAs for high fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 60-67, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
43 | Petros Oikonomakos, Simon W. Moore |
An Asynchronous PLA with Improved Security Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 257-264, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Reza Molavi, Shahriar Mirabbasi, Resve A. Saleh |
A high-speed low-energy dynamic PLA using an input-isolation scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada |
Logic synthesis for PLA with 2-input logic elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 373-376, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada |
A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 3-4, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
43 | Kazuhiro Tsuchiya, Yoshiyasu Takefuji |
A neural network approach to PLA folding problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10), pp. 1299-1305, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
43 | Srinivas Devadas, Hi-Keung Tony Ma |
Easily testable PLA-based finite state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6), pp. 604-611, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
43 | Chin-Long Wey, Tsin-Yuan Chang |
An efficient output phase assignment for PLA minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1), pp. 1-7, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
43 | R. Galivanche, Sudhakar M. Reddy |
A Parallel PLA Minimization Program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 600-607, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
43 | Chidchanok Lursinsap, Daniel Gajski |
Improving a PLA Area by Pull-Up Transistor Folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 608-614, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
43 | Christine M. Gerveshi |
Comparison of CMOS PLA and polycell representations of control logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 638-642, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
43 | Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli |
PLATYPUS: a PLA test pattern generation tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 197-203, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
43 | Yue-Sun Kuo, C. Chen, T. C. Hu |
A heuristic algorithm for PLA block folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 744-747, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
38 | Erika Pittella, Livio D'Alvia, Eduardo Palermo, Emanuele Piuzzi |
Microwave Characterization of 3D Printed PLA and PLA/CNT Composites. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSI ![In: 6th IEEE International Forum on Research and Technology for Society and Industry, RTSI 2021, Naples, Italy, September 6-9, 2021, pp. 52-56, 2021, IEEE, 978-1-6654-4135-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
38 | Anatoly Hwatow, Margaret Gradova, Oleg Gradov, Sergey Lomakin |
PLA and PLA+cellulose containing dropelets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2020 |
DOI RDF |
|
38 | Abbas Dandache |
Conception de PLA CMOS. (CMOS PLA design). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1986 |
RDF |
|
38 | Abbas Dandache |
Évaluations électriques et temporelles des PLA complexes COMPLETE : COM plex PLA Electrical and Temporal Evaluator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1983 |
RDF |
|
38 | Will Sherwood |
PLATO - PLA Translator/Optimizer - "a ROM is a PLA in no uncertain terms.". ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 28-35, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
38 | Jing-Yang Jou |
An effective BIST design for PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 286-292, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BIST design, deterministic test pattern generator, cross point, AND array, fault detection capability, contact fault model, logic testing, built-in self test, integrated circuit testing, combinational circuits, automatic testing, programmable logic arrays, PLA, CMOS logic circuits, characteristic polynomial, stuck-at fault model, multiple input signature register |
38 | Wilfried Daehn |
A unified treatment of PLA faults by Boolean differences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 334-338, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
Boolean difference, cubical calculus, test pattern calculation, PLA |
37 | U. K. Bhattacharyya, Idranil Sen Gupta, S. Shyama Nath, P. Dutta |
PLA based synthesis and testing of hazard free logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 121-124, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multi-output circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions |
37 | Wen-Zen Shen, Gwo-Haur Hwang, Wen-Jun Hsu, Yun-Jung Jan |
Design of Pseudoexhaustive Testable PLA with Low Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(7), pp. 887-891, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
pseudoexhaustive testable PLA, large embedded programmable logic array, low overhead PET, logic testing, built-in self test, design for testability, product lines, logic arrays, test length, area overhead |
37 | Edward A. Bender, Jon T. Butler |
On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(1), pp. 82-98, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
product terms, nonzero output values, PLA size, realizable functions, lower bounds, logic design, upper bounds, variance, switching functions, logic arrays, minimisation of switching nets, multiple-valued functions |
37 | Robert P. Treuer, Vinod K. Agarwal, Hideo Fujiwara |
A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 36(3), pp. 369-373, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
output response compression, parity bits, Built-in self test (BIST), fault models, fault coverage, VLSI design, test pattern generation, programmable logic array (PLA) |
37 | Sudhakar M. Reddy, Dong Sam Ha |
A New Approach to the Design of Testable PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 36(2), pp. 201-211, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
testing, Fault detection, programmable logic array (PLA), multiple faults, testable design |
37 | Janusz Rajski, Jerzy Tyszer |
The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(1), pp. 81-85, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
PLA testing, contact faults, fault coverage, fault masking, multiple fault detection, Combinatorial analysis |
37 | Yuval Tamir, Carlo H. Séquin |
Design and Application of Self-Testing Comparators Implemented with MOS PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(6), pp. 493-506, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
two-rail code checker, duplication and matching, faults in VLSI circuits, MOS PLA fault model, self-testing comparator, programmable logic array, Concurrent error detection |
36 | Vinod K. Agarwal |
Multiple Fault Detection in Programmable Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(6), pp. 518-522, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
single fault coverage, Contact faults, PLA fault detection, PLA modeling, programmable logic arrays, masking, multiple fault detection |
36 | Venkata Rajesh Mekala, Venkata Rakesh Mekala |
Methodology for Characterization of NOR-NOR Programmable Logic Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: Second Asia International Conference on Modelling and Simulation, AMS 2008, Kuala Lumpur, Malaysia, May 13-15, 2008, pp. 1025-1028, 2008, IEEE Computer Society, 978-0-7695-3136-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
H-Spice |
36 | Maria Kontaki, Apostolos N. Papadopoulos, Yannis Manolopoulos |
Continuous Trend-Based Clustering in Data Streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DaWaK ![In: Data Warehousing and Knowledge Discovery, 10th International Conference, DaWaK 2008, Turin, Italy, September 2-5, 2008, Proceedings, pp. 251-262, 2008, Springer, 978-3-540-85835-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Uthman Alsaiari, Resve A. Saleh |
Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 703-710, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Jules White, Douglas C. Schmidt, Egon Wuchner, Andrey Nechypurenko |
Automating Product-Line Variant Selection for Mobile Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPLC ![In: Software Product Lines, 11th International Conference, SPLC 2007, Kyoto, Japan, September 10-14, 2007, Proceedings, pp. 129-140, 2007, IEEE Computer Society, 0-7695-2888-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | M. Cecilia Bastarrica, Sebastián Rivas, Pedro O. Rossel |
From a Single Product Architecture to a Product Line Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCCC ![In: XXVI International Conference of the Chilean Computer Science Society (SCCC 2007), 8-9 November 2007, Iquique, Chile, pp. 115-122, 2007, IEEE Computer Society, 978-0-7695-3017-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Jules White, Douglas C. Schmidt |
FireAnt: A Tool for Reducing Enterprise Product Line Architecture Deployment, Configuration, and Testing Costs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 13th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2006), 27-30 March 2006, Potsdam, Germany, pp. 507-508, 2006, IEEE Computer Society, 0-7695-2546-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Arvind S. Krishna, Aniruddha S. Gokhale, Douglas C. Schmidt |
Context-specific middleware specialization techniques for optimizing software product-line architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: Proceedings of the 2006 EuroSys Conference, Leuven, Belgium, April 18-21, 2006, pp. 205-218, 2006, ACM, 1-59593-322-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
middleware, product lines, specializations |
36 | Joanna Jedrzejowicz, Piotr Jedrzejowicz |
New Upper Bounds for the Permutation Flowshop Scheduling Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE ![In: Innovations in Applied Artificial Intelligence, 18th International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, IEA/AIE 2005, Bari, Italy, June 22-24, 2005, Proceedings, pp. 232-235, 2005, Springer, 3-540-26551-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Mari Matinlassi |
Comparison of Software Product Line Architecture Design Methods: COPA, FAST, FORM, KobrA and QADA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: 26th International Conference on Software Engineering (ICSE 2004), 23-28 May 2004, Edinburgh, United Kingdom, pp. 127-136, 2004, IEEE Computer Society, 0-7695-2163-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang |
Performance-driven mapping for CPLD architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10), pp. 1424-1431, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Fan Mo, Robert K. Brayton |
River PLAs: a regular circuit structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 201-206, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
river routing, programmable logic array |
36 | Charles E. Stroud, James R. Bailey, Johan R. Emmert |
A New Method for Testing Re-Programmable PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(6), pp. 635-640, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
electrically erasable programmable logic array testing, manufacturing test development, bridging faults |
36 | Yong Liu 0012, Masaya Iwata, Tetsuya Higuchi, Didier Keymeulen |
An Integrated On-Line Learning System for Evolving Programmable Logic Array Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPSN ![In: Parallel Problem Solving from Nature - PPSN VI, 6th International Conference, Paris, France, September 18-20, 2000, Proceedings, pp. 589-598, 2000, Springer, 3-540-41056-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | D. M. Marcynuk, D. Michael Miller |
The OR-k method for on-line checking of programmable logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(1), pp. 53-65, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
fault secure design, on-line checking, concurrency, programmable logic array |
36 | Chidchanok Lursinsap, Daniel D. Gajski |
A technique for pull-up transistor folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8), pp. 887-896, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
31 | Adam Slowik, Jacek M. Zurada |
Evolutionary Optimization of Number of Gates in PLA Circuits Implemented in VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2009: EvoCOMNET, EvoENVIRONMENT, EvoFIN, EvoGAMES, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, EvoNUM, EvoSTOC, EvoTRANSLOG, Tübingen, Germany, April 15-17, 2009. Proceedings, pp. 363-368, 2009, Springer, 978-3-642-01128-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Mayur Bubna, Naresh Shenoy, Santanu Chattopadhyay |
An efficient greedy approach to PLA folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1356-1359, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli |
Interactive presentation: Improving the fault tolerance of nanometric PLA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 570-575, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Tzyy-Kuen Tien, Jing-Jou Tang, Kuan-Jou Chen |
A new high speed dynamic PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Jason Helge Anderson, Stephen Dean Brown |
An LPGA with Foldable PLA-style Logic Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 244-252, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | David Binger, David Knapp |
Automatic synthesis of a dual-PLA controller with a counter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 149-157, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
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