Search results for "PLA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
192	Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology.	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
127	Kenneth Yan	Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks.	ASP-DAC	2001	DBLP DOI BibTeX RDF
115	Yanbing Xu, Mostafa I. H. Abd-El-Barr, Carl McCrosky	Graph-based output phase assignment for PLA minimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
103	Jie Pan, Zhenqing Hou, Peijuan Zhu, Yange Wang, Qian Wang, Qiqing Zhang	Optimization of Production of PLA Microbubble Ultrasound Contrast Agents for Hydroxycamptothecin Delivery.	BMEI (1)	2008	DBLP DOI BibTeX RDF	Ultrasound contrast agent, Poly
103	Christos A. Papachristou, Anil L. Pandya	A design scheme for PLA-based control tables with reduced area and time-delay cost.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
97	Chunduri Rama Mohan, Partha Pratim Chakrabarti	Combined optimization of area and testability during state assignment of PLA-based FSM's.	VLSI Design	1995	DBLP DOI BibTeX RDF	combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization
91	Maciej J. Ciesielski, Seiyang Yang	PLADE: a two-stage PLA decomposition.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
91	Che W. Chiou, Ted C. Yang	Fully testable PLA design with minimal extra input.	EURO-DAC	1990	DBLP DOI BibTeX RDF
79	Stanislaw J. Piestrak	Design of minimal-level PLA self-testing checkers for m-out-of-n codes.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
68	Michiel M. Ligthart, Emile H. L. Aarts, Frans P. M. Beenker	Design-for-testability of PLA's using statistical cooling.	DAC	1986	DBLP DOI BibTeX RDF	PLA testing, statistical cooling, design-for-testability, PLA
67	Ireneusz Czarnowski, Piotr Jedrzejowicz	An Agent-Based PLA for the Cascade Correlation Learning Architecture.	ICANN (2)	2005	DBLP DOI BibTeX RDF
67	Chunduri Rama Mohan, Partha Pratim Chakrabarti	EARTH: combined state assignment of PLA-based FSM's targeting area and testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
67	Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya	BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays.	DAC	1987	DBLP DOI BibTeX RDF
62	Suganth Paul, Rajesh Garg, Sunil P. Khatri	Pipelined network of PLA based circuit design.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	synchronous, pipelining, PLA
62	Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	logic synthesis, PLA
62	Dong Sam Ha, Sudhakar M. Reddy	On the design of random pattern testable PLA based on weighted random pattern testing.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	built-in self-test, PLA, testable design, random pattern testability
61	Reinhard Rauscher, Andreas Krause 0007	A System for Heuristic Modifications on PLA - Specifications.	EUROMICRO	1996	DBLP DOI BibTeX RDF	heuristic modifications, PLA-specifications, numerical exactness, implicated deviation, optimization tool, HOPE, ESPRESSO, programmable logic arrays, binary coding
60	Scott A. Hendrickson, Swaminathan Subramanian, André van der Hoek	Multi-tiered design rationale for change set based product line architectures.	SHARK	2008	DBLP DOI BibTeX RDF	design rationale, architectural knowledge, product line architectures
60	Ben I. Hounsell, Tughrul Arslan, Robert Thomson 0003	Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform.	Soft Comput.	2004	DBLP DOI BibTeX RDF	Robust hardware, Finite impulse response filters, Genetic algorithms, Fault tolerant, Programmable logic arrays, PLAs, FIR filters, Evolvable hardware
60	Ben I. Hounsell, Tughrul Arslan	Evolutionary Design And Adaptation Of Digital Filters Within An Embedded Fault Tolerant Hardware Platform .	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
60	Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu	A graph representation for programmable logic arrays to facilitate testing and logic design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
60	Kye S. Hedlund	Electrical optimization of PLAs.	DAC	1985	DBLP DOI BibTeX RDF
55	K. Vijayan Asari, C. Eswaran	An Optimization Technique for the Design of Multiple Valued PLA's.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multiple valued PLA design, output encoding, binary output, multiple function literal circuits, PLA size, encoding, minimization, programmable logic arrays, adders, adder, many-valued logics, minimisation, multiple valued logic, logic arrays, optimization technique, network synthesis
55	Scott A. Hendrickson, Yang Wang 0005, André van der Hoek, Richard N. Taylor, Alfred Kobsa	Modeling PLA variation of privacy-enhancing personalized systems.	SPLC	2009	DBLP BibTeX RDF
55	Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang	Crosstalk Minimization in Logic Synthesis for PLA.	DATE	2004	DBLP DOI BibTeX RDF
55	Mirjam Steger, Christian Tischer 0002, Birgit Boss, Andreas Müller 0014, Oliver Pertler, Wolfgang Stolz, Stefan Ferber	Introducing PLA at Bosch Gasoline Systems: Experiences and Practices.	SPLC	2004	DBLP DOI BibTeX RDF
55	Fan Mo, Robert K. Brayton	PLA-based regular structures and their synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
55	Kaamran Raahemifar, Majid Ahmadi	An efficient 0-1 linear programming for optimal PLA folding.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
55	Alireza Kaviani, Stephen Dean Brown	Technology mapping issues for an FPGA with lookup tables and PLA-like blocks.	FPGA	2000	DBLP DOI BibTeX RDF
55	Gwo-Haur Hwang, Wen-Zen Shen	Restructuring and logic minimization for testable PLA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
55	Chun-Yeh Liu, Kewal K. Saluja	An efficient algorithm for bipartite PLA folding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
55	Claudio Arbib	Two Polynomial Problems in PLA Folding.	WG	1990	DBLP DOI BibTeX RDF
55	J. E. (Ned) Lecky, O. J. Murphy, Richard Absher	Graph theoretic algorithms for the PLA folding problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
55	Pierre G. Paulin	Horizontal Partitioning of PLA-based Finite State Machines.	DAC	1989	DBLP DOI BibTeX RDF
55	Norbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth	A Defect-Tolerant and Fully Testable PLA.	DAC	1988	DBLP BibTeX RDF
55	M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli	Programmable logic circuits based on ambipolar CNFET.	DAC	2008	DBLP DOI BibTeX RDF	CNFET, FPGA, PLA, carbon nanotube
55	Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang	Crosstalk minimization in logic synthesis for PLAs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	synthesis, Crosstalk, PLA, domino logic
55	Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri	A design flow to optimize circuit delay by using standard cells and PLAs.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	PLA, standard cell
55	Sudhakar Bobba, Ibrahim N. Hajj	Maximum Current Estimation in Programmable Logic Arrays.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	maximum current, PLA
55	Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell	Functional test generation for path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
54	Saied Bozorgui-Nesbat, Edward J. McCluskey	Lower Overhead Design for Testability of Programmable Logic Arrays.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	test generation for PLA's, PLA testing, Design for testability, programmable logic arrays (PLA)
54	Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang	Performance-driven mapping for CPLD architectures.	FPGA	2001	DBLP DOI BibTeX RDF	PLA-style logic cells, FPGA, technology mapping, CPLD, delay optimization
54	Anzhela Yu. Matrosova, Sergey Ostanin	Self-Checking FSM Design with Observing only FSM Outputs.	IOLTW	2000	DBLP DOI BibTeX RDF	Self-checking design, unidirectional fault, PLA description, multilevel synthesis, FSM
50	Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri	A PLA based asynchronous micropipelining approach for subthreshold circuit design.	DAC	2006	DBLP DOI BibTeX RDF	micro-pipelining, asynchronous, PLA, sub-threshold
48	Yang Wang 0005, Alfred Kobsa	Performance Evaluation of a Privacy-Enhancing Framework for Personalized Websites.	UMAP	2009	DBLP DOI BibTeX RDF
48	Patrick H. S. Brito, Cecília M. F. Rubira, Rogério de Lemos	Verifying architectural variabilities in software fault tolerance techniques.	WICSA/ECSA	2009	DBLP DOI BibTeX RDF
48	Pedro O. Rossel, Daniel Perovich, M. Cecilia Bastarrica	Reuse of Architectural Knowledge in SPL Development.	ICSR	2009	DBLP DOI BibTeX RDF
48	Joanna Jedrzejowicz, Piotr Jedrzejowicz	Agent-Based Approach to Solving Difficult Scheduling Problems.	IEA/AIE	2006	DBLP DOI BibTeX RDF
48	Weishan Zhang, Stan Jarzabek	Reuse without Compromising Performance: Industrial Experience from RPG Software Product Line for Mobile Devices.	SPLC	2005	DBLP DOI BibTeX RDF
48	Claudia Fritsch, Ralf Hahn	Product Line Potential Analysis.	SPLC	2004	DBLP DOI BibTeX RDF
48	James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal	Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs.	VLSI Design	1997	DBLP DOI BibTeX RDF
48	Shambhu J. Upadhyaya, Kewal K. Saluja	A new approach to the design of built-in self-testing PLAs for high fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
43	Petros Oikonomakos, Simon W. Moore	An Asynchronous PLA with Improved Security Characteristics.	DSD	2006	DBLP DOI BibTeX RDF
43	Reza Molavi, Shahriar Mirabbasi, Resve A. Saleh	A high-speed low-energy dynamic PLA using an input-isolation scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
43	Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	Logic synthesis for PLA with 2-input logic elements.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
43	Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme.	ASP-DAC	2001	DBLP DOI BibTeX RDF
43	Kazuhiro Tsuchiya, Yoshiyasu Takefuji	A neural network approach to PLA folding problems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
43	Srinivas Devadas, Hi-Keung Tony Ma	Easily testable PLA-based finite state machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
43	Chin-Long Wey, Tsin-Yuan Chang	An efficient output phase assignment for PLA minimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
43	R. Galivanche, Sudhakar M. Reddy	A Parallel PLA Minimization Program.	DAC	1987	DBLP DOI BibTeX RDF
43	Chidchanok Lursinsap, Daniel Gajski	Improving a PLA Area by Pull-Up Transistor Folding.	DAC	1987	DBLP DOI BibTeX RDF
43	Christine M. Gerveshi	Comparison of CMOS PLA and polycell representations of control logic.	DAC	1986	DBLP DOI BibTeX RDF
43	Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli	PLATYPUS: a PLA test pattern generation tool.	DAC	1985	DBLP DOI BibTeX RDF
43	Yue-Sun Kuo, C. Chen, T. C. Hu	A heuristic algorithm for PLA block folding.	DAC	1985	DBLP DOI BibTeX RDF
38	Erika Pittella, Livio D'Alvia, Eduardo Palermo, Emanuele Piuzzi	Microwave Characterization of 3D Printed PLA and PLA/CNT Composites.	RTSI	2021	DBLP DOI BibTeX RDF
38	Anatoly Hwatow, Margaret Gradova, Oleg Gradov, Sergey Lomakin	PLA and PLA+cellulose containing dropelets.		2020	DOI RDF
38	Abbas Dandache	Conception de PLA CMOS. (CMOS PLA design).		1986	RDF
38	Abbas Dandache	Évaluations électriques et temporelles des PLA complexes COMPLETE : COM plex PLA Electrical and Temporal Evaluator.		1983	RDF
38	Will Sherwood	PLATO - PLA Translator/Optimizer - "a ROM is a PLA in no uncertain terms.".	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
38	Jing-Yang Jou	An effective BIST design for PLA.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST design, deterministic test pattern generator, cross point, AND array, fault detection capability, contact fault model, logic testing, built-in self test, integrated circuit testing, combinational circuits, automatic testing, programmable logic arrays, PLA, CMOS logic circuits, characteristic polynomial, stuck-at fault model, multiple input signature register
38	Wilfried Daehn	A unified treatment of PLA faults by Boolean differences.	DAC	1986	DBLP DOI BibTeX RDF	Boolean difference, cubical calculus, test pattern calculation, PLA
37	U. K. Bhattacharyya, Idranil Sen Gupta, S. Shyama Nath, P. Dutta	PLA based synthesis and testing of hazard free logic.	VLSI Design	1995	DBLP DOI BibTeX RDF	PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multi-output circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions
37	Wen-Zen Shen, Gwo-Haur Hwang, Wen-Jun Hsu, Yun-Jung Jan	Design of Pseudoexhaustive Testable PLA with Low Overhead.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	pseudoexhaustive testable PLA, large embedded programmable logic array, low overhead PET, logic testing, built-in self test, design for testability, product lines, logic arrays, test length, area overhead
37	Edward A. Bender, Jon T. Butler	On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	product terms, nonzero output values, PLA size, realizable functions, lower bounds, logic design, upper bounds, variance, switching functions, logic arrays, minimisation of switching nets, multiple-valued functions
37	Robert P. Treuer, Vinod K. Agarwal, Hideo Fujiwara	A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	output response compression, parity bits, Built-in self test (BIST), fault models, fault coverage, VLSI design, test pattern generation, programmable logic array (PLA)
37	Sudhakar M. Reddy, Dong Sam Ha	A New Approach to the Design of Testable PLA's.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	testing, Fault detection, programmable logic array (PLA), multiple faults, testable design
37	Janusz Rajski, Jerzy Tyszer	The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	PLA testing, contact faults, fault coverage, fault masking, multiple fault detection, Combinatorial analysis
37	Yuval Tamir, Carlo H. Séquin	Design and Application of Self-Testing Comparators Implemented with MOS PLA's.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	two-rail code checker, duplication and matching, faults in VLSI circuits, MOS PLA fault model, self-testing comparator, programmable logic array, Concurrent error detection
36	Vinod K. Agarwal	Multiple Fault Detection in Programmable Logic Arrays.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	single fault coverage, Contact faults, PLA fault detection, PLA modeling, programmable logic arrays, masking, multiple fault detection
36	Venkata Rajesh Mekala, Venkata Rakesh Mekala	Methodology for Characterization of NOR-NOR Programmable Logic Array.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	H-Spice
36	Maria Kontaki, Apostolos N. Papadopoulos, Yannis Manolopoulos	Continuous Trend-Based Clustering in Data Streams.	DaWaK	2008	DBLP DOI BibTeX RDF
36	Uthman Alsaiari, Resve A. Saleh	Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy.	ISQED	2007	DBLP DOI BibTeX RDF
36	Jules White, Douglas C. Schmidt, Egon Wuchner, Andrey Nechypurenko	Automating Product-Line Variant Selection for Mobile Devices.	SPLC	2007	DBLP DOI BibTeX RDF
36	M. Cecilia Bastarrica, Sebastián Rivas, Pedro O. Rossel	From a Single Product Architecture to a Product Line Architecture.	SCCC	2007	DBLP DOI BibTeX RDF
36	Jules White, Douglas C. Schmidt	FireAnt: A Tool for Reducing Enterprise Product Line Architecture Deployment, Configuration, and Testing Costs.	ECBS	2006	DBLP DOI BibTeX RDF
36	Arvind S. Krishna, Aniruddha S. Gokhale, Douglas C. Schmidt	Context-specific middleware specialization techniques for optimizing software product-line architectures.	EuroSys	2006	DBLP DOI BibTeX RDF	middleware, product lines, specializations
36	Joanna Jedrzejowicz, Piotr Jedrzejowicz	New Upper Bounds for the Permutation Flowshop Scheduling Problem.	IEA/AIE	2005	DBLP DOI BibTeX RDF
36	Mari Matinlassi	Comparison of Software Product Line Architecture Design Methods: COPA, FAST, FORM, KobrA and QADA.	ICSE	2004	DBLP DOI BibTeX RDF
36	Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang	Performance-driven mapping for CPLD architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
36	Fan Mo, Robert K. Brayton	River PLAs: a regular circuit structure.	DAC	2002	DBLP DOI BibTeX RDF	river routing, programmable logic array
36	Charles E. Stroud, James R. Bailey, Johan R. Emmert	A New Method for Testing Re-Programmable PLAs.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	electrically erasable programmable logic array testing, manufacturing test development, bridging faults
36	Yong Liu 0012, Masaya Iwata, Tetsuya Higuchi, Didier Keymeulen	An Integrated On-Line Learning System for Evolving Programmable Logic Array Controllers.	PPSN	2000	DBLP DOI BibTeX RDF
36	D. M. Marcynuk, D. Michael Miller	The OR-k method for on-line checking of programmable logic arrays.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	fault secure design, on-line checking, concurrency, programmable logic array
36	Chidchanok Lursinsap, Daniel D. Gajski	A technique for pull-up transistor folding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
31	Adam Slowik, Jacek M. Zurada	Evolutionary Optimization of Number of Gates in PLA Circuits Implemented in VLSI Circuits.	EvoWorkshops	2009	DBLP DOI BibTeX RDF
31	Mayur Bubna, Naresh Shenoy, Santanu Chattopadhyay	An efficient greedy approach to PLA folding.	ISCAS	2008	DBLP DOI BibTeX RDF
31	Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli	Interactive presentation: Improving the fault tolerance of nanometric PLA designs.	DATE	2007	DBLP DOI BibTeX RDF
31	Tzyy-Kuen Tien, Jing-Jou Tang, Kuan-Jou Chen	A new high speed dynamic PLA.	ISCAS	2006	DBLP DOI BibTeX RDF
31	Jason Helge Anderson, Stephen Dean Brown	An LPGA with Foldable PLA-style Logic Blocks.	FPGA	1998	DBLP DOI BibTeX RDF
31	David Binger, David Knapp	Automatic synthesis of a dual-PLA controller with a counter.	MICRO	1990	DBLP BibTeX RDF