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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 47 occurrences of 39 keywords
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Results
Found 41 publication records. Showing 41 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
107 | Kewal K. Saluja, Kyuchull Kim |
Improved Test Generation for High-Activity Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 7(4), pp. 26-31, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
99 | Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui |
PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, pp. 149-155, 2002, IEEE Computer Society, 0-7695-1462-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Static Testability Measures, Dynamic Testability Measures, Test Generation, Multiple-Valued Logic, PODEM |
72 | Hi-Keung Tony Ma, Srinivas Devadas, Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli |
Logic verification algorithms and their parallel implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(2), pp. 181-189, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
72 | Hi-Keung Tony Ma, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli, Ruey-Sing Wei |
Logic Verification Algorithms and Their Parallel Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 283-290, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
72 | Sanjay J. Patel, Janak H. Patel |
Effectiveness of heuristics measures for automatic test pattern generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 547-552, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
45 | Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas |
Low power ATPG for path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 389-392, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
low power, ATPG, path delay faults, PODEM |
45 | Toshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada |
Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 171-176, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
supply current testing, D-frontier, test generation, IDDQ testing, PODEM |
45 | Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai |
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 100-, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits |
36 | Tadeu Moreira de Classe, Henrique Prado de Sá Sousa, Ronney Moreira de Castro |
Sistemas de Informação Podem Ajudar no Combate à Corrupção Através de Recursos de Transparência? Mapeamento Sistemático da Literatura. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Braz. J. Inf. Syst. ![In: Braz. J. Inf. Syst. 16(1), 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
36 | Janderson Ferreira Dutra, João Batista Firmino Júnior, Damires Yluska de Souza Fernandes |
Fatores que podem interferir no desempenho de estudantes no ENEM: uma revisão sistemática da literatura. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Revista Brasileira de Informática na Educ. ![In: Revista Brasileira de Informática na Educ. 31, pp. 323-351, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
36 | Ahmad Shabani, Bijan Alizadeh |
PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Netw. Comput. Appl. ![In: J. Netw. Comput. Appl. 167, pp. 102713, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
36 | Andréia Libório Sampaio, Clarisse Sieckenius de Souza |
Usuários podem escrever especificações de sistemas? Um estudo empírico com uma linguagem de script. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IHC ![In: VIII Simpósio Brasileiro de Fatores Humanos em Sistemas Computacionais (IHC 2008), De 21 a 24 de Outubro 2008, Porto Alegre, ANAIS (Proceedings of the VIII Brazilian Symposium on Human Factors in Computing Systems 2008, Porto Alegre, RS, Brazil, October 21-24, 2008), pp. 224-233, 2008, ACM, 978-85-7669-203-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
especificação de sistemas, extensão de sistemas, linguagens de descrição, end user programming, end user development |
36 | Prabhakar Goel, Barry C. Rosales |
PODEM-X: An automatic test generation system for VLSI logic structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 18th Design Automation Conference, DAC '81, Nashville, Tennessee, USA, June 29 - July 1, 1981, pp. 260-268, 1981, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP BibTeX RDF |
|
36 | Chen-Liang Fang, Wen-Ben Jone |
Timing optimization by gate resizing and critical path identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2), pp. 201-217, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
36 | Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer |
SWiTEST: a switch level test generation system for CMOS combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5), pp. 625-637, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
36 | Kwang-Ting Cheng, Hi-Keung Tony Ma |
On the over-specification problem in sequential ATPG algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10), pp. 1599-1604, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
36 | Debashis Bhattacharya, John P. Hayes |
A hierarchical test generation methodology for digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(2), pp. 103-123, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
high-level circuit models, test generation, fault modeling, digital circuits, hierarchical testing |
36 | Sunil Arvindam, Vipin Kumar 0001, V. Nageshwara Rao, Vineet Singh |
Automatic Test Pattern Generation on Multiprocessors: A Summary of Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KBCS ![In: Knowledge Based Computer Systems, International Conference KBCS '89, Bombay, India, December 11-13, 1989, Proceedings, pp. 41-51, 1989, Springer, 3-540-52850-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
27 | Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara |
A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 345-349, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
acceptable faults, threshold test generation, error significance, 5-valued logic, PODEM |
27 | Todd P. Kelsey, Kewal K. Saluja, Soo Young Lee |
An Efficient Algorithm for Sequential Circuit Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(11), pp. 1361-1371, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
automatic test generation algorithm, nine-valued logic model, Initial Timeframe Algorithm, Previous State Information Problem, faulty machine states, logic testing, sequential circuits, automatic testing, sequential circuit test generation, PODEM |
27 | Hideo Fujiwara, Takeshi Shimono |
On the Acceleration of Test Generation Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(12), pp. 1137-1144, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
multiple backtrace, PODEM algorithm, decision tree, test generation, sensitization, Combinational logic circuits, D-algorithm, stuck faults |
18 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001 |
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 167-172, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling |
18 | Luiz Fernando Gomes Soares, Rogério Ferreira Rodrigues, Romualdo Monteiro de Resende Costa |
Automatic building of frameworks for processing XML documents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WebMedia ![In: Proceedings of the 12th Brazilian Symposium on Multimedia and the Web, WebMedia 2006, Natal, Rio Grande do Norte, Brazil, November 19-22, 2006, pp. 118-127, 2006, ACM, 85-7669-100-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
middleware declarativo, TV digital, maestro, XML, framework, NCL, SBTVD |
18 | Elmário Gomes Dutra Jr., José Valdeni de Lima |
Supplement of partial ranks to the data fusion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WebMedia ![In: Proceedings of the 12th Brazilian Symposium on Multimedia and the Web, WebMedia 2006, Natal, Rio Grande do Norte, Brazil, November 19-22, 2006, pp. 148-154, 2006, ACM, 85-7669-100-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fusão de dados, recuperação de informação, IR |
18 | Shweta Chary, Michael L. Bushnell |
Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 818-823, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Xiaoliang Bai, Sujit Dey, Angela Krstic |
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 112-121, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Seongmoon Wang, Sandeep K. Gupta 0001 |
An automatic test pattern generator for minimizing switching activity during scan testing activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8), pp. 954-968, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Bipul Chandra Paul, Kaushik Roy 0001 |
Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 384-390, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Ilker Hamzaoglu, Janak H. Patel |
New Techniques for Deterministic Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 63-73, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
redundancy, stuck-at fault, Boolean satisfiability, automatic test generation, scan design, logic implications |
18 | Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang |
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 4(2), pp. 194-218, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Weiyu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer |
Test generation in VLSI circuits for crosstalk noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 641-650, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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18 | Seongmoon Wang, Sandeep K. Gupta 0001 |
ATPG for Heat Dissipation Minimization During Scan Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 614-619, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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18 | Bechir Ayari, Bozena Kaminska |
A new dynamic test vector compaction for automatic test pattern generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3), pp. 353-358, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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18 | Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy |
COMPACTEST: a method to generate compact test sets for combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7), pp. 1040-1049, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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18 | Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer |
Delay-fault test generation and synthesis for testability under a standard scan design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8), pp. 1217-1231, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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18 | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
Test generation and verification for highly sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5), pp. 652-667, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
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18 | Carles Ferrer 0001, Joan Oliver, Elena Valderrama |
A new switch-level test pattern generation algorithm based on single path over a graph representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 402-406, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
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18 | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
Verification of Interacting Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 213-219, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
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18 | Noriyoshi Itazaki, Kozo Kinoshita |
Test pattern generation for circuits with tri-state modules by Z-algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12), pp. 1327-1334, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
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18 | André Ivanov, Vinod K. Agarwal |
Dynamic testability measures for ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(5), pp. 598-608, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
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18 | Hi-Keung Tony Ma, Srinivas Devadas, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
Test generation for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10), pp. 1081-1093, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
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