Search results for "PODEM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
107	Kewal K. Saluja, Kyuchull Kim	Improved Test Generation for High-Activity Circuits.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
99	Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui	PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits.	ISMVL	2002	DBLP DOI BibTeX RDF	Static Testability Measures, Dynamic Testability Measures, Test Generation, Multiple-Valued Logic, PODEM
72	Hi-Keung Tony Ma, Srinivas Devadas, Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli	Logic verification algorithms and their parallel implementation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
72	Hi-Keung Tony Ma, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli, Ruey-Sing Wei	Logic Verification Algorithms and Their Parallel Implementation.	DAC	1987	DBLP DOI BibTeX RDF
72	Sanjay J. Patel, Janak H. Patel	Effectiveness of heuristics measures for automatic test pattern generation.	DAC	1986	DBLP DOI BibTeX RDF
45	Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas	Low power ATPG for path delay faults.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low power, ATPG, path delay faults, PODEM
45	Toshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada	Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	supply current testing, D-frontier, test generation, IDDQ testing, PODEM
45	Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai	Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits
36	Tadeu Moreira de Classe, Henrique Prado de Sá Sousa, Ronney Moreira de Castro	Sistemas de Informação Podem Ajudar no Combate à Corrupção Através de Recursos de Transparência? Mapeamento Sistemático da Literatura.	Braz. J. Inf. Syst.	2023	DBLP DOI BibTeX RDF
36	Janderson Ferreira Dutra, João Batista Firmino Júnior, Damires Yluska de Souza Fernandes	Fatores que podem interferir no desempenho de estudantes no ENEM: uma revisão sistemática da literatura.	Revista Brasileira de Informática na Educ.	2023	DBLP DOI BibTeX RDF
36	Ahmad Shabani, Bijan Alizadeh	PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices.	J. Netw. Comput. Appl.	2020	DBLP DOI BibTeX RDF
36	Andréia Libório Sampaio, Clarisse Sieckenius de Souza	Usuários podem escrever especificações de sistemas? Um estudo empírico com uma linguagem de script.	IHC	2008	DBLP BibTeX RDF	especificação de sistemas, extensão de sistemas, linguagens de descrição, end user programming, end user development
36	Prabhakar Goel, Barry C. Rosales	PODEM-X: An automatic test generation system for VLSI logic structures.	DAC	1981	DBLP BibTeX RDF
36	Chen-Liang Fang, Wen-Ben Jone	Timing optimization by gate resizing and critical path identification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
36	Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer	SWiTEST: a switch level test generation system for CMOS combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
36	Kwang-Ting Cheng, Hi-Keung Tony Ma	On the over-specification problem in sequential ATPG algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
36	Debashis Bhattacharya, John P. Hayes	A hierarchical test generation methodology for digital circuits.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	high-level circuit models, test generation, fault modeling, digital circuits, hierarchical testing
36	Sunil Arvindam, Vipin Kumar 0001, V. Nageshwara Rao, Vineet Singh	Automatic Test Pattern Generation on Multiprocessors: A Summary of Results.	KBCS	1989	DBLP DOI BibTeX RDF
27	Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara	A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic.	DELTA	2010	DBLP DOI BibTeX RDF	acceptable faults, threshold test generation, error significance, 5-valued logic, PODEM
27	Todd P. Kelsey, Kewal K. Saluja, Soo Young Lee	An Efficient Algorithm for Sequential Circuit Test Generation.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	automatic test generation algorithm, nine-valued logic model, Initial Timeframe Algorithm, Previous State Information Problem, faulty machine states, logic testing, sequential circuits, automatic testing, sequential circuit test generation, PODEM
27	Hideo Fujiwara, Takeshi Shimono	On the Acceleration of Test Generation Algorithms.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	multiple backtrace, PODEM algorithm, decision tree, test generation, sensitization, Combinational logic circuits, D-algorithm, stuck faults
18	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.	VTS	2007	DBLP DOI BibTeX RDF	Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling
18	Luiz Fernando Gomes Soares, Rogério Ferreira Rodrigues, Romualdo Monteiro de Resende Costa	Automatic building of frameworks for processing XML documents.	WebMedia	2006	DBLP DOI BibTeX RDF	middleware declarativo, TV digital, maestro, XML, framework, NCL, SBTVD
18	Elmário Gomes Dutra Jr., José Valdeni de Lima	Supplement of partial ranks to the data fusion.	WebMedia	2006	DBLP DOI BibTeX RDF	fusão de dados, recuperação de informação, IR
18	Shweta Chary, Michael L. Bushnell	Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
18	Xiaoliang Bai, Sujit Dey, Angela Krstic	HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk.	ITC	2003	DBLP DOI BibTeX RDF
18	Seongmoon Wang, Sandeep K. Gupta 0001	An automatic test pattern generator for minimizing switching activity during scan testing activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
18	Bipul Chandra Paul, Kaushik Roy 0001	Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.	ITC	2002	DBLP DOI BibTeX RDF
18	Ilker Hamzaoglu, Janak H. Patel	New Techniques for Deterministic Test Pattern Generation.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	redundancy, stuck-at fault, Boolean satisfiability, automatic test generation, scan design, logic implications
18	Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang	BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF
18	Weiyu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	Test generation in VLSI circuits for crosstalk noise.	ITC	1998	DBLP DOI BibTeX RDF
18	Seongmoon Wang, Sandeep K. Gupta 0001	ATPG for Heat Dissipation Minimization During Scan Testing.	DAC	1997	DBLP DOI BibTeX RDF
18	Bechir Ayari, Bozena Kaminska	A new dynamic test vector compaction for automatic test pattern generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
18	Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy	COMPACTEST: a method to generate compact test sets for combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
18	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	Delay-fault test generation and synthesis for testability under a standard scan design methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
18	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Test generation and verification for highly sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
18	Carles Ferrer 0001, Joan Oliver, Elena Valderrama	A new switch-level test pattern generation algorithm based on single path over a graph representation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
18	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Verification of Interacting Sequential Circuits.	DAC	1990	DBLP DOI BibTeX RDF
18	Noriyoshi Itazaki, Kozo Kinoshita	Test pattern generation for circuits with tri-state modules by Z-algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
18	André Ivanov, Vinod K. Agarwal	Dynamic testability measures for ATPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
18	Hi-Keung Tony Ma, Srinivas Devadas, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli	Test generation for sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF