Search results for "SDRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
128	Jelena Trajkovic, Alexander V. Veidenbaum, Arun Kejariwal	Improving SDRAM access energy efficiency for low-power embedded systems.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	embedded processors and low power, fetch buffer, write-combining buffer, SDRAM
128	Jun Shao, Brian T. Davis	The Bit-reversal SDRAM Address Mapping.	SCOPES	2005	DBLP DOI BibTeX RDF	address mapping, SDRAM, memory controller
114	Hojun Shim, Yongsoo Joo, Yongseok Choi, Hyung Gyu Lee, Naehyuck Chang	Low-energy off-chip SDRAM memory systems for embedded applications.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	Low power, memory system, SDRAM
100	Ying Xu, Aabhas S. Agarwal, Brian T. Davis	Prediction in Dynamic SDRAM Controller Policies.	SAMOS	2009	DBLP DOI BibTeX RDF	Access Control Policy, Memory Latency, SDRAM
100	Yongsoo Joo, Yongseok Choi, Hojun Shim, Hyung Gyu Lee, Kwanho Kim, Naehyuck Chang	Energy exploration and reduction of SDRAM memory systems.	DAC	2002	DBLP DOI BibTeX RDF	low power, memory system, SDRAM
91	Jiayi Zhu 0001, Peilin Liu, Dajiang Zhou	An SDRAM controller optimized for high definition video coding application.	ISCAS	2008	DBLP DOI BibTeX RDF
91	Stefano Bertazzoni, Domenico Di Giovenale, Marcello Salmeri, Arianna Mencattini, Adelio Salsano, M. Florean, Jeffery Wyss, Ricardo Rando, Silvano Lora	Monitoring Methodology for TID Damaging of SDRAM Devices based on Retention Time Analysis.	DFT	2004	DBLP DOI BibTeX RDF
86	Benny Akesson, Kees Goossens, Markus Ringhofer	Predator: a predictable SDRAM memory controller.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	predictability, system-on-chip, SDRAM, memory controller
86	Sven Heithecker, Rolf Ernst	Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements.	DAC	2005	DBLP DOI BibTeX RDF	QoS, FPGA, flow control, priorities, memory access, traffic shaping, SDRAM
86	V. Krishna Nandivada, Jens Palsberg	Efficient spill code for SDRAM.	CASES	2003	DBLP DOI BibTeX RDF	optimization, integer linear programming, SDRAM, memory layout
77	Wooyoung Jang, David Z. Pan	An SDRAM-aware router for Networks-on-Chip.	DAC	2009	DBLP DOI BibTeX RDF	Networks-on-Chip, memory, flow control, router
71	André Borin Soares, Alexsandro Cristovão Bonatto, Altamiro Amadeu Susin	A new march sequence to fit DDR SDRAM test in burst mode.	SBCCI	2008	DBLP DOI BibTeX RDF	DDR SDRAM, march algorithms, built-in self test, system on chip, memory test
64	Jesús Corbal, Roger Espasa, Mateo Valero	Command Vector Memory Systems: High Performance at Low Cost.	IEEE PACT	1998	DBLP DOI BibTeX RDF	memory systems, vector processors, SDRAM
63	Sven Heithecker, Rolf Ernst	An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
63	Simon Napper, Dian Yang	Equivalence Checking a 256MB SDRAM.	MTDT	2001	DBLP DOI BibTeX RDF
63	Binu K. Mathew, Sally A. McKee, John B. Carter, Al Davis	Design of a Parallel Vector Access Unit for SDRAM Memory Systems.	HPCA	2000	DBLP DOI BibTeX RDF
59	Richard H. Stern	Coming down the home stretch in the Rambus standardization skullduggery saga: To levy or not to levy royalties.	IEEE Micro	2007	DBLP DOI BibTeX RDF	Rambus, antitrust violation, skullduggery, Secret Squirrel, DDR SDRAM, JEDEC, standardization, law, patents, SDRAM
57	Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo Kim, Soonhoi Ha	Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems.	CASES	2007	DBLP DOI BibTeX RDF	dual-port SDRAM, mobile embedded system, memory architecture
57	Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Erik Brockmeyer, Francky Catthoor, Mary Jane Irwin	Estimating influence of data layout optimizations on SDRAM energy consumption.	ISLPED	2003	DBLP DOI BibTeX RDF	Ehrhart polynomial, Omega calculator, page break, energy, data locality, data layout, Presburger arithmetic, SDRAM
56	Scott Rixner	Memory Controller Optimizations for Web Servers.	MICRO	2004	DBLP DOI BibTeX RDF
49	Wooyoung Jang, David Z. Pan	Application-aware NoC design for efficient SDRAM access.	DAC	2010	DBLP DOI BibTeX RDF	QoS, memory, flow control, router, NoC, on-chip communication
49	Xin Yang 0010, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.	High performance IP lookup circuit using DDR SDRAM.	SoCC	2008	DBLP DOI BibTeX RDF
49	Seiji Miura, Satoru Akiyama	A memory controller that reduces latency of cached SDRAM.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
49	Paul Marchal, José Ignacio Gómez, Luis Piñuel, Davide Bruni, Luca Benini, Francky Catthoor, Henk Corporaal	SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.	DATE	2003	DBLP DOI BibTeX RDF
49	Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Steen Pedersen	Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off.	CODES	2000	DBLP DOI BibTeX RDF	case study, memory architecture, 3D graphics
43	Seiji Miura, Kazushige Ayukawa, Takao Watanabe	A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU.	ISLPED	2001	DBLP DOI BibTeX RDF	SDRAM controller, active-standby mode, standby mode
42	Leonardo Luiz Ecco	Architecture and Performance Analysis of a Multi-Generation SDRAM Controller for Mixed Criticality Systems (Architektur- und Leistungsanalyse eines Mehgenerationen-SDRAM-Controllers für gemischte Kritikalitätssysteme) (PDF / PS)		2018	DOI RDF
42	Eleftherios Kyriakakis, Kalle Ngo, Johnny Öberg	Mitigating single-event upsets in COTS SDRAM using an EDAC SDRAM controller.	NORCAS	2017	DBLP DOI BibTeX RDF
42	Youn-Sik Park, Sung-Wook Lee, Bai-Sun Kong, Kwang-Il Park, Jeong-Don Ihm, Joo-Sun Choi, Young-Hyun Jun	PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion.	ISCAS	2008	DBLP DOI BibTeX RDF
42	Jun Shao, Brian T. Davis	A Burst Scheduling Access Reordering Mechanism.	HPCA	2007	DBLP DOI BibTeX RDF
42	Hongqi Hu, Jiadong Xu, Zhemin Duan, Jingnan Sun	High Efficiency Synchronous DRAM Controller for H.264 HDTV Encoder.	SiPS	2007	DBLP DOI BibTeX RDF
42	Séamas McGettrick, Dermot Geraghty, Ciarán McElroy	Searching the Web with an FPGA Based Search Engine.	ARC	2007	DBLP DOI BibTeX RDF
42	Zude Zhou, Songlin Cheng, Quan Liu	Application of DDR Controller for High-speed Data Acquisition Board.	ICICIC (2)	2006	DBLP DOI BibTeX RDF
42	Kartik Mohanram, Scott Rixner	Context-Independent Codes for Off-Chip Interconnects.	PACS	2004	DBLP DOI BibTeX RDF
35	Sean Whitty, Rolf Ernst	A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture.	IPDPS	2008	DBLP DOI BibTeX RDF
35	Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu	SDRAM Delay Fault Modeling and Performance Testing.	VTS	2007	DBLP DOI BibTeX RDF
35	Kangmin Lee, Chi Weon Yoon, Ramchan Woo, Jeong-Hun Kook, Ja-Il Koo, Tae-Sung Jung, Hoi-Jun Yoo	A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
28	Yu-Wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Hung-Chi Fang, Liang-Gee Chen	124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory.	IEEE Trans. Circuits Syst. Video Technol.	2007	DBLP DOI BibTeX RDF
28	Soo Yun Hwang, Hyeong Jun Park, Kyoung Son Jhang	An implementation and performance analysis of slave-side arbitration schemes for the ML-AHB BusMatrix.	SAC	2007	DBLP DOI BibTeX RDF	arbitration scheme, multi-layer AHB BusMatrix, slave-side arbitration, system on a chip, on chip bus
28	Matthew E. Tolentino, Joseph Turner, Kirk W. Cameron	Memory-miser: a performance-constrained runtime system for power-scalable clusters.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	resource allocation, control, power management, memory
28	Amilcar do Carmo Lucas, Sven Heithecker, Peter Rüffer, Rolf Ernst, Holger Rückert, Gerhard Wischermann, Karin Gebel, Reinhard Fach, Wolfgang Huther, Stefan Eichner, Gunter Scheller	A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications.	DATE	2006	DBLP DOI BibTeX RDF	digital film, stream-based architecture, weak-programming, FPGA, motion-estimation, reconfigurable
28	David Wang 0003, Brinda Ganesh, Nuengwong Tuaycharoen, Kathleen Baynes, Aamer Jaleel, Bruce L. Jacob	DRAMsim: a memory system simulator.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
28	Kun-Bin Lee, Tzu-Chieh Lin, Chein-Wei Jen	An Efficient Quality-Aware Memory Controller for Multimedia Platform SoC.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
28	Soon-Tak Lee, Joong-Hwan Baek	Predictive Directional Rectangular Zonal Search for Digital Multimedia Processor.	PCM (1)	2005	DBLP DOI BibTeX RDF
28	Tomás Marek, Martin Novotný, Ludek Crha	Design and Implementation of the Memory Scheduler for the PC-Based Router.	FPL	2004	DBLP DOI BibTeX RDF
28	Chanik Park, Jeong-Uk Kang, Seon-Yeong Park, Jinsoo Kim 0001	Energy-aware demand paging on NAND flash-based embedded storages.	ISLPED	2004	DBLP DOI BibTeX RDF	embedded storages, page replacemen, embedded systems, virtual memory, NAND flash memory, demand paging
28	Shih-Lien Lu, Konrad Lai	Implementation of HW$im - A Real-Time Configurable Cache Simulator.	FPL	2003	DBLP DOI BibTeX RDF
28	Jörg E. Vollrath	Output Timing Measurement Using an Idd Method.	MTDT	2003	DBLP DOI BibTeX RDF	DDR, timing, DRAM
28	Richard H. Stern	FTC Piles onto Rambus' Standardization Skullduggery.	IEEE Micro	2002	DBLP DOI BibTeX RDF
28	Richard H. Stern	Another Update on Standardization Skullduggery.	IEEE Micro	2001	DBLP DOI BibTeX RDF
28	Panagiotis Stogiannos, Apostolos Dollas, Vassilios Digalakis	A Configurable Logic Based Architecture for Real-Time Continuous Speech Recognition Using Hidden Markov Models.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
28	Jean-Michel Raczinski, Stéphane Sladek	The Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing.	FPL	2000	DBLP DOI BibTeX RDF
22	Benny Akesson, Williston Hayes Jr., Kees Goossens	Classification and Analysis of Predictable Memory Patterns.	RTCSA	2010	DBLP DOI BibTeX RDF	memory patterns, burst count, classification, predictability, SDRAM, memory controller
22	Daniel Schmidt 0001, Norbert Wehn	DRAM power management and energy consumption: a critical assessment.	SBCCI	2009	DBLP DOI BibTeX RDF	modelling, measurement, power management, SDRAM
22	Min Lee, Euiseong Seo, Joonwon Lee, Jinsoo Kim 0001	PABC: Power-Aware Buffer Cache Management for Low Power Consumption.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	PAVM, energy management, Buffer cache, SDRAM
22	Youngjin Cho, Naehyuck Chang	Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling.	ISLPED	2004	DBLP DOI BibTeX RDF	low power, memory system, SDRAM
22	Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge	High-Performance DRAMs in Workstation Environments.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	DRAM architectures, DRAM performance, DRAM systems, DDR DRAM, Direct Rambus DRAM, PC100 SDRAM, DDR2 DRAM, system modeling
21	IkJoon Choi, Seunghwan Hong, Kihyun Kim, Jeongsik Hwang, Seunghan Woo, Young-Sang Kim, Cheongryong Cho, Eun-Young Lee, Hun-Jae Lee, Min-Su Jung, Hee-Yun Jung, Ju-Seong Hwang, Junsub Yoon, Wonmook Lim, Hyeong-Jin Yoo, Won-Ki Lee, Jung-Kyun Oh, Dong-Su Lee, Jong-Eun Lee, Jun-Hyung Kim, Young-Kwan Kim, Su-Jin Park, Byung-Kyu Ho, Byongwook Na, Hye-In Choi, Chung-Ki Lee, Soo-Jung Lee, Hyunsung Shin, Young-Kyu Lee, Jang-Woo Ryu, Sangwoong Shin, Sungchul Park, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, SangJoon Hwang	13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.	ISSCC	2024	DBLP DOI BibTeX RDF
21	Yindong Xiao, Gongbai Xiao, Ke Liu 0005, Zaiming Fu, Houjun Wang	Constraint Models of SDRAM-Based Arbitrary Waveform Generator.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
21	Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-Il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jung-Bum Shin, Yanggyoon Loh, Chang-Yong Lee, Junmyung Woo, Hye-Seung Yu, Changhyun Bae, Reum Oh, Young-Soo Sohn, Changsik Yoo, Jooyoung Lee	A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL.	ISSCC	2023	DBLP DOI BibTeX RDF
21	Feng Dan Lin, Kang Leo Zhao	Receiver Characterization with On-Die Eye Monitor (ODEM) in LPDDR5 and DDR5 SDRAM.	ASICON	2023	DBLP DOI BibTeX RDF
21	Hyun-A. Ahn, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Garam Choi, Jun-Seo Park, Bo-Hyeon Lee, Jin-Hyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Changsik Yoo, Tae-Young Oh	A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications.	A-SSCC	2023	DBLP DOI BibTeX RDF
21	Phil Murray, Feras Al-Hawari	Challenges in implementing DDR3 memory interface on PCB systems: a methodology for interfacing DDR3 SDRAM DIMM to an FPGA.	CoRR	2022	DBLP DOI BibTeX RDF
21	Xiaofeng Yang, Ancheng Liu, Jinjin Wang	High Speed Multi-channel Data Cache Design Based on DDR3 SDRAM.	AIPR	2022	DBLP DOI BibTeX RDF
21	Dae-Hyun Kim 0003, Byungkyu Song, Hyun-A. Ahn, Woongjoon Ko, Sung-Geun Do, Seokjin Cho, Kihan Kim, Seung-Hoon Oh, Hye-Yoon Joo, Geuntae Park, Jin-Hun Jang, Yong-Hun Kim, Donghun Lee, Jaehoon Jung, Yongmin Kwon, Youngjae Kim, Jaewoo Jung, Seongil O, Seoulmin Lee, Jaeseong Lim, Junho Son, Jisu Min, Haebin Do, Jaejun Yoon, Isak Hwang, Jinsol Park, Hong Shim, Seryeong Yoon, Dongyeong Choi, Jihoon Lee, Soohan Woo, Eunki Hong, Junha Choi, Jae-Sung Kim, Sangkeun Han, Jong-Min Bang, Bokgue Park, Jang-Hoo Kim, Seouk-Kyu Choi, Gong-Heum Han, Yoo-Chang Sung, Wonil Bae, Jeong-Don Lim, Seungjae Lee, Changsik Yoo, Sang Joon Hwang, Jooyoung Lee	A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.	ISSCC	2022	DBLP DOI BibTeX RDF
21	Alfonso Mascareñas González, Jean-Baptiste Chaudron, Frédéric Boniol, Youcef Bouchebaba, Jean-Loup Bussenot	Task and Memory Mapping Optimization for SDRAM Interference Minimization on Heterogeneous MPSoCs.	ETFA	2022	DBLP DOI BibTeX RDF
21	Alfonso Mascareñas González, Jean-Baptiste Chaudron, Frédéric Boniol, Youcef Bouchebaba, Jean-Loup Bussenot	Towards an efficient cost function equation for DDR SDRAM interference analysis on heterogeneous MPSoCs.	DS-RT	2022	DBLP DOI BibTeX RDF
21	Chang-Kyo Lee, Hyung-Joon Chi, Jin-Seok Heo, Junghwan Park, Jin-Hun Jang, Dongkeon Lee, Jaehoon Jung, Dong-Hun Lee, Dae-Hyun Kim 0003, Kihan Kim, Sang-Yun Kim 0001, Dukha Park, Youngil Lim, Geuntae Park, Seungjun Lee, Seungki Hong, Dae-Hyun Kwon, Isak Hwang, Byongwook Na, Kyungryun Kim, Seouk-Kyu Choi, Hye-In Choi, Hangi-Jung, Wonil Bae, Jeong-Don Ihm, Seung-Jun Bae, Nam Sung Kim, Jung-Bae Lee	An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
21	Alfonso Mascareñas González, Frédéric Boniol, Youcef Bouchebaba, Jean-Loup Bussenot, Jean-Baptiste Chaudron	Heterogeneous multicore SDRAM interference analysis.	RTNS	2021	DBLP DOI BibTeX RDF
21	Yong-Hun Kim, Hyung-Jin Kim, Jaemin Choi, Min-Su Ahn, Dongkeon Lee, Seung-Hyun Cho, Dong-Yeon Park, Young-Jae Park, Min-Soo Jang, Yong-Jun Kim, Jinyong Choi, Sung-Woo Yoon, Jae-Woo Jung, Jae-Koo Park, Jae-Woo Lee, Dae-Hyun Kwon, Hyung-Seok Cha, Si-Hyeong Cho, Seong-Hoon Kim, Jihwa You, Kyoung-Ho Kim, Dae-Hyun Kim 0003, Byung-Cheol Kim, Young-Kwan Kim, Jun-Ho Kim, Seouk-Kyu Choi, Chanyoung Kim, Byongwook Na, Hye-In Choi, Reum Oh, Jeong-Don Ihm, Seung-Jun Bae, Nam Sung Kim, Jung-Bae Lee	25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM.	ISSCC	2021	DBLP DOI BibTeX RDF
21	Seunghwan Hong, Chang-Hyun Bae, Yoo-Chang Sung, Jaewoong Kim, Junsub Yoon, Sangwoo Kim, Jin-Hyeok Baek, Cheongryong Cho, Useung Shin, Sang-Kyeom Kim, Hwan-Chul Jung, Ho-Jun Chang, Jang-Hoo Kim, Jeongsik Hwang, Hyunki Kim, Ki-Won Lee, Dongmin Kim, Han-Ki Jeong, Myung-O. Kim, Kyomin Sohn, Jeong-Don Ihm, Changsik Yoo, Sang Joon Hwang	A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
21	Yanwu Du, Chris Eom, Jake Jung, Brian Lee 0003, Edwin Kim, Kanyu Cao	Adaptive OCD and ODT Control for Channel S/I Enhancement in DDR4 SDRAM.	ASICON	2021	DBLP DOI BibTeX RDF
21	Seunggyu Lee, Jongho Yoon, Jakang Lee, Seokhyeong Kang	Giga-sample Data Acquisition Method for High-speed DDR5 SDRAM.	ISOCC	2021	DBLP DOI BibTeX RDF
21	Dongkyun Kim, Kibong Koo, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Ki Hun Kwon, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Jong-Sam Kim, Seungwook Oh, Minsu Park, Dain Im, Yongsung Lee, Mingyu Park, Jonghyuck Choi, Junhyun Chun, Kyowon Jin, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Changhyun Kim, Minsik Han	A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
21	Kyung-Soo Ha, Seungseob Lee, Youn-Sik Park, Hyuck-Joon Kwon, Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Hyong-Ryol Hwang, Dukha Park, Young-Hwa Kim, Young Hoon Son, Byongwook Na	A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
21	Hyung-Joon Chi, Chang-Kyo Lee, Junghwan Park, Jin-Seok Heo, Jaehoon Jung, Dongkeon Lee, Dae-Hyun Kim 0003, Dukha Park, Kihan Kim, Sang-Yun Kim 0001, Jinsol Park, Hyunyoon Cho, Sukhyun Lim, YeonKyu Choi, Youngil Lim, Daesik Moon, Geuntae Park, Jin-Hun Jang, Kyungho Lee, Isak Hwang, Cheol Kim, Younghoon Son, Gil-Young Kang, Kiwon Park, Seungjun Lee, Su-Yeon Doo, Chang-Ho Shin, Byongwook Na, Ji-Suk Kwon, Kyung Ryun Kim, Hye-In Choi, Seouk-Kyu Choi, Soobong Chang, Wonil Bae, Hyuck-Joon Kwon, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee	22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.	ISSCC	2020	DBLP DOI BibTeX RDF
21	Chenguang Guo, Jiancheng Xu, Wenyao Xu	Highly efficient design of SDRAM-based CTM for real-time SAR imaging system.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
21	Vladimir M. Milovanovic, Darko M. Tasovac	A Customizable DDR3 SDRAM Controller Tailored for FPGA-Based Data Buffering Inside Real-Time Range-Doppler Radar Signal Processing Back Ends.	EUROCON	2019	DBLP DOI BibTeX RDF
21	Dan Gui	Data Storage and Simulation Based on FPGA and DDR SDRAM for Super-Resolution Localization Microscopy.	ICITEE	2019	DBLP DOI BibTeX RDF
21	Kyung-Soo Ha, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Jin-Hun Jang, Hyong-Ryol Hwang, Hyung-Joon Chi, Junghwan Park, Seungjun Shin, Dukha Park, Sang-Yun Kim 0001, Sukhyun Lim, Kiwon Park, YeonKyu Choi, Young-Hwa Kim, Younghoon Son, Hyunyoon Cho, Byongwook Na, Hyo-Joo Ahn, Seungseob Lee, Seouk-Kyu Choi, Youn-Sik Park, Seok-Hun Hyun, Soobong Chang, Hyuck-Joon Kwon, Jung-Hwan Choi, Tae-Young Oh, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang	A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.	ISSCC	2019	DBLP DOI BibTeX RDF
21	Dongkyun Kim, Minsu Park, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Jaeil Kim, Changhyun Kim, Kyung Whan Kim, Kibong Koo, Seonghwi Song, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Dae Suk Kim, Ki Hun Kwon, Minsik Han, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Yeonuk Kim, Jong-Sam Kim, Sanghui Kim, Youngsuk Seo, Seungwook Oh, Dain Im, Haksong Kim, Jonghyuck Choi, Jinil Chung, Changhyun Lee, Yongsung Lee, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh	A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.	ISSCC	2019	DBLP DOI BibTeX RDF
21	Jin-Seok Heo, Kihan Kim, Dong-Hoon Lee, Chang-Kyo Lee, Daesik Moon, Kiho Kim, Jin-Hyeok Baek, Sung-Woo Yoon, Hui-Kap Yang, Kyungryun Kim, Youngjae Kim, Bokgue Park, Su-Jin Park, Joung-Wook Moon, Jae-Hyung Lee, Yun-Sik Park, Soobong Jang, Seok-Hun Hyun, Hyuck-Joon Kwon, Jung-Hwan Choi, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee	A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
21	Chang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Jin-Hyeok Baek, Gil-Hoon Cha, Daesik Moon, Dong-Hun Lee, Jong-Wook Park, Seunseob Lee, Si-Hyeong Cho, Young-Ryeol Choi, Kyung-Soo Ha, Eunsung Seo, Youn-Sik Park, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang	Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
21	Jianfei Wu, Wei Zhu, Binhong Li, Yafei Li, Hongyi Wang 0003, Mengjun Wang	Investigations on immunity of interfaces between intelligent media processor and DDR3 SDRAM memory.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
21	Hoang T. Nguyen, Axel Rodriguez, Frederic Wrobel, Alain Michez, Francoise Bezerra, Nathalie Chatry, Benjamin Vandevelde	TCAD simulation of radiation-induced leakage current in 1T1C SDRAM.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
21	Seokbo Shim, Sungho Kim, Jooyoung Bae, Keunsik Ko, Eunryeong Lee, Kwidong Kim, Kyeongtae Kim, Sangho Lee, Jinhoon Hyun, Insung Koh, Joonhong Park, Minjeong Kim, Sunhye Shin, Dongha Lee, Yunyoung Lee, Sangah Hyun, Wonjohn Choi, Dain Im, Dongheon Lee, Jieun Jang, Junhyun Chun, Jonghoon Oh, Jinkook Kim, Seok Hee Lee	A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with improved power distribution and repair strategy.	ISSCC	2018	DBLP DOI BibTeX RDF
21	Ki Chul Chun, Yong-Gyu Chu, Jin-Seok Heo, Tae-Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sang-uhn Cha, Hyung-Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim 0001, Won-Jun Choi, Dae-Sik Yim, Inkyu Moon, Young-Ju Kim 0003, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong-Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Youngjae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seung-Bum Ko, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang	A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.	ISSCC	2018	DBLP DOI BibTeX RDF
21	Narasinga Rao Miniskar, Sirish Kumar Pasupuleti, Vasanthakumar Rajagopal, Ashok Vishnoi, Chandra Kumar Ramasamy, Raj Narayana Gadde	Optimal SDRAM Buffer Allocator for Efficient Reuse of Layer IO in CNNs Inference Framework.	ISCAS	2018	DBLP DOI BibTeX RDF
21	Joung-Wook Moon, Hye-Sung Yoo, Hundai Choi, Il-Won Park, Seok-Yong Kang, Jun-Bae Kim, Haeyoung Chung, Kiho Kim, Dong-Hun Lee, Ki-Jae Song, Seok-Hun Hyun, Indal Song, Young-Soo Sohn, Yong-Ho Cho, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang	An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM.	A-SSCC	2018	DBLP DOI BibTeX RDF
21	Leonardo Ecco, Rolf Ernst	Tackling the Bus Turnaround Overhead in Real-Time SDRAM Controllers.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
21	Martin Versen, W. Ernst, Prince Gulati	A row hammer pattern analysis of DDR2 SDRAM.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
21	Jungtaek You, Junyoung Song, Chulwoo Kim	A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
21	Leonardo Ecco, Rolf Ernst	Architecting high-speed command schedulers for open-row real-time SDRAM controllers.	DATE	2017	DBLP DOI BibTeX RDF
21	Chang-Kyo Lee, Yoon-Joo Eom, Jin-Hee Park, Junha Lee, Hye-Ran Kim, Kihan Kim, Young Choi, Ho-Jun Chang, Jonghyuk Kim, Jong-Min Bang, Seungjun Shin, Hanna Park, Su-Jin Park, Young-Ryeol Choi, Hoon Lee, Kyong-Ho Jeon, Jae-Young Lee, Hyo-Joo Ahn, Kyoung-Ho Kim, Jung-Sik Kim, Soobong Chang, Hyong-Ryol Hwang, Duyeul Kim, Yoon-Hwan Yoon, Seok-Hun Hyun, Joon-Young Park, Yoon-Gyu Song, Youn-Sik Park, Hyuck-Joon Kwon, Seung-Jun Bae, Tae-Young Oh, Indal Song, Yong-Cheol Bae, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin	23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.	ISSCC	2017	DBLP DOI BibTeX RDF
21	Hye-Jung Kwon, Eunsung Seo, ChangYong Lee, Young-Hun Seo, Gong-Heum Han, Hye-Ran Kim, Jong-Ho Lee, Min-Su Jang, Sung-Geun Do, Seung-Hyun Cho, Jae-Koo Park, Su-Yeon Doo, Jung-Bum Shin, Sang-Hoon Jung, Hyoung-Ju Kim, In-Ho Im, Beob-Rae Cho, Jaewoong Lee, Jae-Youl Lee, Ki-Hun Yu, Hyung-Kyu Kim, Chul-Hee Jeon, Hyun-Soo Park, Sang-Sun Kim, Seok-Ho Lee, Jong-Wook Park, Seung-Sub Lee, Bo-Tak Lim, Jun-Young Park, Yoon-Sik Park, Hyuk-Jun Kwon, Seung-Jun Bae, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin	23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.	ISSCC	2017	DBLP DOI BibTeX RDF
21	Nohhyup Kwak, Saeng-Hwan Kim, Kyong Ha Lee, Chang-Ki Baek, Mun Seon Jang, Yongsuk Joo, Seung-Hun Lee, Wooyoung Lee, Eunryeong Lee, Donghee Han, Jaeyeol Kang, Jung Ho Lim, Jae-Beom Park, Kyung-Tae Kim, Sunki Cho, Sung Woo Han, Jee Yeon Keh, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee	23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications.	ISSCC	2017	DBLP DOI BibTeX RDF
21	Chang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Gil-Hoon Cha, Jin-Hyeok Baek, Daesik Moon, Yoon-Joo Eom, Tae-Sung Kim, Hyunyoon Cho, Young Hoon Son, Seonghwan Kim 0002, Jong-Wook Park, Sewon Eom, Si-Hyeong Cho, Young-Ryeol Choi, Seungseob Lee, Kyoung-Soo Ha, Youngseok Kim, Bo-Tak Lim, Dae-Hee Jung, Eungsung Seo, Kyoung-Ho Kim, Yoon-Gyu Song, Youn-Sik Park, Tae-Young Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Joon-Young Park, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang	Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM.	A-SSCC	2017	DBLP DOI BibTeX RDF
21	Sven Goossens, Karthik Chandrasekar 0001, Benny Akesson, Kees Goossens	Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
21	Kyungbae Park, Chul Seung Lim, Donghyuk Yun, Sanghyeon Baeg	Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 × nm technology.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
21	Tae-Young Oh, Hoeju Chung, Jun-Young Park, Ki-Won Lee, Seung-Hoon Oh, Su-Yeon Doo, Hyoung-Joo Kim 0002, ChangYong Lee, Hye-Ran Kim, Jong-Ho Lee, Jin-Il Lee, Kyung-Soo Ha, Young-Ryeol Choi, Young-Chul Cho, Yong-Cheol Bae, Taeseong Jang, Chulsung Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi	A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF