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Found 96 publication records. Showing 96 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
64 | Robert Law |
Using student blogs for documentation in software development projects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITiCSE ![In: Proceedings of the 16th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, ITiCSE 2011, Darmstadt, Germany, June 27-29, 2011, pp. 366, 2011, ACM, 978-1-4503-0697-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
33 | Ping Gui, Fouad E. Kiamilev, Xiaoqing Wang, Michael J. MacFadden, Xingle Wang, Nick Waite, Michael W. Haney, Charlie Kuznia |
A Source-Synchronous Double-Data-Rate Parallel Optical Transceiver IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(7), pp. 833-842, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Ganesh Balamurugan, Naresh R. Shanbhag |
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 254-260, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | David C. Keezer, Dany Minier, Patrice Ducharme |
Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(1), pp. 46-57, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
control structure reliability, multi-gigahertz testing, picosecond timing accuracy, jitter-tolerance testing, jitter injection, fault tolerance, testing |
26 | Bernd Laquai, Martin Hua, Guido Schulze, Michael Braun |
A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 97-102, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Darren Aaberge, Ken Mockler, Dieu Van Dinh, Raoul Belleau, Tim Donovan, Reid Hewlitt |
Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 75-84, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RapidIO, Source-Synchronous, LVDS, Differential, ATE, Non-determinism |
24 | A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson |
Tester Architecture For The Source Synchronous Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 738-747, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Andres Ayes, Eby G. Friedman |
Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 93, pp. 102066, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Kartik Mohanram, Nur A. Touba |
Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 121-127, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Youn-Sik Park, Sung-Wook Lee, Bai-Sun Kong, Kwang-Il Park, Jeong-Don Ihm, Joo-Sun Choi, Young-Hyun Jun |
PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1902-1905, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Jongsun Kim, Ingrid Verbauwhede, M.-C. Frank Chang |
Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 881-894, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Sebastian Fischer, Amir Najafi 0001, Alberto García Ortiz |
Wave-Pipelined Source-Synchronous Circuit-Switched Data Transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 12th International Conference on Modern Circuits and Systems Technologies, MOCAST 2023, Athens, Greece, June 28-30, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2107-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Yang-Hang Fan, Ankur Kumar, Takayuki Iwai, Ashkan Roshan-Zamir, Shengchang Cai, Bo Sun, Samuel Palermo |
A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 55(2), pp. 439-451, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Oscar Yu, Cheng-Wei Chen, Chih-Shen Yeh, Jih-Sheng Lai 0001 |
Sequential Parallel Switching for Drain-Source Synchronous Rectification Efficiency Boost in Parallel Switch Rectifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. ![In: IEEE Trans. Circuits Syst. 67-II(11), pp. 2637-2641, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Christopher Williams 0003, Diaaeldin Abdelrahman, Xiangdong Jia, Abdullah Ibn Abbas, Glenn E. R. Cowan, Odile Liboiron-Ladouceur |
Reconfiguration in Source-Synchronous Receivers for Short-Reach Parallel Optical Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Christopher Williams 0003, Diaaeldin Abdelrahman, Xiangdong Jia, Abdullah Ibn Abbas, Odile Liboiron-Ladouceur, Glenn E. R. Cowan |
Reconfiguration in Source-Synchronous Receivers for Short-Reach Parallel Optical Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(7), pp. 1548-1560, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Shunli Ma, Hao Yu 0001, Qun Jane Gu, Junyan Ren |
A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2), pp. 555-568, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Yang-Hang Fan, Ankur Kumar, Takayuki Iwai, Ashkan Roshan-Zamir, Shengchang Cai, Bo Sun, Samuel Palermo |
A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019, pp. 1-4, 2019, IEEE, 978-1-5386-9395-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Cosimo Aprile, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl |
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(3), pp. 861-872, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu |
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(3), pp. 884-895, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim |
A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(11), pp. 1564-1568, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Pil-Ho Lee, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang |
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(4), pp. 1386-1396, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Timothy O. Dickson, Yong Liu 0023, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman |
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(8), pp. 1744-1755, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
13 | Kunzhi Yu, Cheng Li, Hao Li 0047, Alex Titriku, Ayman Shafik, Binhao Wang, Zhongkai Wang, Rui Bai 0001, Chin-Hui Chen, Marco Fiorentino, Patrick Yin Chiang, Samuel Palermo |
A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(9), pp. 2129-2141, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
13 | Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu |
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, pp. 398-399, 2016, IEEE, 978-1-4673-9466-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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13 | Gregory K. Chen, Mark A. Anders 0001, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal 0001, Ram Krishnamurthy 0001, Vivek De, Shekhar Borkar |
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(1), pp. 59-67, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
13 | Timothy O. Dickson, Yong Liu 0023, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman |
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(8), pp. 1917-1931, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
13 | Shuai Yuan 0005, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Peng Wang, Wen Jia, Chun Zhang, Zhihua Wang 0001 |
A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference, Graz, Austria, September 14-18, 2015, pp. 144-147, 2015, IEEE, 978-1-4673-7470-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
13 | Timothy O. Dickson, Yong Liu 0023, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman |
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8682-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
13 | Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu |
3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-4799-6223-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
13 | Kunzhi Yu, Hao Li 0047, Cheng Li, Alex Titriku, Ayman Shafik, Binhao Wang, Zhongkai Wang, Rui Bai 0001, Chin-Hui Chen, Marco Fiorentino, Patrick Yin Chiang, Samuel Palermo |
22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-4799-6223-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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13 | Lizhou Wu, Nong Xiao, Fang Liu 0002, Yimo Du, Shuo Li 0007, Yang Ou |
Dysource: a high performance and scalable NAND flash controller architecture based on source synchronous interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 12th ACM International Conference on Computing Frontiers, CF'15, Ischia, Italy, May 18-21, 2015, pp. 25:1-25:8, 2015, ACM, 978-1-4503-3358-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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13 | Kyongsu Lee, Jae-Yoon Sim |
Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(10), pp. 2093-2102, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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13 | Yoon Seok Yang, Reeshav Kumar, Gwan S. Choi, Paul V. Gratz |
WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 19(4), pp. 34:1-34:22, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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13 | Shuai Yuan 0005, Ziqiang Wang, Xuqiang Zheng, Ke Huang 0003, Ni Xu, Woogeun Rhee, Liji Wu, Chun Zhang |
A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 61-II(4), pp. 209-213, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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13 | Woo-Rham Bae, Deog-Kyoon Jeong, Byoung-Joo Yoo |
A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, pp. 55-58, 2014, IEEE Computer Society, 978-1-4799-4560-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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13 | Timothy O. Dickson, Yong Liu 0023, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman |
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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13 | Gregory K. Chen, Mark A. Anders 0001, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal 0001, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De |
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014, pp. 276-277, 2014, IEEE, 978-1-4799-0918-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
13 | Tao Li, Greg Sadowski |
Design and implementation of novel source synchronous interconnection in modern GPU chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 27th IEEE International System-on-Chip Conference, SOCC 2014, Las Vegas, NV, USA, September 2-5, 2014, pp. 130-135, 2014, IEEE, 978-1-4799-3378-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
13 | Ashok Jaiswal |
Source-synchronous I/O Links using Adaptive Interface Training for High Bandwidth Applications (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2014 |
RDF |
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13 | Peter Gillingham, David Chinn, Eric Choi, Jin-Ki Kim, Don MacDonald, Hakjune Oh, Hong-Beom Pyeon, Roland Schuetz |
800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 1, pp. 811-816, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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13 | Jang-Woo Lee, Hong-Jung Kim, Chun-Seok Jeong, Jae-Jin Lee, Changsik Yoo |
Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(11), pp. 2155-2159, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
13 | Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra |
Exploring topologies for source-synchronous ring-based network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pp. 1026-1031, 2013, EDA Consortium San Jose, CA, USA / ACM DL, 978-1-4503-2153-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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13 | Ashok Jaiswal, Yuan Fang, Peter Gregorius, Klaus Hofmann |
Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013, pp. 752-758, 2013, IEEE Computer Society, 978-1-4799-2978-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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13 | Yuan Fang, Ashok Jaiswal, Klaus Hofmann |
Low-power signal integrity trainings for multi-clock source-synchronous memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013, pp. 319-324, 2013, IEEE, 978-1-4799-1166-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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13 | Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra |
A source-synchronous Htree-based network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013, pp. 161-166, 2013, ACM, 978-1-4503-2032-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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13 | Kunzhi Yu, Xuqiang Zheng, Ke Huang 0003, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang 0001 |
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013, pp. 1-4, 2013, IEEE, 978-1-4673-4435-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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13 | Timothy O. Dickson, Yong Liu 0023, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman |
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 47(4), pp. 884-896, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
13 | Ke Huang 0003, Ziqiang Wang, Xuqiang Zheng, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang 0001 |
A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012, pp. 932-935, 2012, IEEE, 978-1-4673-2526-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
13 | Hyunjin Kim, Jacob A. Abraham |
On-chip source synchronous interface timing test scheme with calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, pp. 1146-1149, 2012, IEEE, 978-1-4577-2145-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
13 | Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra |
A fast, source-synchronous ring-based network-on-chip design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, pp. 1489-1494, 2012, IEEE, 978-1-4577-2145-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
13 | Dennis Walter, Sebastian Höppner, Holger Eisenreich, Georg Ellguth, Stephan Henker, Stefan Hänzsche, René Schüffny, Markus Winter 0002, Gerhard P. Fettweis |
A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, pp. 180-182, 2012, IEEE, 978-1-4673-0376-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
13 | Yoon Seok Yang, Reeshav Kumar, Gwan Choi, Paul Gratz |
WaveSync: A low-latency source synchronous bypass network-on-chip architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012, pp. 241-248, 2012, IEEE Computer Society, 978-1-4673-3051-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
13 | Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra |
Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012, pp. 482-483, 2012, IEEE Computer Society, 978-1-4673-3051-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
13 | Ke Huang 0003, Chen Jia, Xuqiang Zheng, Ni Xu, Chun Zhang, Woogeun Rhee, Zhihua Wang 0001 |
A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 313-316, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
13 | Shijie Hu, Chen Jia, Ke Huang 0003, Chun Zhang, Xuqiang Zheng, Zhihua Wang 0001 |
A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 309-312, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
13 | Carl Edward Gray |
An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2012 |
RDF |
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13 | Masum Hossain, Anthony Chan Carusone |
7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 46(6), pp. 1337-1348, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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13 | Jared Zerbe, Barry Daly, Lei Luo 0006, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi T. Kollipara |
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 46(4), pp. 974-985, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
13 | Alessandro Strano, Carles Hernández 0001, Federico Silla, Davide Bertozzi |
Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Embed. Real Time Commun. Syst. ![In: Int. J. Embed. Real Time Commun. Syst. 2(4), pp. 1-20, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
13 | Young-Chan Jang |
A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(2), pp. 633-638, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
13 | Fotis Plessas, Alexis Alexandropoulos, Sotiris Koutsomitsos, Efthimios Davrazos, Michael K. Birbas |
Advanced calibration techniques for high-speed source-synchronous interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 5(5), pp. 366-374, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
13 | Ahmed Ragab, Yang Liu, Kangmin Hu, Patrick Chiang 0001, Samuel Palermo |
Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electr. Comput. Eng. ![In: J. Electr. Comput. Eng. 2011, pp. 982314:1-982314:15, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
13 | J. Mark Pullen, Nicholas K. Clark |
Moodle-integrated open source synchronous teaching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITiCSE ![In: Proceedings of the 16th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, ITiCSE 2011, Darmstadt, Germany, June 27-29, 2011, pp. 353, 2011, ACM, 978-1-4503-0697-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
13 | Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty |
4×2Gbps Source-Synchronous Transmitter in 45nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2011: 24th International Conference on VLSI Design, IIT Madras, Chennai, India, 2-7 January 2011, pp. 1-5, 2011, IEEE Computer Society, 978-0-7695-4348-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
13 | Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz |
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 45(12), pp. 2850-2860, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
13 | Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas |
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(6), pp. 897-910, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
13 | Young-Chan Jang |
An unmatched source synchronous I/O link for jitter reduction in a multi-phase clock system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 7(11), pp. 797-803, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
13 | Hyunjin Kim, Jacob A. Abraham |
A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, pp. 123-128, 2010, IEEE Computer Society, 978-0-7695-4248-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
13 | Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz |
A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010, pp. 160-161, 2010, IEEE, 978-1-4244-6033-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
13 | Alessandro Strano, Carles Hernández 0001, Federico Silla, Davide Bertozzi |
Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: 2010 International Symposium on System on Chip, SoC 2010, Tampere, September 29-30, 2010, pp. 43-48, 2010, IEEE, 978-1-4244-8279-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
13 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De |
SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2), pp. 384-394, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings, pp. 234-243, 2009, IEEE Computer Society, 978-1-4244-4142-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Anh Thien Tran, Dean Truong, Bevan M. Baas |
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings, pp. 214-223, 2009, IEEE Computer Society, 978-1-4244-4142-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas |
A Low-cost High-speed Source-synchronous Interconnection Technique for GALS Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 996-999, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei |
A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008, pp. 459-462, 2008, IEEE, 978-1-4244-2018-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De |
Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2007, pp. 95402:1-95402:12, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Derrin M. Berger, Jonathan Y. Chen, Frank D. Ferraiolo, Jeffrey A. Magee, Gary A. Van Huben |
High-speed source-synchronous interface for the IBM System z9 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 51(1/2), pp. 53-64, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Bernd Laquai, Michael Braun, S. Walther, Guido Schulze |
Flexible and scalable methodology for testing high-speed source synchronous interfaces on automated test equipment (ATE) with multiple fixed phase capture and compare. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 1(3), pp. 154-158, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu |
2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007, pp. 145-148, 2007, IEEE, 978-1-4244-1623-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan Casper, Aaron Martin, Joseph T. Kennedy, Naresh R. Shanbhag, Randy Mooney |
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(1), pp. 80-88, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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13 | Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan |
A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(9), pp. 1829-1838, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | J. Mark Pullen, Priscilla M. McAndrews |
A Web Portal for Open-Source Synchronous Distance Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CATE ![In: Proceedings of the 7th IASTED International Conference on Computers and Advanced Technology in Education, August 16-18, 2004, Kauai, Hawaii, USA, pp. 315-320, 2004, ACTA Press, 0-88986-422-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
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13 | Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan |
A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC 2004, Orlando, FL, USA, October 2004, pp. 431-434, 2004, IEEE, 0-7803-8495-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Jongsun Kim, Zhiwei Xu 0003, M. Frank Chang |
A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003, pp. 317-320, 2003, IEEE, 0-7803-7842-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | J. Mark Pullen |
Integrating Synchronous and Asynchronous Internet Distributed Education for Maximum Effectiveness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Education for the 21st Century ![In: Education for the 21st Century - Impact of ICT and Digital Resources, IFIP 19th World Computer Congress, TC-3, Education, August 21-24, 2006, Santiago, Chile, pp. 165-174, 2006, Springer, 0-387-34627-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 43-52, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing |
7 | Jongsun Kim, Bo-Cheng Lai, Mau-Chung Frank Chang, Ingrid Verbauwhede |
A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(12), pp. 1714-1719, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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7 | Suwen Yang, Mark R. Greenstreet, Jihong Ren |
A Jitter Attenuating Timing Chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA, pp. 25-38, 2007, IEEE Computer Society, 978-0-7695-2771-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
7 | Smruti R. Sarangi, Brian Greskamp, Josep Torrellas |
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2006 International Conference on Dependable Systems and Networks (DSN 2006), 25-28 June 2006, Philadelphia, Pennsylvania, USA, Proceedings, pp. 301-312, 2006, IEEE Computer Society, 0-7695-2607-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | T. M. Mak, Mike Tripp, Anne Meixner |
Testing Gbps Interfaces without a Gigahertz Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(4), pp. 278-286, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo |
SILENT: serialized low energy transmission coding for on-chip interconnection networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 448-451, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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7 | A. T. Sivaram, Pascal Pierra, Shida Sheibani, Nancy Wang-Lee, Jorge E. Solorzano, Lily Tran |
Active Tester Interface Unit Design For Data Collection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 587-596, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | Kenneth S. Stevens |
Energy and Performance Models for Clocked and Asynchronous Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 12-16 May 2003, Vancouver, BC, Canada, pp. 56-67, 2003, IEEE Computer Society, 0-7695-1898-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
7 | Jongsun Kim, Zhiwei Xu 0003, Mau-Chung Frank Chang |
Reconfigurable memory bus systems using multi-Gbps/pin CDMA I/O transceivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 33-36, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
7 | Claude R. Gauthier, Jayakumaran Sivagnaname, Richard B. Brown |
Dynamic Receiver Biasing For Inter-Chip Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA, pp. 101-111, 2001, IEEE Computer Society, 0-7695-1037-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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