Search results for "Source-Synchronous"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
64	Robert Law	Using student blogs for documentation in software development projects.	ITiCSE	2011	DBLP DOI BibTeX RDF
33	Ping Gui, Fouad E. Kiamilev, Xiaoqing Wang, Michael J. MacFadden, Xingle Wang, Nick Waite, Michael W. Haney, Charlie Kuznia	A Source-Synchronous Double-Data-Rate Parallel Optical Transceiver IC.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
33	Ganesh Balamurugan, Naresh R. Shanbhag	Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links.	ICCD	2003	DBLP DOI BibTeX RDF
31	David C. Keezer, Dany Minier, Patrice Ducharme	Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	control structure reliability, multi-gigahertz testing, picosecond timing accuracy, jitter-tolerance testing, jitter injection, fault tolerance, testing
26	Bernd Laquai, Martin Hua, Guido Schulze, Michael Braun	A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare.	ETS	2006	DBLP DOI BibTeX RDF
25	Darren Aaberge, Ken Mockler, Dieu Van Dinh, Raoul Belleau, Tim Donovan, Reid Hewlitt	Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities.	VTS	2005	DBLP DOI BibTeX RDF	RapidIO, Source-Synchronous, LVDS, Differential, ATE, Non-determinism
24	A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson	Tester Architecture For The Source Synchronous Bus.	ITC	2004	DBLP DOI BibTeX RDF
21	Andres Ayes, Eby G. Friedman	Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces.	Integr.	2023	DBLP DOI BibTeX RDF
20	Kartik Mohanram, Nur A. Touba	Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses.	VTS	2003	DBLP DOI BibTeX RDF
13	Youn-Sik Park, Sung-Wook Lee, Bai-Sun Kong, Kwang-Il Park, Jeong-Don Ihm, Joo-Sun Choi, Young-Hyun Jun	PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion.	ISCAS	2008	DBLP DOI BibTeX RDF
13	Jongsun Kim, Ingrid Verbauwhede, M.-C. Frank Chang	Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
13	Sebastian Fischer, Amir Najafi 0001, Alberto García Ortiz	Wave-Pipelined Source-Synchronous Circuit-Switched Data Transmission.	MOCAST	2023	DBLP DOI BibTeX RDF
13	Yang-Hang Fan, Ankur Kumar, Takayuki Iwai, Ashkan Roshan-Zamir, Shengchang Cai, Bo Sun, Samuel Palermo	A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
13	Oscar Yu, Cheng-Wei Chen, Chih-Shen Yeh, Jih-Sheng Lai 0001	Sequential Parallel Switching for Drain-Source Synchronous Rectification Efficiency Boost in Parallel Switch Rectifiers.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
13	Christopher Williams 0003, Diaaeldin Abdelrahman, Xiangdong Jia, Abdullah Ibn Abbas, Glenn E. R. Cowan, Odile Liboiron-Ladouceur	Reconfiguration in Source-Synchronous Receivers for Short-Reach Parallel Optical Links.	ISCAS	2020	DBLP DOI BibTeX RDF
13	Christopher Williams 0003, Diaaeldin Abdelrahman, Xiangdong Jia, Abdullah Ibn Abbas, Odile Liboiron-Ladouceur, Glenn E. R. Cowan	Reconfiguration in Source-Synchronous Receivers for Short-Reach Parallel Optical Links.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
13	Shunli Ma, Hao Yu 0001, Qun Jane Gu, Junyan Ren	A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
13	Yang-Hang Fan, Ankur Kumar, Takayuki Iwai, Ashkan Roshan-Zamir, Shengchang Cai, Bo Sun, Samuel Palermo	A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS.	CICC	2019	DBLP DOI BibTeX RDF
13	Cosimo Aprile, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl	An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
13	Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu	A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
13	Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim	A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
13	Pil-Ho Lee, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang	An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
13	Timothy O. Dickson, Yong Liu 0023, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman	A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
13	Kunzhi Yu, Cheng Li, Hao Li 0047, Alex Titriku, Ayman Shafik, Binhao Wang, Zhongkai Wang, Rui Bai 0001, Chin-Hui Chen, Marco Fiorentino, Patrick Yin Chiang, Samuel Palermo	A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
13	Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu	23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.	ISSCC	2016	DBLP DOI BibTeX RDF
13	Gregory K. Chen, Mark A. Anders 0001, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal 0001, Ram Krishnamurthy 0001, Vivek De, Shekhar Borkar	A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
13	Timothy O. Dickson, Yong Liu 0023, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman	A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
13	Shuai Yuan 0005, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Peng Wang, Wen Jia, Chun Zhang, Zhihua Wang 0001	A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS.	ESSCIRC	2015	DBLP DOI BibTeX RDF
13	Timothy O. Dickson, Yong Liu 0023, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman	A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.	CICC	2015	DBLP DOI BibTeX RDF
13	Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu	3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS.	ISSCC	2015	DBLP DOI BibTeX RDF
13	Kunzhi Yu, Hao Li 0047, Cheng Li, Alex Titriku, Ayman Shafik, Binhao Wang, Zhongkai Wang, Rui Bai 0001, Chin-Hui Chen, Marco Fiorentino, Patrick Yin Chiang, Samuel Palermo	22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization.	ISSCC	2015	DBLP DOI BibTeX RDF
13	Lizhou Wu, Nong Xiao, Fang Liu 0002, Yimo Du, Shuo Li 0007, Yang Ou	Dysource: a high performance and scalable NAND flash controller architecture based on source synchronous interface.	Conf. Computing Frontiers	2015	DBLP DOI BibTeX RDF
13	Kyongsu Lee, Jae-Yoon Sim	Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
13	Yoon Seok Yang, Reeshav Kumar, Gwan S. Choi, Paul V. Gratz	WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture.	ACM Trans. Design Autom. Electr. Syst.	2014	DBLP DOI BibTeX RDF
13	Shuai Yuan 0005, Ziqiang Wang, Xuqiang Zheng, Ke Huang 0003, Ni Xu, Woogeun Rhee, Liji Wu, Chun Zhang	A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
13	Woo-Rham Bae, Deog-Kyoon Jeong, Byoung-Joo Yoo	A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology.	DDECS	2014	DBLP DOI BibTeX RDF
13	Timothy O. Dickson, Yong Liu 0023, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman	A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.	CICC	2014	DBLP DOI BibTeX RDF
13	Gregory K. Chen, Mark A. Anders 0001, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal 0001, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De	16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS.	ISSCC	2014	DBLP DOI BibTeX RDF
13	Tao Li, Greg Sadowski	Design and implementation of novel source synchronous interconnection in modern GPU chips.	SoCC	2014	DBLP DOI BibTeX RDF
13	Ashok Jaiswal	Source-synchronous I/O Links using Adaptive Interface Training for High Bandwidth Applications (PDF / PS)		2014	RDF
13	Peter Gillingham, David Chinn, Eric Choi, Jin-Ki Kim, Don MacDonald, Hakjune Oh, Hong-Beom Pyeon, Roland Schuetz	800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology.	IEEE Access	2013	DBLP DOI BibTeX RDF
13	Jang-Woo Lee, Hong-Jung Kim, Chun-Seok Jeong, Jae-Jin Lee, Changsik Yoo	Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
13	Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra	Exploring topologies for source-synchronous ring-based network-on-chip.	DATE	2013	DBLP DOI BibTeX RDF
13	Ashok Jaiswal, Yuan Fang, Peter Gregorius, Klaus Hofmann	Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication Systems.	DSD	2013	DBLP DOI BibTeX RDF
13	Yuan Fang, Ashok Jaiswal, Klaus Hofmann	Low-power signal integrity trainings for multi-clock source-synchronous memory systems.	SoCC	2013	DBLP DOI BibTeX RDF
13	Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra	A source-synchronous Htree-based network-on-chip.	ACM Great Lakes Symposium on VLSI	2013	DBLP DOI BibTeX RDF
13	Kunzhi Yu, Xuqiang Zheng, Ke Huang 0003, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang 0001	A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
13	Timothy O. Dickson, Yong Liu 0023, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman	An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
13	Ke Huang 0003, Ziqiang Wang, Xuqiang Zheng, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang 0001	A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS.	MWSCAS	2012	DBLP DOI BibTeX RDF
13	Hyunjin Kim, Jacob A. Abraham	On-chip source synchronous interface timing test scheme with calibration.	DATE	2012	DBLP DOI BibTeX RDF
13	Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra	A fast, source-synchronous ring-based network-on-chip design.	DATE	2012	DBLP DOI BibTeX RDF
13	Dennis Walter, Sebastian Höppner, Holger Eisenreich, Georg Ellguth, Stephan Henker, Stefan Hänzsche, René Schüffny, Markus Winter 0002, Gerhard P. Fettweis	A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS.	ISSCC	2012	DBLP DOI BibTeX RDF
13	Yoon Seok Yang, Reeshav Kumar, Gwan Choi, Paul Gratz	WaveSync: A low-latency source synchronous bypass network-on-chip architecture.	ICCD	2012	DBLP DOI BibTeX RDF
13	Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra	Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design.	ICCD	2012	DBLP DOI BibTeX RDF
13	Ke Huang 0003, Chen Jia, Xuqiang Zheng, Ni Xu, Chun Zhang, Woogeun Rhee, Zhihua Wang 0001	A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology.	ISCAS	2012	DBLP DOI BibTeX RDF
13	Shijie Hu, Chen Jia, Ke Huang 0003, Chun Zhang, Xuqiang Zheng, Zhihua Wang 0001	A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS.	ISCAS	2012	DBLP DOI BibTeX RDF
13	Carl Edward Gray	An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.		2012	RDF
13	Masum Hossain, Anthony Chan Carusone	7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
13	Jared Zerbe, Barry Daly, Lei Luo 0006, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi T. Kollipara	A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
13	Alessandro Strano, Carles Hernández 0001, Federico Silla, Davide Bertozzi	Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design.	Int. J. Embed. Real Time Commun. Syst.	2011	DBLP DOI BibTeX RDF
13	Young-Chan Jang	A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2011	DBLP DOI BibTeX RDF
13	Fotis Plessas, Alexis Alexandropoulos, Sotiris Koutsomitsos, Efthimios Davrazos, Michael K. Birbas	Advanced calibration techniques for high-speed source-synchronous interfaces.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
13	Ahmed Ragab, Yang Liu, Kangmin Hu, Patrick Chiang 0001, Samuel Palermo	Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links.	J. Electr. Comput. Eng.	2011	DBLP DOI BibTeX RDF
13	J. Mark Pullen, Nicholas K. Clark	Moodle-integrated open source synchronous teaching.	ITiCSE	2011	DBLP DOI BibTeX RDF
13	Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty	4×2Gbps Source-Synchronous Transmitter in 45nm CMOS.	VLSI Design	2011	DBLP DOI BibTeX RDF
13	Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz	A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
13	Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas	A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
13	Young-Chan Jang	An unmatched source synchronous I/O link for jitter reduction in a multi-phase clock system.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
13	Hyunjin Kim, Jacob A. Abraham	A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
13	Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz	A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS.	ISSCC	2010	DBLP DOI BibTeX RDF
13	Alessandro Strano, Carles Hernández 0001, Federico Silla, Davide Bertozzi	Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip.	SoC	2010	DBLP DOI BibTeX RDF
13	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
13	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Estimating reliability and throughput of source-synchronous wave-pipelined interconnect.	NOCS	2009	DBLP DOI BibTeX RDF
13	Anh Thien Tran, Dean Truong, Bevan M. Baas	A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network.	NOCS	2009	DBLP DOI BibTeX RDF
13	Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas	A Low-cost High-speed Source-synchronous Interconnection Technique for GALS Chip Multiprocessors.	ISCAS	2009	DBLP DOI BibTeX RDF
13	Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei	A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction.	CICC	2008	DBLP DOI BibTeX RDF
13	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme.	VLSI Design	2007	DBLP DOI BibTeX RDF
13	Derrin M. Berger, Jonathan Y. Chen, Frank D. Ferraiolo, Jeffrey A. Magee, Gary A. Van Huben	High-speed source-synchronous interface for the IBM System z9 processor.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
13	Bernd Laquai, Michael Braun, S. Walther, Guido Schulze	Flexible and scalable methodology for testing high-speed source synchronous interfaces on automated test equipment (ATE) with multiple fixed phase capture and compare.	IET Comput. Digit. Tech.	2007	DBLP DOI BibTeX RDF
13	Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu	2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device.	CICC	2007	DBLP DOI BibTeX RDF
13	James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan Casper, Aaron Martin, Joseph T. Kennedy, Naresh R. Shanbhag, Randy Mooney	8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
13	Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan	A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
13	J. Mark Pullen, Priscilla M. McAndrews	A Web Portal for Open-Source Synchronous Distance Education.	CATE	2004	DBLP BibTeX RDF
13	Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan	A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface.	CICC	2004	DBLP DOI BibTeX RDF
13	Jongsun Kim, Zhiwei Xu 0003, M. Frank Chang	A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability.	CICC	2003	DBLP DOI BibTeX RDF
11	J. Mark Pullen	Integrating Synchronous and Asynchronous Internet Distributed Education for Maximum Effectiveness.	Education for the 21st Century	2006	DBLP DOI BibTeX RDF
7	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
7	Jongsun Kim, Bo-Cheng Lai, Mau-Chung Frank Chang, Ingrid Verbauwhede	A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
7	Suwen Yang, Mark R. Greenstreet, Jihong Ren	A Jitter Attenuating Timing Chain.	ASYNC	2007	DBLP DOI BibTeX RDF
7	Smruti R. Sarangi, Brian Greskamp, Josep Torrellas	CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging.	DSN	2006	DBLP DOI BibTeX RDF
7	T. M. Mak, Mike Tripp, Anne Meixner	Testing Gbps Interfaces without a Gigahertz Tester.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
7	Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo	SILENT: serialized low energy transmission coding for on-chip interconnection networks.	ICCAD	2004	DBLP DOI BibTeX RDF
7	A. T. Sivaram, Pascal Pierra, Shida Sheibani, Nancy Wang-Lee, Jorge E. Solorzano, Lily Tran	Active Tester Interface Unit Design For Data Collection.	ITC	2004	DBLP DOI BibTeX RDF
7	Kenneth S. Stevens	Energy and Performance Models for Clocked and Asynchronous Communication.	ASYNC	2003	DBLP DOI BibTeX RDF
7	Jongsun Kim, Zhiwei Xu 0003, Mau-Chung Frank Chang	Reconfigurable memory bus systems using multi-Gbps/pin CDMA I/O transceivers.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
7	Claude R. Gauthier, Jayakumaran Sivagnaname, Richard B. Brown	Dynamic Receiver Biasing For Inter-Chip Communication.	ARVLSI	2001	DBLP DOI BibTeX RDF