Search results for "Stratix"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
97	David M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan	Architectural enhancements in Stratix-IIITM and Stratix-IVTM.	FPGA	2009	DBLP DOI BibTeX RDF	power management, memory, fpga architecture, static power
70	David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose	The Stratix II logic and routing architecture.	FPGA	2005	DBLP DOI BibTeX RDF	logic module, FPGA, routing
70	Viktor Fischer, Milos Drutarovský, Martin Simka, Nathalie Bochard	High Performance True Random Number Generator in Altera Stratix FPLDs.	FPL	2004	DBLP DOI BibTeX RDF
55	Pawel Swierczynski, Amir Moradi 0001, David F. Oswald, Christof Paar	Physical Security Evaluation of the Bitstream Encryption Mechanism of Altera Stratix II and Stratix III FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2015	DBLP DOI BibTeX RDF
36	Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose	FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy.	FCCM	2009	DBLP DOI BibTeX RDF	photodynamic therapy, PDT, Stratix, DE3, FPGA, applications, pipeline, Power, Monte Carlo, SystemC, acceleration, cancer
28	Yongjae Jeong, Kwon-Yeol Ryu, Tae-Il Jeong, Kwang-Seok Moon, Jong-Nam Kim	FPGA Implementation of Video Watermark Embedding System.	ICIC (3)	2007	DBLP DOI BibTeX RDF	Real Time Video Watermarking, FPGA, Hardware Implementation, Spread Spectrum
28	Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier	An adaptive Reed-Solomon errors-and-erasures decoder.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, power reduction, Reed-Solomon
28	Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown	Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.	SLIP	2006	DBLP DOI BibTeX RDF
28	Martin Simka, Milos Drutarovský, Viktor Fischer, J. Fayolle	Model of a true random number generator aimed at cryptographic applications.	ISCAS	2006	DBLP DOI BibTeX RDF
28	Ahmed Ben Atitallah, Patrice Kadionik, Fahmi Ghozzi, Patrice Nouel, Nouri Masmoudi, Hervé Levi	HW/SW Codesign of the H.263 Video Coder.	CCECE	2006	DBLP DOI BibTeX RDF
28	Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster 0001	An FPGA-based VLIW processor with custom hardware execution.	FPGA	2005	DBLP DOI BibTeX RDF	NIOS, parallelism, compiler, synthesis, kernels, VLIW
28	Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini	Improving FPGA Performance and Area Using an Adaptive Logic Module.	FPL	2004	DBLP DOI BibTeX RDF
28	Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson	Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
28	David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose	The StratixTM routing and logic architecture.	FPGA	2003	DBLP DOI BibTeX RDF
27	John A. Kalomiros, John V. Vourvoulakis, Stavros Vologiannidis	A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology.	ACM Trans. Reconfigurable Technol. Syst.	2024	DBLP DOI BibTeX RDF
27	Martin Langhammer, Eriko Nurvitadhi, Sergey Gribok, Bogdan Pasca 0001	Stratix 10 NX Architecture.	ACM Trans. Reconfigurable Technol. Syst.	2022	DBLP DOI BibTeX RDF
27	Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami	MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA.	FPGA	2022	DBLP DOI BibTeX RDF
27	Ahmad Mouri Zadeh Khaki, Ebrahim Farshidi, Karim Ansari-Asl, Sawal Hamid Md. Ali, Masuri Othman	Design and Analysis of a Multirate 5-bit High-Order 52 fsrms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA.	IEEE Access	2021	DBLP DOI BibTeX RDF
27	Jacob Lambert 0002, Seyong Lee, Jeffrey S. Vetter, Allen D. Malony	Optimization with the OpenACC-to-FPGA framework on the Arria 10 and Stratix 10 FPGAs.	Parallel Comput.	2021	DBLP DOI BibTeX RDF
27	Paolo Gorlani, Christian Plessl	High Level Synthesis Implementation of a Three-dimensional Systolic Array Architecture for Matrix Multiplications on Intel Stratix 10 FPGAs.	CoRR	2021	DBLP BibTeX RDF
27	Martin Langhammer, Eriko Nurvitadhi, Bogdan Pasca 0001, Sergey Gribok	Stratix 10 NX Architecture and Applications.	FPGA	2021	DBLP DOI BibTeX RDF
27	Chester Liu, Jacob Botimer, Zhengya Zhang	A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer.	CICC	2021	DBLP DOI BibTeX RDF
27	Sung-Gun Cho, Wei Tang 0010, Chester Liu, Zhengya Zhang	PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
27	Takaaki Miyajima, Kentaro Sano	A memory bandwidth improvement with memory space partitioning for single-precision floating-point FFT on Stratix 10 FPGA.	CLUSTER	2021	DBLP DOI BibTeX RDF
27	Ke He, Bo Liu, Yu Zhang, Andrew Ling, Dian Gu	FeCaffe: FPGA-enabled Caffe with OpenCL for Deep Learning Training and Inference on Intel Stratix 10.	FPGA	2020	DBLP DOI BibTeX RDF
27	Atsushi Koshiba, Kouki Watanabe, Takaaki Miyajima, Kentaro Sano	Performance Evaluation and Power Analysis of Teraflop-scale Fluid Simulation with Stratix 10 FPGA.	FPGA	2020	DBLP DOI BibTeX RDF
27	Ke He, Bo Liu, Yu Zhang, Andrew Ling, Dian Gu	FeCaffe: FPGA-enabled Caffe with OpenCL for Deep Learning Training and Inference on Intel Stratix 10.	CoRR	2019	DBLP BibTeX RDF
27	Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy 0001, Debbie Marr, Sergey Gribok, Bogdan Pasca 0001, Martin Langhammer, Aravind Dasu	Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI.	FPGA	2019	DBLP DOI BibTeX RDF
27	Paolo Gorlani, Tobias Kenter, Christian Plessl	OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.	FPT	2019	DBLP DOI BibTeX RDF
27	Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
27	Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.	FPL	2018	DBLP DOI BibTeX RDF
27	Pan Li 0001, Rui Zhang, Jing Zhang, Jie Li, Guanxing Zhao, Hua Li	Design of Radar Electromagnetic Environment Simulation System Based on Altera Stratix® III Series FPGA.	ICSAI	2018	DBLP DOI BibTeX RDF
27	Madison N. Emas, Austin Baylis, Greg Stitt	High-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlex.	FCCM	2018	DBLP DOI BibTeX RDF
27	Tian Tan 0007, Eriko Nurvitadhi, David Shih, Derek Chiou	Evaluating The Highly-Pipelined Intel Stratix 10 FPGA Architecture Using Open-Source Benchmarks.	FPT	2018	DBLP DOI BibTeX RDF
27	David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken	The Stratix™ 10 Highly Pipelined FPGA Architecture.	FPGA	2016	DBLP DOI BibTeX RDF
27	Carl Ebeling, Dana How, David M. Lewis, Herman Schmit	Stratix™ 10 High Performance Routable Clock Networks.	FPGA	2016	DBLP DOI BibTeX RDF
27	Zhenzhong Xiao, Dirk Koch, Mikel Luján	A partial reconfiguration controller for Altera Stratix V FPGAs.	FPL	2016	DBLP DOI BibTeX RDF
27	Dana L. How, Sean Atsatt	Sectors: Divide & Conquer and Softwarization in the Design and Validation of the Stratix® 10 FPGA.	FCCM	2016	DBLP DOI BibTeX RDF
27	Sumedh Guha, Wen Wang 0007, Shafeeq Ibraheem, Mahesh Balakrishnan 0001, Jakub Szefer	Design and implementation of open-source SATA III core for Stratix V FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
27	Iman Firmansyah, Yoshiki Yamaguchi, Taisuke Boku	Performance evaluation of Stratix V DE5-Net FPGA board for high performance computing.	IC3INA	2016	DBLP DOI BibTeX RDF
27	Mike Hutton	Stratix® 10: 14nm FPGA delivering 1GHz.	Hot Chips Symposium	2015	DBLP DOI BibTeX RDF
27	Kenneth Hill, Stefan Craciun, Alan D. George, Herman Lam	Comparative analysis of OpenCL vs. HDL with image-processing kernels on Stratix-V FPGA.	ASAP	2015	DBLP DOI BibTeX RDF
27	Zakaria Moutakki, Tarik Ayaou, Karim Afdel, Abdellah Amghar	Prototype of an embedded system using Stratix III FPGA for vehicle detection and traffic management.	ICMCS	2014	DBLP DOI BibTeX RDF
27	Amir Moradi 0001, David F. Oswald, Christof Paar, Pawel Swierczynski	Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering.	FPGA	2013	DBLP DOI BibTeX RDF
27	David M. Lewis, David Cashman, Mark Chan, Jeffrey Chromczak, Gary Lai, Andy Lee, Tim Vanderhoek, Haiming Yu	Architectural enhancements in Stratix V™.	FPGA	2013	DBLP DOI BibTeX RDF
27	Dan Mansur, Sergey Y. Shumarayev	Introducing 28-nm stratix VFPGAs: Built for bandwidth.	Hot Chips Symposium	2010	DBLP DOI BibTeX RDF
27	Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu	DPL on Stratix II FPGA: What to Expect?.	ReConFig	2009	DBLP DOI BibTeX RDF	Dual-rail with Precharge Logic (DPL), Wave Dynamic Differential Logic (WDDL), Field Programmable Gates Array (FPGA), Differential Power Analysis (DPA), Commercial Off-The-Shelf (COTS), Side-Channel Analysis (SCA)
27	Jay Kraut	Hardware Edge Detection using an Altera Stratix NIOS2 Development Kit.	CCECE	2006	DBLP DOI BibTeX RDF
14	Charles Eric LaForest, J. Gregory Steffan	Efficient multi-ported memories for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, parallel, memory, multi-port
14	Miad Faezipour, Mehrdad Nourani, Rina Panigrahy	A hardware platform for efficient worm outbreak detection.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	shared counters, worm outbreak, hashing, false positive, Network Intrusion Detection System, false negative, polymorphic worm
14	Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada	All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.	DDECS	2009	DBLP DOI BibTeX RDF
14	Xin Xiao, Erdal Oruklu, Jafar Saniie	Fast memory addressing scheme for radix-4 FFT implementation.	EIT	2009	DBLP DOI BibTeX RDF
14	Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour	Towards automated ECOs in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	pst, optimization, fpga, boolean satisfiability, resynthesis
14	Robson Dornelles, Felipe Sampaio, Daniel Palomino 0001, Luciano Volcan Agostini	Transforms and quantization design targeting the H.264/AVC intra prediction constraints.	SBCCI	2009	DBLP DOI BibTeX RDF	IQ modules, Q, T, IT, video coding, high performance, H.264/AVC, VLSI design, low latency, intra-prediction
14	Pouya Dormiani, Milos D. Ercegovac, Jean-Michel Muller	Design and Implementation of a Radix-4 Complex Division Unit with Prescaling.	ASAP	2009	DBLP DOI BibTeX RDF
14	Kimmo U. Järvinen, Jorma Skyttä	On Parallelization of High-Speed Processors for Elliptic Curve Cryptography.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
14	Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung	Outer Loop Pipelining for Application Specific Datapaths in FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
14	Eero Aho, Jarno Vanne, Timo D. Hämäläinen	Configurable Data Memory for Multimedia Processing.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	stride access, configurable, parallel memory, skewing scheme, SIMD processing
14	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming.	DATE	2008	DBLP DOI BibTeX RDF
14	Tomasz S. Czajkowski, Stephen Dean Brown	Fast toggle rate computation for FPGA circuits.	FPL	2008	DBLP DOI BibTeX RDF
14	Martin Langhammer	Floating point datapath synthesis for FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
14	Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama	FPGA implementation of a vehicle detection algorithm using three-dimensional information.	IPDPS	2008	DBLP DOI BibTeX RDF
14	Yasuaki Ito, Koji Nakano	Component labeling for k-concave binary images using an FPGA.	IPDPS	2008	DBLP DOI BibTeX RDF
14	Kimmo U. Järvinen, Jorma O. Skyttä	High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves.	FCCM	2008	DBLP DOI BibTeX RDF
14	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	VESPA: portable, scalable, and flexible FPGA-based vector processors.	CASES	2008	DBLP DOI BibTeX RDF	SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
14	Jacqueline Gomes Mertes, Norian Marranghello, Aledir Silveira Pereira	Implementation of Filters for Image Pre-processing for Leaf Analyses in Plantations.	ICCS (2)	2008	DBLP DOI BibTeX RDF	hardware description language application, reconfigurable architectures, digital image processing, Precision agriculture
14	Jie Shao, Ning Ye, Xiao-Yan Zhang	An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs.	CSSE (4)	2008	DBLP DOI BibTeX RDF
14	Zhi-Jian Sun, Xue-Mei Liu	The Realization of SAR Real-Time Signal Processor by FPGA.	CSSE (4)	2008	DBLP DOI BibTeX RDF
14	Seth H. Groder, Kenneth W. Hsu	Design methodolgy for HD Photo compression algorithm targeting a FPGA.	SoCC	2008	DBLP DOI BibTeX RDF
14	Maxim Leonov, Vyacheslav V. Kitaev	Feasibility Study of Implementing Multi-Channel Correlation for DSP Applications on Reconfigurable CPU+FPGA Platform.	PDCAT	2008	DBLP DOI BibTeX RDF
14	Yasuaki Ito, Koji Nakano	Optimized Component Labeling Algorithm for Using in Medium Sized FPGAs.	PDCAT	2008	DBLP DOI BibTeX RDF
14	Alan Kennedy, Xiaojun Wang 0001, Zhen Liu 0018, Bin Liu 0001	Low power architecture for high speed packet classification.	ANCS	2008	DBLP DOI BibTeX RDF	energy efficient, hardware accelerator, packet classification, frequency scaling
14	Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee	An Overview of a Compiler for Mapping Software Binaries to Hardware.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
14	T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot, Javier Valls	Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	Fast Fourier Transform, digital circuits, digital communications
14	Nathan Woods	Integrating FPGAs in high-performance computing: the architecture and implementation perspective.	FPGA	2007	DBLP DOI BibTeX RDF	compute acceleration, high-performance computinghigh-performance computing, reconfigurable computing, co-processor
14	Brad Matthews, Itamar Elhanany, Vahid Tabatabaee	Accelerated Packet Placement Architecture for Parallel Shared Memory Routers.	Networking	2007	DBLP DOI BibTeX RDF
14	Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang	High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF
14	Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung	A Hybrid Memory Sub-system for Video Coding Applications.	FCCM	2007	DBLP DOI BibTeX RDF
14	Rui Rodrigues 0004, João M. P. Cardoso, Pedro C. Diniz	A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops.	FCCM	2007	DBLP DOI BibTeX RDF
14	Ronen Goldberg, Guy Even, Peter-Michael Seidel	An FPGA implementation of pipelined multiplicative division with IEEE Rounding.	FCCM	2007	DBLP DOI BibTeX RDF
14	Kentaro Sano, Takanori Iizuka, Satoru Yamamoto	Systolic Architecture for Computational Fluid Dynamics on FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
14	Daniel Baumgartner, Peter Rössler, Wilfried Kubinger	Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms.	CVPR	2007	DBLP DOI BibTeX RDF
14	Yehua Gu, Xiaoyang Zeng, Jun Han 0003, Jia Zhao	A Low-cost and High-performance SoC Design for OMA DRM2 Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Kimmo U. Järvinen, Juha Forsten, Jorma Skyttä	FPGA Design of Self-certified Signature Verification on Koblitz Curves.	CHES	2007	DBLP DOI BibTeX RDF
14	Thaísa Leal da Silva, Cláudio Machado Diniz, João Alberto Vortmann, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi	A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder.	PSIVT	2007	DBLP DOI BibTeX RDF	8x8 2-D DCT, H.264/AVC standard, Video compression, Architectural Design
14	Tomasz S. Czajkowski, Stephen Dean Brown	Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits.	DAC	2007	DBLP DOI BibTeX RDF
14	Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa	High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	queue processor, design, prototyping, high performance, high-level modeling
14	Amit Kumar Gupta, Saeid Nooshabadi, David Taubman, Michael Dyer	Realizing Low-Cost High-Throughput General-Purpose Block Encoder for JPEG2000.	IEEE Trans. Circuits Syst. Video Technol.	2006	DBLP DOI BibTeX RDF
14	Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster 0001	Reducing power while increasing performance with supercisc.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Low-power, synthesis, VLIW, predication, multicore architectures
14	Gang Chen 0020, Jason Cong	Simultaneous placement with clustering and duplication.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	clustering, FPGA, Placement, legalization, duplication, redundancy removal
14	Eero Aho, Jarno Vanne, Timo D. Hämäläinen	Parallel Memory Implementation for Arbitrary Stride Accesses.	ICSAMOS	2006	DBLP DOI BibTeX RDF
14	J. Andy Harriman, Brent R. Petersen, Mary E. Kaye	A Reconfigurable Four-Channel Transceiver Testbed with Signalling-Wavelength-Spaced Antennas under Centralized FPGA Control.	CNSR	2006	DBLP DOI BibTeX RDF
14	Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel	A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes.	ISVLSI	2006	DBLP DOI BibTeX RDF
14	Reid B. Porter, Jan R. Frigo, Maya B. Gokhale, Christophe Wolinski, François Charot, Charles Wagner	A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing.	DSD	2006	DBLP DOI BibTeX RDF
14	Baofeng Li, Qiang Shao	Deeply Parallel Architecture for Lifting-Based 2D DWT in JPEG2000.	CIT	2006	DBLP DOI BibTeX RDF
14	Antonin Hermanek, Michal Kunes, Michal Kvasnicka	Using Reconfigurable HW for High Dimensional CAF Computation.	FPL	2006	DBLP DOI BibTeX RDF
14	Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton	Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays.	FPL	2006	DBLP DOI BibTeX RDF
14	Ciaran Toal, Sakir Sezer	Investigation into programmability for layer 2 protocol frame delineation architectures.	IPDPS	2006	DBLP DOI BibTeX RDF
14	Yousef El-Kurdi, Warren J. Gross, Dennis Giannacopoulos	Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
14	Reid B. Porter, Jan R. Frigo, Maya B. Gokhale, Christophe Wolinski, François Charot, Charles Wagner	A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing.	FCCM	2006	DBLP DOI BibTeX RDF