Search results for "VLSI-CAD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Anthony F. Hutchings, Richard J. Bonneau, William M. Fisher	Integrated VLSI CAD systems at Digital Equipment Corporation.	DAC	1985	DBLP DOI BibTeX RDF
65	Anoop Singhal, Chi-Yuan Lo	Object oriented data modeling for VLSI/CAD.	VLSI Design	1995	DBLP DOI BibTeX RDF	design data manager, integrated CAD system, modular program architecture, VLSI, object-oriented methods, integrated circuit design, circuit CAD, object oriented data modeling, VLSI CAD
61	Juin-Yeu Lu, Shiu-Kai Chin	Linking HOL to a VLSI CAD System.	HUG	1993	DBLP DOI BibTeX RDF
57	Balkrishna Ramkumar, Prithviraj Banerjee	ProperCAD: A portable object-oriented parallel environment for VLSI CAD.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
51	Scott Hauck, Stephen Knol	Data Security for Web-based CAD.	DAC	1998	DBLP DOI BibTeX RDF	Web-based CAD, Internet, encryption, data security
46	Tan Yan, Shuting Li, Yasuhiro Takashima, Hiroshi Murata	A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks.	ASP-DAC	2007	DBLP DOI BibTeX RDF	shortest obstacle-avoiding routing length, wire length estimation algorithms, shortest routing length, routing obstacles, block placement, computational geometry, VLSI CAD
46	Anoop Singhal, Robert M. Arlein, Chi-Yuan Lo	DDB: An Object Oriented Design Data Manager for VLSI CAD.	SIGMOD Conference	1993	DBLP DOI BibTeX RDF	C++
41	Michael L. Bushnell, Stephen W. Director	VLSI CAD tool integration using the Ulysses environment.	DAC	1986	DBLP DOI BibTeX RDF	Ulysses
40	Darko Kirovski, David T. Liu, Jennifer L. Wong, Miodrag Potkonjak	Forensic engineering techniques for VLSI CAD tools.	DAC	2000	DBLP DOI BibTeX RDF
40	Don S. Batory, Won Kim 0001	Modeling Concepts for VLSI CAD Objects.	ACM Trans. Database Syst.	1985	DBLP DOI BibTeX RDF
39	Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee	Load Balancing and Workload Minimization Of Overlapping Parallel Tasks.	ICPP	1997	DBLP DOI BibTeX RDF	parallel compiled VHDL simulation, load balancing, task assignment, VLSI-CAD, fine grained parallelism
38	Martin Bolton	Texts reflect growing interest in CAD for VLSI: Fichtner, W and Morf, M (eds)VLSI CAD tools and applications Kluwer, Boston, MA, USA (1987) $69.50 pp 552.	Microprocess. Microsystems	1988	DBLP DOI BibTeX RDF
37	N. J. Elias, R. J. Byrne, A. D. Close, Robert M. McDermott	The ITT VLSI design system: CAD integration in a multi-national environment.	DAC	1985	DBLP DOI BibTeX RDF
34	Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal	A novel ultra-fast heuristic for VLSI CAD steiner trees.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	routing, steiner trees, interconnect estimation
33	James Daniell, Stephen W. Director	An object oriented approach to CAD tool control [VLSI].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
32	Melvin A. Breuer, Majid Sarrafzadeh, Fabio Somenzi	Fundamental CAD algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
29	John A. Nestor	Web-Based Visualization Tools for Teaching VLSI CAD Algorithms.	MSE	2001	DBLP DOI BibTeX RDF
29	Katsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka	Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	automatic fault tracing system, EB tester, CAD layout, VLSI
29	Louis-Philippe Demers, P. Jacques, S. Fauvel, Eduard Cerny	CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools.	DAC	1987	DBLP DOI BibTeX RDF
29	Rolf Drechsler, Detlef Sieling	Binary decision diagrams in theory and practice.	Int. J. Softw. Tools Technol. Transf.	2001	DBLP DOI BibTeX RDF	data structure, Boolean function, Binary decision diagram, VLSI CAD, Branching program
29	Anand Chavan, Shiu-Kai Chin, Shahid Ikram, Jang Dae Kim, Juin-Yeu Zu	Extending VLSI design with higher-order logic.	ICCD	1995	DBLP DOI BibTeX RDF	Cambridge Higher-Order Logic theorem-prover, microprogram sequencer, Am2910, VLSI, formal verification, formal verification, logic testing, theorem proving, logic design, logic CAD, VLSI design, higher-order logic, theorem-prover, design environment, instruction-set architecture, VLSI CAD
29	Scott Hauck, Gaetano Borriello	An evaluation of bipartitioning techniques.	ARVLSI	1995	DBLP DOI BibTeX RDF	bipartitioning techniques, VLSI, logic CAD, integrated circuit design, circuit CAD, logic partitioning, logic partitioning, VLSI CAD
29	Akio Okazaki, Takashi Kondo, Kazuhiro Mori, Shou Tsunekawa, Eiji Kawamoto	An Automatic Circuit Diagram Reader with Loop-Structure-Based Symbol Recognition.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	automatic circuit diagram reader, loop-structure-based symbol recognition, logic circuit diagram reader, symbol segmentation, symbol identification, decision-tree control, character string recognition, connecting line analysis, computer vision, feature extraction, computerised pattern recognition, computerised pattern recognition, logic CAD, template matching, circuit CAD, VLSI-CAD
28	Yinghai Lu, Hai Zhou 0001, Li Shang, Xuan Zeng 0001	Multicore parallel min-cost flow algorithm for CAD applications.	DAC	2009	DBLP DOI BibTeX RDF	min-cost flow, parallel programming, multicore
28	Renaud Cornu-Emieux	Réseau de cellules intégré : étude d'architectures pour des applications de CAO de VLSI. (Integrated cell network: architecture study for vlsi cad applications).		1988	RDF
24	Shantanu Dutt, Wenyong Deng	Cluster-aware iterative improvement techniques for partitioning large VLSI circuits.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	VLSI circuit partitioning, mincut, physical design/layout, Clusters, iterative-improvement
24	Mario Alberto López, Ravi Janardan, Sartaj K. Sahni	Efficient net extraction for restricted orientation designs [VLSI layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
22	Olivier Coudert, Igor L. Markov, Christoph Meinel, Ellen Sentovich	Web-based frameworks to enable CAD RD (abstract).	DAC	2000	DBLP DOI BibTeX RDF
20	Gang Qu 0001	Publicly detectable watermarking for intellectual property authentication in VLSI design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
20	Shantanu Dutt, Wenyong Deng	VLSI circuit partitioning by cluster-removal using iterative improvement techniques.	ICCAD	1996	DBLP DOI BibTeX RDF	ACM/SIGDA benchmark circuits, Fiduccia-Mattheyses algorithm, VLSI circuit partitioning, cluster-removal, iterative improvement techniques, look-ahead algorithm, partition quality, spectral partitioner MELO, VLSI, CAD
20	Gwo-Dong Chen, Tai-Ming Parng	A Database Management System for a VLSI Design System.	DAC	1988	DBLP BibTeX RDF
19	Zhuomin Chai, Yuxiang Zhao, Wei Liu, Yibo Lin, Runsheng Wang, Ru Huang	CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
19	Sukanta Dey, Sukumar Nandi, Gaurav Trivedi	Machine Learning for VLSI CAD: A Case Study in On-Chip Power Grid Design.	ISVLSI	2021	DBLP DOI BibTeX RDF
19	Tsung-Wei Huang	A General-purpose Parallel and Heterogeneous Task Programming System for VLSI CAD.	ICCAD	2020	DBLP DOI BibTeX RDF
19	Tsung-Wei Huang	Programming Systems for Parallelizing VLSI CAD and Beyond.	VLSI-DAT	2020	DBLP DOI BibTeX RDF
19	Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu	Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.	ISCAS	2016	DBLP DOI BibTeX RDF
19	Qian Zhao 0001, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi	FPGA Design Framework Combined with Commercial VLSI CAD.	IEICE Trans. Inf. Syst.	2013	DBLP DOI BibTeX RDF
19	David Z. Pan, Jhih-Rong Gao, Bei Yu 0001	VLSI CAD for emerging nanolithography.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
19	Massimo Alioto	Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
19	Chul-Hong Park, David Z. Pan, Kevin Lucas	Exploration of VLSI CAD researches for early design rule evaluation.	ASP-DAC	2011	DBLP DOI BibTeX RDF
19	Lucanus J. Simonson	Industrial strength polygon clipping: A novel algorithm with applications in VLSI CAD.	Comput. Aided Des.	2010	DBLP DOI BibTeX RDF
19	Alex K. Jones, Steven P. Levitan, Rob A. Rutenbar, Yuan Xie 0001	Collaborative VLSI-CAD Instruction in the Digital Sandbox.	MSE	2007	DBLP DOI BibTeX RDF
19	Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada	VLSI CAD Education and Exercise Course with Public Domain Tools.	MSE	2007	DBLP DOI BibTeX RDF
19	Lin Yuan, Gang Qu 0001, Ankur Srivastava 0001	VLSI CAD tool protection by birthmarking design solutions.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	birthmarking, CAD, protection, intellectual property
19	Mitchell Aaron Thornton, Rolf Drechsler, D. Michael Miller	Spectral techniques in VLSI CAD.		2001	RDF
19	Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov	Hypergraph partitioning with fixed vertices [VLSI CAD].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
19	Sverre Wichlund, Einar J. Aas	On efficient CPU-usage in a VLSI CAD-environment with application to circuit partitioning.	ICECS	2000	DBLP DOI BibTeX RDF
19	Rolf Drechsler	Evolutionary Algorithms for VLSI CAD [book Review].	IEEE Trans. Evol. Comput.	1999	DBLP DOI BibTeX RDF
19	Zhen Luo, Margaret Martonosi, Pranav Ashar	An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking.	FCCM	1999	DBLP DOI BibTeX RDF	Scanline Algorithm, Configurable Hardware, FPGA, DRC
19	Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov	Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting.	DAC	1999	DBLP DOI BibTeX RDF
19	C.-J. Richard Shi, Janusz A. Brzozowski	Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	cluster-cover, logic minimizaiton, self-checking logic design, topological routing, NP-completeness, state assignment
19	Motohide Otsubo, Satoru Fujita, Toru Yamanouchi	Intelligent Command Control for VLSI CAD Systems.	AAAI/IAAI	1997	DBLP BibTeX RDF
19	John G. Holm, John A. Chandy, Steven Parkes, Sumit Roy 0003, Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee	Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors.	International Conference on Supercomputing	1997	DBLP DOI BibTeX RDF
19	John A. Chandy, Steven Parkes, Prithviraj Banerjee	Distributed Object Oriented Data Structures and Algorithms for VLSI CAD.	IRREGULAR	1996	DBLP DOI BibTeX RDF
19	C.-J. Richard Shi, Janusz A. Brzozowski	A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems.	ASP-DAC	1995	DBLP DOI BibTeX RDF
19	Renate Beckmann, Ulrich Bieker, Ingolf Markhof	Application of Constraint Logic Programming for VLSI CAD Tools.	CCL	1994	DBLP DOI BibTeX RDF
19	A. Bandyopadhyay, P. R. Verma, A. B. Bhattacharyya, M. J. Zarabi	LATCHSIM - A Lath-Up Simulator in VLSI CAD Environment for CMOS and BiCMOS Circuits.	VLSI Design	1994	DBLP DOI BibTeX RDF
19	Krishna P. Belkhale, Randall J. Brouwer, Prithviraj Banerjee	Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
19	Israel A. Wagner, Israel Koren	An Interactive Yield Estimator as a VLSI CAD Tool.	DFT	1993	DBLP BibTeX RDF
19	Balkrishna Ramkumar, Prithviraj Banerjee	ProperCAd: A Portable Object-Oriented Parallel Environment for VLSI CAD.	ICCD	1992	DBLP DOI BibTeX RDF
19	A. Tietz, J. Koehl	A VLSI - CAD system for efficient design of CMOS/390 processors.	Microprocessing and Microprogramming	1991	DBLP DOI BibTeX RDF
19	Doohun Eum, Toshimi Minoura	Data-Structure Builder for VLSI/CAD Software.	DEXA	1991	DBLP BibTeX RDF
19	Yongtao You	Toward a Fully Integrated VLSI CAD System: from Custom to Fully Automatic.		1991	RDF
19	Rajiv Gupta 0002, Melvin A. Breuer	An Extensible User Interface for an Object-Oriented VLSI CAD Framework.	ICSI	1990	DBLP BibTeX RDF
19	Marwan A. Jabri	BREL - a Prolog Knowledge-based System Shell for VLSI CAD.	DAC	1990	DBLP DOI BibTeX RDF	Prolog
19	David Hung-Chang Du, Subbarao Ghanta	A Framework for efficient IC/VLSI CAD databases.	Inf. Sci.	1989	DBLP DOI BibTeX RDF
19	Rajiv Gupta 0002, Wesley H. Cheng, Rajesh Gupta 0003, Ido Hardonag, Melvin A. Breuer	An Object-Oriented VLSI CAD Framework: A Case Study in Rapid Prototyping.	Computer	1989	DBLP DOI BibTeX RDF
19	Alok Kumar, Vijeta Kashyap, Sunil D. Sherlekar, G. Venkatesh 0001, S. Biswas, Anshul Kumar, P. C. P. Bhatt, Sashi Kumar	Ideas: a tool for VLSI CAD.	IEEE Des. Test	1989	DBLP DOI BibTeX RDF
19	Arnaldo Hilário Viegas de Lima, Raul César B. Martins, Ronaldo Stern, Luiza Maria F. Carneiro	GARDEN - An Integrated and Evolving Environment for ULSI/VLSI CAD Applications.	IBM Syst. J.	1989	DBLP DOI BibTeX RDF
19	Anoop Singhal, Nishit P. Parikh, Debaprosad Dutt, Chi-Yuan Lo	A data model and architecture for VLSI/CAD databases.	ICCAD	1989	DBLP DOI BibTeX RDF
19	Meng-Lin Yu	A Study of the Applicability of Hopfield Decision Neural Nets to VLSI CAD.	DAC	1989	DBLP DOI BibTeX RDF
19	Tore Sæter	Software techniques for integrating text and graphics in VLSI CAD tools.	Microprocess. Microprogramming	1988	DBLP DOI BibTeX RDF
19	Pei-Yung Hsiao, Chen Yung Syau, Wu-Shiung Feng, T. M. Parng, Cheng-Chung Hsu	A rule-based compactor for VLSI/CAD mask layout.	COMPSAC	1988	DBLP DOI BibTeX RDF
19	Frederica Darema, Gregory F. Pfister	Multipurpose Parallelism for VLSI Cad on the RP3.	IEEE Des. Test	1987	DBLP DOI BibTeX RDF
19	Rolf-Dieter Fiebrich	The Connection Machine - A General Purpose Accelerator for VLSI CAD.	COMPCON	1987	DBLP BibTeX RDF
19	David Hung-Chang Du, Subbarao Ghanta	A Framework for Efficient IC/VLSI CAD Databases.	ICDE	1987	DBLP DOI BibTeX RDF
19	Rolf-Dieter Fiebrich	A Supercomputer Workstation for VLSI CAD.	IEEE Des. Test	1986	DBLP DOI BibTeX RDF
19	Richard E. Zippel, Paul Penfield Jr., Lance A. Glasser, Charles E. Leiserson, John L. Wyatt Jr., Jonathan Allen	Recent Results in VLSI CAD at MIT.	FJCC	1986	DBLP BibTeX RDF
19	Louis I. Steinberg, Tom M. Mitchell	The Redesign System: A Knowledge-Based Approach to VLSI CAD.	IEEE Des. Test	1985	DBLP DOI BibTeX RDF
19	Don S. Batory, Won Kim 0001	Modeling Concepts for VLSI CAD Objects (Abstract).	SIGMOD Conference	1985	DBLP DOI BibTeX RDF
19	Won Kim 0001, Don S. Batory	A Model and Storage Technique for Versions of VLSI CAD Objects.	FODO	1985	DBLP BibTeX RDF
19	Hamideh Afsarmanesh, Dennis McLeod, David Knapp, Alice C. Parker	An Extensible Object-Oriented Approach to Databases for VLSI/CAD.	VLDB	1985	DBLP BibTeX RDF
19	Louis I. Steinberg, Tom M. Mitchell	A knowledge based approach to VLSI CAD the redesign system.	DAC	1984	DBLP BibTeX RDF
19	Hal W. Daseking, Robert I. Gardner, Paul B. Weil	VISTA: A VLSI CAD System.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1982	DBLP DOI BibTeX RDF
19	Daniel L. Weinreb	High Performance Personal Computation for VLSI CAD.	COMPCON	1982	DBLP BibTeX RDF
18	Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Timing-driven variation-aware nonuniform clock mesh synthesis.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	clock mesh synthesis, non-tree clock networks, vlsi cad, power, process variations, physical design, clock skew, clock distribution
18	Ruchir Puri	Will 22nm be our catch 22!: design and cad challenges.	ISPD	2009	DBLP DOI BibTeX RDF	22nm cmos, design productivity, vlsi cad challenges, vlsi design challenges, vlsi physical design, 3d ics, automated synthesis
18	Anand Rajaram, David Z. Pan	Variation tolerant buffered clock network synthesis with cross links.	ISPD	2006	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
18	Sean X. Shi, Peng Yu, David Z. Pan	A unified non-rectangular device and circuit simulation model for timing and power.	ICCAD	2006	DBLP DOI BibTeX RDF	physical design, VLSI CAD, device modeling
18	Anand Rajaram, David Z. Pan, Jiang Hu	Improved algorithms for link-based non-tree clock networks for skew variability reduction.	ISPD	2005	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
18	Jill H. Y. Law, Evangeline F. Y. Young	Multi-bend bus driven floorplanning.	ISPD	2005	DBLP DOI BibTeX RDF	bus planning, floorplanning, VLSI CAD
18	Shin-ichi Minato	Streaming BDD Manipulation.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	algorithm, verification, testing, data structure, logic design, binary decision diagram, BDD, combinatorial problem, VLSI CAD
18	Jason Cong, Chang Wu	Global clustering-based performance-driven circuit partitioning.	ISPD	2002	DBLP DOI BibTeX RDF	clustering, partitioning, performance optimization, retiming, VLSI CAD
18	Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng	Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction.	SLIP	2002	DBLP DOI BibTeX RDF	rectilinear steiner tree algorithm, refined single trunk tree, routing estimation, VLSI CAD
18	Shin-ichi Minato	Zero-suppressed BDDs and their applications.	Int. J. Softw. Tools Technol. Transf.	2001	DBLP DOI BibTeX RDF	Boolean function, BDD, Combinatorial problem, VLSI CAD, ZBDD
18	Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung	An accurate evaluation of routing density for symmetrical FPGAs.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF	VLSI/CAD algorithm, symmetrical FPGA, FPGA routing
18	Donald S. Gelosh, Dorothy E. Setliff	Modeling layout tools to derive forward estimates of area and delay at the RTL level.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	estimation techniques, machine learning, estimation, layout, VLSI CAD
18	Dirk Stroobandt, Herwig Van Marck	Efficient representation of interconnection length distributions using generating polynomials.	SLIP	2000	DBLP DOI BibTeX RDF	interconnect length distributions, enumeration, VLSI CAD, generating polynomials
18	Jim E. Crenshaw, Majid Sarrafzadeh	Low Power Driven Scheduling and Binding.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	high level synthesis, low power design, design automation, VLSI CAD
18	Unni Narayanan, C. L. Liu 0001	Low power logic synthesis for XOR based circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	vlsi cad logic synthesis, XOR logic, Fixed Polarity Reed Muller Forms, Huffman Algorithm, low power design