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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 87 occurrences of 72 keywords
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Results
Found 49 publication records. Showing 49 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
64 | Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar |
A multiplier generator for Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 322-323, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs |
64 | Hardy J. Pottinger, Chien-Yuh Lin |
Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 242-245, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education |
54 | Gennadiy Kiryukhin, Mehmet Celenk |
Implementation of 2D-DCT on XC4000 series FPGA using DFT-based DSFG and DA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (3) ![In: Proceedings of the 2001 International Conference on Image Processing, ICIP 2001, Thessaloniki, Greece, October 7-10, 2001, pp. 302-305, 2001, IEEE, 0-7803-6725-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
54 | Xiaoling Sun, Jian Xu, Pieter M. Trouborst |
Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 221-, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
configurable logic blocks, fault diagnosis, BIST, FPGA testing |
37 | Xiaoling Sun, Pieter M. Trouborst |
A unified global and local interconnect test scheme for Xilinx XC4000 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 53(2), pp. 368-377, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 289-299, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, test, ATPG, iterative testing |
37 | Abdelkrim Kamel Oudjida, Sabrina Titri, Mustapha Hamerlain |
Synthesizing full-systolic arrays for matrix product on Xilinx's XC4000(E, EX) FPGAs (poster abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 222, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Deepak Rautela, Rajendra S. Katti |
Efficient utilization of heterogeneous routing resources for FPGAs (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 264, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel |
Power estimation approach for SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 195-202, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
Bridging Fault Detection in FPGA Interconnects Using IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 95-104, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Jason Cong, Yean-Yow Hwang |
Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 27-34, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Yao-Wen Chang, D. F. Wong 0001, C. K. Wong |
Universal switch modules for FPGA design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(1), pp. 80-101, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Radhika S. Grover, Weijia Shang, Qiang Li |
A faster distributed arithmetic architecture for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 31-39, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
DALUT, XC4000, carry propagation, cost-performance analysis, distributed arithmetic |
17 | Deepak Rautela, Rajendra S. Katti |
Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 232-237, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Martin Danek, Josef Kolár |
FPGA modelling for high-performance algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 251, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung |
On optimal hyperuniversal and rearrangeable switch box designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12), pp. 1637-1649, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe |
An estimation and exploration methodology from system-level specifications: application to FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 239, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Seokjin Lee, Hua Xiang 0001, D. F. Wong 0001, Richard Y. Sun |
Wire type assignment for FPGA routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 61-67, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
min-cost flow algorithm, wire type assignment, FPGA routing |
17 | Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet |
Fast prototyping of reconfigurable architectures from a C program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 589-592, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Hassan Ibrahim Saleh, M. A. Ashour, Aly E. Salama |
GDFT types mapping algorithms and structured regular FPGA implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 129-132, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong |
Reduction design for generic universal switch blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(4), pp. 526-546, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA architecture design, routing requirement, switch module, universal switch block, routing, decomposition |
17 | Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung |
On Optimum Designs of Universal Switch Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 142-151, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Xiaoling Sun, A. Alimohammad, Pieter M. Trouborst |
Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 284-292, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
global/local interconnect testing, modeling, graph coloring, greedy algorithms, FPGA testing |
17 | Hongbing Fan, Jiping Liu, Yu-Liang Wu |
Combinatorial routing analysis and design of universal switch blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 641-644, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Tilman Neumann, Andreas Koch |
A Generic Library for Adaptive Computing Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 503-512, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Xiaoling Sun, Jian Xu, Pieter M. Trouborst |
Testing Carry Logic Modules of SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, CA, USA, pp. 91-98, 2001, IEEE Computer Society, 0-7695-1242-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi |
An Approach for Detecting Multiple Faulty FPGA Logic Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(1), pp. 48-54, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fault tolerance, FPGA, multiple faults, C-testability, PLD |
17 | Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang |
Generic Universal Switch Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(4), pp. 348-359, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
design, architecture, Analysis, digital, programmable logic array, gate array |
17 | Kazimierz Wiatr, Ernest Jamro |
Constant Coefficient Multiplication in FPGA Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1252-1259, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Min Xu, Fadi J. Kurdahi |
Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(4), pp. 411-418, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Abderrahim Doumar, Hideo Ito |
Testing the Logic Cells and Interconnect Resources for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 369-374, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 375-, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Thomas Blum |
Montgomery Modular Exponentiation on Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 70-77, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Katriina Heikkinen, Petri Vuorimaa |
Computation of Two Texture Features in Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIAP ![In: 1oth International Conference on Image Analysis and Processing (ICIAP 1999), 27-29 September 1999, Venice, Italy, pp. 125-129, 1999, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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17 | Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor |
FPGA-Based Structures for On-Line FFT and DCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 310-311, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGA, interconnect, MAC, FFT, signal processing, DCT, online, on-line, distributed arithmetic, bit-serial, xilinx, on-line arithmetic |
17 | K. K. Lee, D. F. Wong 0001 |
An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 216-221, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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17 | Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang |
Generic Universal Switch Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 311-314, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
HFPGA, logic block, switch block, programmable switch, universal switch block, dimension constraint, FPGA, routing, flexibility, routability |
17 | John Marty Emmert, Dinesh Bhatia |
Fast timing driven placement using tabu search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 302-305, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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17 | Delon Levi, Steve Guccione |
GeneticFPGA: Evolving Stable Circuits on Mainstream FPGA Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), July 19-21, 1999, Pasadena, CA, USA, pp. 12-17, 1999, IEEE Computer Society, 0-7695-0256-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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17 | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(10), pp. 1136-1152, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Hans-Georg Martin, Wolfgang Rosenstiel |
A Comparing Study of Technology Mapping for FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 939-940, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
mapping for routability, computation time, design alternatives, FPGA design |
17 | Juri Põldre, Kalle Tammemäe, Marek Mandre |
Modular Exponent Realization on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 336-347, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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17 | John Marty Emmert, Akash Randhar, Dinesh Bhatia |
Fast Floorplanning for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 129-138, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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17 | Wenyi Feng, Fred J. Meyer, Wei-Kang Huang, Fabrizio Lombardi |
On the Complexity of Sequential Testing in Configurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 164-, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
FPGA, pipeline, PLD, sequential testing, iterative array |
17 | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1037-1046, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
IDDQ Tes t, Configurable Logic Blocks, FPGA, Testing, Bridging Fault, Programming Phase |
17 | Jason Cong, Songjie Xu |
Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 704-707, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
technology mapping, programmable logic devices, PLA-style logic blocks |
17 | Madhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao |
A Technology Mapper for Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 57-61, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic |
Minimizing FPGA Interconnect Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 13(4), pp. 16-23, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Pierre Abouzeid, Belgacem Babba, Michel Crastes de Paulet, Gabriele Saucier |
Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7), pp. 913-925, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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