Search results for "XC4000"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
64	Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
64	Hardy J. Pottinger, Chien-Yuh Lin	Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
54	Gennadiy Kiryukhin, Mehmet Celenk	Implementation of 2D-DCT on XC4000 series FPGA using DFT-based DSFG and DA architectures.	ICIP (3)	2001	DBLP DOI BibTeX RDF
54	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules.	DFT	2001	DBLP DOI BibTeX RDF	configurable logic blocks, fault diagnosis, BIST, FPGA testing
37	Xiaoling Sun, Pieter M. Trouborst	A unified global and local interconnect test scheme for Xilinx XC4000 FPGAs.	IEEE Trans. Instrum. Meas.	2004	DBLP DOI BibTeX RDF
37	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	FPGA, test, ATPG, iterative testing
37	Abdelkrim Kamel Oudjida, Sabrina Titri, Mustapha Hamerlain	Synthesizing full-systolic arrays for matrix product on Xilinx's XC4000(E, EX) FPGAs (poster abstract).	FPGA	2000	DBLP DOI BibTeX RDF
34	Deepak Rautela, Rajendra S. Katti	Efficient utilization of heterogeneous routing resources for FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
34	Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel	Power estimation approach for SRAM-based FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
34	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Bridging Fault Detection in FPGA Interconnects Using IDDQ.	FPGA	1998	DBLP DOI BibTeX RDF
34	Jason Cong, Yean-Yow Hwang	Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation.	FPGA	1998	DBLP DOI BibTeX RDF
34	Yao-Wen Chang, D. F. Wong 0001, C. K. Wong	Universal switch modules for FPGA design.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF
31	Radhika S. Grover, Weijia Shang, Qiang Li	A faster distributed arithmetic architecture for FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF	DALUT, XC4000, carry propagation, cost-performance analysis, distributed arithmetic
17	Deepak Rautela, Rajendra S. Katti	Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources.	ISVLSI	2005	DBLP DOI BibTeX RDF
17	Martin Danek, Josef Kolár	FPGA modelling for high-performance algorithms.	FPGA	2004	DBLP DOI BibTeX RDF
17	Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung	On optimal hyperuniversal and rearrangeable switch box designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
17	Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe	An estimation and exploration methodology from system-level specifications: application to FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
17	Seokjin Lee, Hua Xiang 0001, D. F. Wong 0001, Richard Y. Sun	Wire type assignment for FPGA routing.	FPGA	2003	DBLP DOI BibTeX RDF	min-cost flow algorithm, wire type assignment, FPGA routing
17	Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet	Fast prototyping of reconfigurable architectures from a C program.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
17	Hassan Ibrahim Saleh, M. A. Ashour, Aly E. Salama	GDFT types mapping algorithms and structured regular FPGA implementation.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
17	Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong	Reduction design for generic universal switch blocks.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA architecture design, routing requirement, switch module, universal switch block, routing, decomposition
17	Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung	On Optimum Designs of Universal Switch Blocks.	FPL	2002	DBLP DOI BibTeX RDF
17	Xiaoling Sun, A. Alimohammad, Pieter M. Trouborst	Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations.	DFT	2002	DBLP DOI BibTeX RDF	global/local interconnect testing, modeling, graph coloring, greedy algorithms, FPGA testing
17	Hongbing Fan, Jiping Liu, Yu-Liang Wu	Combinatorial routing analysis and design of universal switch blocks.	ASP-DAC	2001	DBLP DOI BibTeX RDF
17	Tilman Neumann, Andreas Koch	A Generic Library for Adaptive Computing Environments.	FPL	2001	DBLP DOI BibTeX RDF
17	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Carry Logic Modules of SRAM-based FPGAs.	MTDT	2001	DBLP DOI BibTeX RDF
17	Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	An Approach for Detecting Multiple Faulty FPGA Logic Blocks.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	fault tolerance, FPGA, multiple faults, C-testability, PLD
17	Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang	Generic Universal Switch Blocks.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	design, architecture, Analysis, digital, programmable logic array, gate array
17	Kazimierz Wiatr, Ernest Jamro	Constant Coefficient Multiplication in FPGA Structures.	EUROMICRO	2000	DBLP DOI BibTeX RDF
17	Min Xu, Fadi J. Kurdahi	Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
17	Abderrahim Doumar, Hideo Ito	Testing the Logic Cells and Interconnect Resources for FPGAs.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
17	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
17	Thomas Blum	Montgomery Modular Exponentiation on Reconfigurable Hardware.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
17	Katriina Heikkinen, Petri Vuorimaa	Computation of Two Texture Features in Hardware.	ICIAP	1999	DBLP DOI BibTeX RDF
17	Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor	FPGA-Based Structures for On-Line FFT and DCT.	FCCM	1999	DBLP DOI BibTeX RDF	FPGA, interconnect, MAC, FFT, signal processing, DCT, online, on-line, distributed arithmetic, bit-serial, xilinx, on-line arithmetic
17	K. K. Lee, D. F. Wong 0001	An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs.	ICCD	1999	DBLP DOI BibTeX RDF
17	Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang	Generic Universal Switch Blocks.	ICCD	1999	DBLP DOI BibTeX RDF	HFPGA, logic block, switch block, programmable switch, universal switch block, dimension constraint, FPGA, routing, flexibility, routability
17	John Marty Emmert, Dinesh Bhatia	Fast timing driven placement using tabu search.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
17	Delon Levi, Steve Guccione	GeneticFPGA: Evolving Stable Circuits on Mainstream FPGA Devices.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
17	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF
17	Hans-Georg Martin, Wolfgang Rosenstiel	A Comparing Study of Technology Mapping for FPGA.	DATE	1998	DBLP DOI BibTeX RDF	mapping for routability, computation time, design alternatives, FPGA design
17	Juri Põldre, Kalle Tammemäe, Marek Mandre	Modular Exponent Realization on FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
17	John Marty Emmert, Akash Randhar, Dinesh Bhatia	Fast Floorplanning for FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
17	Wenyi Feng, Fred J. Meyer, Wei-Kang Huang, Fabrizio Lombardi	On the Complexity of Sequential Testing in Configurable FPGAs.	DFT	1998	DBLP DOI BibTeX RDF	FPGA, pipeline, PLD, sequential testing, iterative array
17	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ.	ITC	1998	DBLP DOI BibTeX RDF	IDDQ Tes t, Configurable Logic Blocks, FPGA, Testing, Bridging Fault, Programming Phase
17	Jason Cong, Songjie Xu	Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
17	Madhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao	A Technology Mapper for Xilinx FPGAs.	VLSI Design	1997	DBLP DOI BibTeX RDF
17	Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic	Minimizing FPGA Interconnect Delays.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
17	Pierre Abouzeid, Belgacem Babba, Michel Crastes de Paulet, Gabriele Saucier	Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF