Search results for "XOR"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
110	Hirotaka Yoshida, Alex Biryukov	Analysis of a SHA-256 Variant.	Selected Areas in Cryptography	2005	DBLP DOI BibTeX RDF	SHA-2-XOR, SHACAL-2-XOR, Pseudo-collision resistance, Iterative patterns, Differential cryptanalysis, SHA-256
102	Ralf Küsters, Tomasz Truderung	Reducing protocol analysis with XOR to the XOR-free case in the horn theory based approach.	CCS	2008	DBLP DOI BibTeX RDF	security protocols, algebraic properties
87	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
80	Ajay Kumar Verma, Paolo Ienne	Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.	ASP-DAC	2007	DBLP DOI BibTeX RDF	multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers
71	Michael Backes 0001, Birgit Pfitzmann	Limits of the BRSIM/UC soundness of Dolev-Yao-style XOR.	Int. J. Inf. Sec.	2008	DBLP DOI BibTeX RDF	Dolev-Yao-style, Reactive simulatability/UC, Limitations, XOR, Computational soundness
71	Pim Tuyls, Henk D. L. Hollmann, Jack H. van Lint, Ludo M. G. M. Tolhuizen	XOR-based Visual Cryptography Schemes.	Des. Codes Cryptogr.	2005	DBLP DOI BibTeX RDF	Threshold visual secret sharing schemes, XOR, MDS codes
70	Unni Narayanan, C. L. Liu 0001	Low power logic synthesis for XOR based circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	vlsi cad logic synthesis, XOR logic, Fixed Polarity Reed Muller Forms, Huffman Algorithm, low power design
65	Seok-Bum Ko	Area Minimization of Exclusive-OR Intensive Circuits in FPGAs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	FPGA, XOR, ESOP
64	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture
61	Hans Vandierendonck, Koenraad De Bosschere	XOR-Based Hash Functions.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	XOR-based hash function, conflict-free mapping, column space, skewed-associative cache, interbank dispersion, null space
60	Hans Vandierendonck, Philippe Manet, Jean-Didier Legat	Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses.	DATE	2006	DBLP DOI BibTeX RDF
60	Yibin Ye, Kaushik Roy 0001, Rolf Drechsler	Power Consumption in XOR-Based Circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
56	Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu	High-speed generation of LFSR signatures.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	high-speed generation, LFSR signatures, compaction simulation, single-input signature register, equivalent multiple-input implementation, finite field theory, high-speed signature computations, lookahead technique, internal-XOR LFSR, external-XOR LFSR, performance evaluation, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, BIST, linear feedback shift register, binary sequences, subsequences
53	Hirosato Seki, Satoshi Watanabe, Hiroaki Ishii, Masaharu Mizumoto	Realization of XOR by SIRMs Connected Fuzzy Inference Method.	IEA/AIE	2009	DBLP DOI BibTeX RDF	SIRMs connected fuzzy inference method, neural network, Fuzzy Inference, XOR
53	Wei-Kang Huang, M. Y. Zhang, Fred J. Meyer, Fabrizio Lombardi	A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	programmable system, diagnosis, FPGA testing, XOR
52	Jingchao Chen	Building a Hybrid SAT Solver via Conflict-Driven, Look-Ahead and XOR Reasoning Techniques.	SAT	2009	DBLP DOI BibTeX RDF	Conflict-driven, XOR reasoning, Hybrid solving technique, search pruning technique, Look-ahead, Boolean satisfiability (SAT)
52	Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi	Noise tolerant low voltage XOR-XNOR for fast arithmetic.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	XOR-XNOR circuits, multipliers, noise tolerant, deep submicron, nanometer technology
51	Xihui Chen, Ton van Deursen, Jun Pang 0001	Improving Automatic Verification of Security Protocols with XOR.	ICFEM	2009	DBLP DOI BibTeX RDF
51	Richard Cleve, William Slofstra, Falk Unger, Sarvagya Upadhyay	Perfect Parallel Repetition Theorem for Quantum Xor Proof Systems.	Comput. Complex.	2008	DBLP DOI BibTeX RDF	Subject classification. 81P68, 68Q10
51	Rajesh Prasad, Hongyi Wu, Dmitri D. Perkins, Nian-Feng Tzeng	Local Topology Assisted XOR Coding in Wireless Mesh Networks.	ICDCS Workshops	2008	DBLP DOI BibTeX RDF
51	Jay J. Wylie, Ram Swaminathan	Determining Fault Tolerance of XOR-Based Erasure Codes Efficiently.	DSN	2007	DBLP DOI BibTeX RDF
51	Emanuele Viola, Avi Wigderson	Norms, XOR Lemmas, and Lower Bounds for GF(2) Polynomials and Multiparty Protocols.	CCC	2007	DBLP DOI BibTeX RDF
51	Richard Cleve, William Slofstra, Falk Unger, Sarvagya Upadhyay	Perfect Parallel Repetition Theorem for Quantum XOR Proof Systems.	CCC	2007	DBLP DOI BibTeX RDF
51	Tamar Barzuza, Jacques S. Beckmann, Ron Shamir, Itsik Pe'er	Computational Problems in Perfect Phylogeny Haplotyping: Xor-Genotypes and Tag SNPs.	CPM	2004	DBLP DOI BibTeX RDF
51	Seok-Bum Ko, Jien-Chung Lo	A Novel Technology Mapping Method for AND/XOR Expressions.	ISMVL	2003	DBLP DOI BibTeX RDF
47	Zhou Xu, Xianliang Lu, Hou Mengshu	DCFS: distributed cooperative fault-tolerance storage mechanism.	ACM SIGOPS Oper. Syst. Rev.	2004	DBLP DOI BibTeX RDF	fault-tolerant, graph theory, distributed, cooperative, XOR
46	Hamed F. Dadgour, Muhammad Mustafa Hussain, Kaustav Banerjee	A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs.	ISLPED	2010	DBLP DOI BibTeX RDF	Boolean logic minimization, energy-efficient electronics, laterally-actuated NEMS, nanoelectromechanical switches, XOR gates
46	Tamar Barzuza, Jacques S. Beckmann, Ron Shamir, Itsik Pe'er	Computational Problems in Perfect Phylogeny Haplotyping: Typing without Calling the Allele.	IEEE ACM Trans. Comput. Biol. Bioinform.	2008	DBLP DOI BibTeX RDF	XOR-genotypes, Graph Realization, Haplotypes, Perfect Phylogeny
46	Seok-Bum Ko, Jien-Chung Lo	Efficient Realization of Parity Prediction Functions in FPGAs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	parity prediciton functions, Davio''s expansion, AND/XOR expressions, FPGA, technology mapping
45	Tomasz S. Czajkowski, Stephen Dean Brown	Functionally linear decomposition and synthesis of logic circuits for FPGAs.	DAC	2008	DBLP DOI BibTeX RDF	decomposition, logic synthesis, linearity, Gaussian elimination
42	Takaaki Mizuki, Hideaki Sone	Six-Card Secure AND and Four-Card Secure XOR.	FAW	2009	DBLP DOI BibTeX RDF
42	Peter Sobe, Kathrin Peter	Flexible Parameterization of XOR based Codes for Distributed Storage.	NCA	2008	DBLP DOI BibTeX RDF	Erasure-tolerant Codes, Distribute Storage
42	Kevin M. Greenan, Ethan L. Miller, Jay J. Wylie	Reliability of flat XOR-based erasure codes on heterogeneous devices.	DSN	2008	DBLP DOI BibTeX RDF
42	Hans Vandierendonck, Koen De Bosschere	Constructing Optimal XOR-Functions to Minimize Cache Conflict Misses.	ARCS	2008	DBLP DOI BibTeX RDF
42	Ralf Küsters, Tomasz Truderung	On the Automatic Analysis of Recursive Security Protocols with XOR.	STACS	2007	DBLP DOI BibTeX RDF
42	Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang	A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM.	ISCAS	2006	DBLP DOI BibTeX RDF
42	Michael Backes 0001, Birgit Pfitzmann	Limits of the Cryptographic Realization of Dolev-Yao-Style XOR.	ESORICS	2005	DBLP DOI BibTeX RDF
42	Xu Zhou, Xianliang Lu, Meng-shu Hou, Chuan Zhan	A Novel XOR-Based Fault-Tolerance Mechanism for Distributed Storage System.	CIT	2004	DBLP DOI BibTeX RDF
42	Kumar Neeraj Verma	Alternation in Equational Tree Automata Modulo XOR.	FSTTCS	2004	DBLP DOI BibTeX RDF
42	Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	logic synthesis, PLA
42	Song Chen, Adam Postula, Lech Józwiak	Synthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention.	EUROMICRO	1999	DBLP DOI BibTeX RDF
38	Philip Hawkes, Luke O'Connor	XOR and Non-XOR Differential Probabilities.	EUROCRYPT	1999	DBLP DOI BibTeX RDF
37	Zhi-Guo Chen, Stafford E. Tavares	Toward Provable Security of Substitution-Permutation Encryption Networks.	Selected Areas in Cryptography	1998	DBLP DOI BibTeX RDF	XOR table, block cipher, provable security, nonlinearity, differential attack
36	Tomasz S. Czajkowski, Stephen Dean Brown	Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
36	Moonseo Park, Seong-Lyun Kim	Minimum distortion network code design for source coding over noisy channels.	PIMRC	2008	DBLP DOI BibTeX RDF
36	Benessa Defend, Kevin Fu, Ari Juels	Cryptanalysis of Two Lightweight RFID Authentication Schemes.	PerCom Workshops	2007	DBLP DOI BibTeX RDF
36	Carla P. Gomes, Jörg Hoffmann 0001, Ashish Sabharwal, Bart Selman	Short XORs for Model Counting: From Theory to Practice.	SAT	2007	DBLP DOI BibTeX RDF
36	John Maher, Brian McGinley, Patrick Rocke, Fearghal Morgan	Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices.	FCCM	2006	DBLP DOI BibTeX RDF
36	Elchanan Mossel, Amir Shpilka, Luca Trevisan	On e-Biased Generators in NC0.	FOCS	2003	DBLP DOI BibTeX RDF
36	Anna Gál, Adi Rosén	Lower bounds on the amount of randomness in private computation.	STOC	2003	DBLP DOI BibTeX RDF	lower bounds, randomness, private computation
36	Seok-Bum Ko, Jien-Chung Lo	Efficient Decomposition Techniques for FPGAs.	HiPC	2002	DBLP DOI BibTeX RDF
36	Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal	BDD Decomposition for Efficient Logic Synthesis.	ICCD	1999	DBLP DOI BibTeX RDF	Decomposition, Logic Synthesis, BDD, Dominators
36	Luke O'Connor	On the Distribution of Characteristics in Composite Permutations.	CRYPTO	1993	DBLP DOI BibTeX RDF	iterated mapping, product cipher, Differential cryptanalysis
34	Akhil Kumar 0001, Anup K. Sen, Meda H. Sundari, Amitava Bagchi	Semantic Notions of Weakly Correct AND/XOR Business Workflows Based on Partial Synchronization.	IEEE SCC	2011	DBLP DOI BibTeX RDF	AND/XOR graphs, s-correctness, partial synchronization, corresponding pairs, r-soundness
34	Antonio González 0001, Mateo Valero, Nigel P. Topham, Joan-Manuel Parcerisa	Eliminating Cache Conflict Misses through XOR-Based Placement Functions.	International Conference on Supercomputing	1997	DBLP DOI BibTeX RDF	XOR-based placement functions, cache memory, conflict misses
34	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Reed Muller form, AND-XOR network synthesis, fixed-polarity canonical expansion, genetic algorithm
33	Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao	Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints.	ASP-DAC	2009	DBLP DOI BibTeX RDF
33	Jean Vuillemin, Nicolas Gama	Compact Normal Form for Regular Languages as Xor Automata.	CIAA	2009	DBLP DOI BibTeX RDF
33	Paola Bonizzoni, Gianluca Della Vedova, Riccardo Dondi, Yuri Pirola, Romeo Rizzi	Pure Parsimony Xor Haplotyping.	ISBRA	2009	DBLP DOI BibTeX RDF
33	Helmut Seidl, Kumar Neeraj Verma	Flat and One-Variable Clauses for Single Blind Copying Protocols: The XOR Case.	RTA	2009	DBLP DOI BibTeX RDF
33	Vladimir Kolesnikov, Thomas Schneider 0003	Improved Garbled Circuit: Free XOR Gates and Applications.	ICALP (2)	2008	DBLP DOI BibTeX RDF
33	Carlo Blundo, Clemente Galdi, Giuseppe Persiano	Low-randomness constant-round private XOR computations.	Int. J. Inf. Sec.	2007	DBLP DOI BibTeX RDF	Randomness, Multiparty computation
33	Noga Alon, Eyal Lubetzky	Codes And Xor Graph Products.	Comb.	2007	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000): 05C69, 94A15
33	Arie Yeredor	ICA in Boolean XOR Mixtures.	ICA	2007	DBLP DOI BibTeX RDF
33	Sung Jin Cho 0001, Un-Sook Choi, Yoon-Hee Hwang, Han-Doo Kim	Modeling Efficient XOR-Based Hash Functions for Cache Memories.	International Conference on Computational Science (1)	2006	DBLP DOI BibTeX RDF
33	Graham Steel	Deduction with XOR Constraints in Security API Modelling.	CADE	2005	DBLP DOI BibTeX RDF
33	Christopher J. Martinez, Wei-Ming Lin, Parimal Patel	Optimal XOR hashing for a linearly distributed address lookup in computer networks.	ANCS	2005	DBLP DOI BibTeX RDF	address lookup, packet matching, internet, intrusion detection, network security, computer networks, hashing
33	Ping-Hsun Hsieh, Ing-Yi Chen, Yu-Ting Lin, Sy-Yen Kuo	An XOR Based Reed-Solomon Algorithm for Advanced RAID Systems.	DFT	2004	DBLP DOI BibTeX RDF
33	Yannick Chevalier, Ralf Küsters, Michaël Rusinowitch, Mathieu Turuani	An NP Decision Procedure for Protocol Insecurity with XOR.	LICS	2003	DBLP DOI BibTeX RDF
33	Sarvar Patel, Zulfikar Ramzan, Ganapathy S. Sundaram	Luby-Rackoff Ciphers: Why XOR Is Not So Exclusive.	Selected Areas in Cryptography	2002	DBLP DOI BibTeX RDF
33	Yinshui Xia, A. E. A. Almaini	Best Polarity for Low Power XOR Gate Decomposition.	DSD	2002	DBLP DOI BibTeX RDF
33	Madhu Sudan 0001, Luca Trevisan, Salil P. Vadhan	Pseudorandom Generators without the XOR Lemma (Abstract).	CCC	1999	DBLP DOI BibTeX RDF	polynomial reconstruct ion, Pseudorandom generators, extractors, list-decoding
33	Yibin Ye, Kaushik Roy 0001	A Graph-Based Synthesis Algorithm for AND/XOR Networks.	DAC	1997	DBLP DOI BibTeX RDF
29	Anna Bernasconi 0001, Alessandro Berti, Valentina Ciriani, Gianna M. Del Corso, Innocenzo Fulginiti	XOR-AND-XOR Logic Forms for Autosymmetric Functions and Applications to Quantum Computing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
29	Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu	Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
29	Ragesh Jaiswal	A note on the relation between XOR and Selective XOR lemmas.	Inf. Process. Lett.	2020	DBLP DOI BibTeX RDF
29	Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu	XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption.	ICCAD	2020	DBLP DOI BibTeX RDF
29	María Naya-Plasencia, André Schrottenloher	Optimal Merging in Quantum k-xor and k-xor-sum Algorithms.	EUROCRYPT (2)	2020	DBLP DOI BibTeX RDF
29	Ragesh Jaiswal	A note on the relation between XOR and Selective XOR Lemmas.	Electron. Colloquium Comput. Complex.	2019	DBLP BibTeX RDF
29	Ivo Hálecek, Petr Fiser, Jan Schmidt	Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
29	Eduardo Silva Palmeira, Benjamín R. C. Bedregal	Some Results on Extension of Lattice-Valued XOR, XOR-Implications and E-Implications.	IPMU (2)	2016	DBLP DOI BibTeX RDF
29	Vladimir Kolesnikov, Payman Mohassel, Mike Rosulek	FleXOR: Flexible garbling for XOR gates that beats free-XOR.	IACR Cryptol. ePrint Arch.	2014	DBLP BibTeX RDF
29	Vladimir Kolesnikov, Payman Mohassel, Mike Rosulek	FleXOR: Flexible Garbling for XOR Gates That Beats Free-XOR.	CRYPTO (2)	2014	DBLP DOI BibTeX RDF
29	Benjamín René Callejas Bedregal, Renata Hax Sander Reiser, Graçaliz Pereira Dimuro	Revisiting XOR-Implications: Classes of fuzzy (Co)Implications Based on F-XOR (F-XNOR) Connectives.	Int. J. Uncertain. Fuzziness Knowl. Based Syst.	2013	DBLP DOI BibTeX RDF
29	Harold S. Connamacher	Exact thresholds for DPLL on random XOR-SAT and NP-complete extensions of XOR-SAT.	Theor. Comput. Sci.	2012	DBLP DOI BibTeX RDF
29	Ralf Küsters, Tomasz Truderung	Reducing Protocol Analysis with XOR to the XOR-Free Case in the Horn Theory Based Approach.	J. Autom. Reason.	2011	DBLP DOI BibTeX RDF
29	Benjamín R. C. Bedregal, Renata Hax Sander Reiser, Graçaliz Pereira Dimuro	Xor-Implications and E-Implications: Classes of Fuzzy Implications Based on Fuzzy Xor.	LSFA	2008	DBLP DOI BibTeX RDF
29	Ralf Küsters, Tomasz Truderung	Reducing Protocol Analysis with XOR to the XOR-free Case in the Horn Theory Based Approach	CoRR	2008	DBLP BibTeX RDF
29	Qingsong Wei, Xianliang Lu, Xu Zhou	DFTS: a novel distributed high fault-tolerance storage mechanism.	ACM SIGOPS Oper. Syst. Rev.	2003	DBLP DOI BibTeX RDF	fault-tolerance, network, distributed, storage, fragment, XOR
28	Jian Li 0015, Amol Deshpande	Consensus answers for queries over probabilistic databases.	PODS	2009	DBLP DOI BibTeX RDF	consensus answers, probabilistic and/xor tree, query processing, probabilistic databases, rank aggregation
28	Yuri B. Boiko, Gabriel A. Wainer	Modeling quantum dot devices in Cell-DEVS environment.	SpringSim	2008	DBLP DOI BibTeX RDF	majority vote gates, quantum wire, cellular automata, discrete event simulation, quantum dot, XOR gates, cell-DEVS, quantum automata
28	Russell Impagliazzo, Ragesh Jaiswal, Valentine Kabanets, Avi Wigderson	Uniform direct product theorems: simplified, optimized, and derandomized.	STOC	2008	DBLP DOI BibTeX RDF	direct product code, xor code, direct product theorem
28	S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
28	Rigui Zhou, Nan Jiang, Qiulin Ding	Model and Training of QNN with Weight.	Neural Process. Lett.	2006	DBLP DOI BibTeX RDF	grover algorithm, QNN with weight, XOR problem, training algorithm
28	Yicheng Huang, Jari Korhonen, Ye Wang 0007	Optimization of source and channel coding for voice over IP.	ICME	2005	DBLP DOI BibTeX RDF	speech transmission system, source-channel coding optimization, adaptive multirate, speech codec, XOR operation, simplified E-model, VoIP, forward error correction, FEC, voice over Internet protocol, round trip time, AMR, exclusive OR, RTT
28	Min Zhao 0001, Sachin S. Sapatnekar	Technology mapping algorithms for domino logic.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	XOR/XNOR logic, dual-monotonic gates, parameterized library, phase assignment, synthesis, technology mapping, Domino logic
28	J. Salerno	Using the Particle Swarm Optimization Technique to Train a Recurrent Neural Model.	ICTAI	1997	DBLP DOI BibTeX RDF	particle swarm optimization technique, recurrent neural model training, evolutionary learning technique, neural model architectures, XOR problem, natural language phrase parsing, multilayered feedforward network, recurrent neural nets
28	Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan	A linear code-preserving signature analyzer COPMISR.	VTS	1997	DBLP DOI BibTeX RDF	linear separable code, code preserving multi-input signature register, COPMISR, concurrent checking, parity code, group -parity code, BIST, linear codes, Hamming code, duplication code, XOR-gate, signature analyzer, on-line error detection
28	Yu Fang, Alexander Albicki	Efficient testability enhancement for combinational circuit.	ICCD	1995	DBLP DOI BibTeX RDF	testability enhancement, combinational circuit testing, XOR Chain Structure, insertion points, random pattern resistant node source tracking, ISCAS85, performance evaluation, VLSI, VLSI, logic testing, controllability, built-in self test, combinational circuits, automatic testing, automatic testing, observability, testability analysis, benchmark circuits, hardware overhead, performance penalty
28	M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor	Compact test sets for industrial circuits.	VTS	1995	DBLP DOI BibTeX RDF	compact test sets, industrial circuits, binary logic elements, three-state elements, compaction oriented decision making, heuristics, logic testing, integrated circuit testing, automatic test pattern generation, combinational circuits, automatic testing, multivalued logic circuits, test patterns, bidirectionals, xor gates, or gates, test set size