Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
101 | Yan Sun, Xin Zhang, Xi Jin |
High-Performance Carry Select Adder Using Fast All-One Finding Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: Second Asia International Conference on Modelling and Simulation, AMS 2008, Kuala Lumpur, Malaysia, May 13-15, 2008, pp. 1012-1014, 2008, IEEE Computer Society, 978-0-7695-3136-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
fast all-one finding circuit, add-one circuit, carry-select adder |
99 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 148-152, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
97 | Akhilesh Tyagi |
A Reduced-Area Scheme for Carry-Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(10), pp. 1163-1170, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders |
95 | Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld |
Modulo p=3 Checking for a Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(1), pp. 101-107, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
concurrent checking, modulo checking, carry select adder |
92 | Vitit Kantabutra |
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(12), pp. 1495-1499, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
recursive carry-lookahead/carry-select hybrid adder, double-precision mantissas, spanning tree carry lookahead adder, redundant cell adder, Am29050 microprocessor, Manchester carry chains, delays, adders |
82 | Keshab K. Parhi |
Low-energy CSMT carry generators and binary adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(4), pp. 450-462, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
79 | Youngjoon Kim, Lee-Sup Kim |
A low power carry select adder with reduced area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 218-221, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
73 | Vitalij Ocheretnij, Daniel Marienfeld, Egor S. Sogomonyan, Michael Gössel |
Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 31-36, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
70 | Yiran Chen 0001, Hai Li 0001, Kaushik Roy 0001, Cheng-Kok Koh |
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 115-118, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low-power, carry-select adder |
70 | Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy 0001 |
Low-power carry-select adder using adaptive supply voltage based on input vector patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 313-318, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
adaptive supply voltage, low power adder, carry-select adder |
61 | Jin-Fu Li 0001, Jiunn-Der Yu, Yu-Jen Huang |
A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 77-80, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
61 | Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld |
A Modulo p Checked Self-Checking Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 25-29, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
57 | Egor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel |
A New Self-Checking Sum-Bit Duplicated Carry-Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1360-1361, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
56 | Morteza Dorrigiv, Ghassem Jaberipur |
Low area/power decimal addition with carry-select correction and carry-select sum-digits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 47(4), pp. 443-451, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
54 | Yajuan He, Chip-Hong Chang, Jiangmin Gu |
An area efficient 64-bit square root carry-select adder for low power applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4082-4085, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Dilip P. Vasudevan, Parag K. Lala |
A Technique for Modular Design of Self-Checking Carry-Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 325-333, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Youngjoon Kim, Ki-Hyuk Sung, Lee-Sup Kim |
A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 461-464, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
45 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry |
High-performance carry chains for FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 138-147, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
45 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry |
High-Performance Carry Chains for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 223-233, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
43 | |
Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Ambient Intell. Humaniz. Comput. ![In: J. Ambient Intell. Humaniz. Comput. 12(5), pp. 5513-5524, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
43 | Mehedi Hasan, Muhammad Saddam Hossain, Abdul Hasib Siddique, Mainul Hossain, Hasan U. Zaman, Sharnali Islam |
A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 109, pp. 104992, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
43 | Minho Nam, Yeonhun Choi, Kyoung-Rok Cho |
High-speed and energy efficient carry select adder (CSLA) dominated by carry generation logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 79, pp. 70-78, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
43 | Habib Ghasemizadeh Tamar, Akbar Ghasemizadeh Tamar, Khayrollah Hadidi, Abdollah Khoei, Pourya Hoseini |
High speed area reduced 64-bit static hybrid carry-lookahead/carry-select adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, pp. 460-463, 2011, IEEE, 978-1-4577-1845-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
43 | Yajuan He, Chip-Hong Chang |
A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(1), pp. 336-346, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy 0001 |
Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 90-C(4), pp. 865-876, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Gustavo A. Ruiz, Mercedes Granda |
An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 35(12), pp. 939-944, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka |
A fast hybrid carry-lookahead/carry-select adder design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001, pp. 149-152, 2001, ACM, 1-58113-351-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
CMOS, domino logic, carry lookahead adder |
42 | Jongsun Park 0001, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy 0001 |
High performance and low power FIR filter design based on sharing multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 295-300, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FIR filter design, computation sharing, conditional capture flip-flop, high performance and low power carry select adder |
42 | Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto |
A 13.3ns double-precision floating-point ALU and multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 466-470, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
double-precision floating-point ALU, floating-point multiplier, carry select addition, prerounding techniques, noise tolerant precharge circuit, two-cycle latency, 13.3 ns, 0.3 micron, 2.5 V, 150 MHz, normalization, floating point arithmetic, CMOS integrated circuits, multiplying circuits, CMOS technology, arithmetic logic unit |
38 | Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait |
Area-time optimal adder with relative placement generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 141-144, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Alireza Namazi, Seyed Ghassem Miremadi, Alireza Ejlali |
A High Speed and Low Cost Error Correction Technique for the Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Forth International Conference on Availability, Reliability and Security, ARES 2009, March 16-19, 2009, Fukuoka, Japan, pp. 635-640, 2009, IEEE Computer Society, 978-1-4244-3572-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | B. Kiran Kumar, Parag K. Lala |
On-line Detection of Faults in Carry-Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 912-918, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig 0004, Gerhard Hellner |
Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 108-111, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
SOI technology, logic design styles, circuit Design |
36 | Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris |
Fast adders in modern FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 250, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis |
A Low-Power Carry Skip Adder with Fast Saturation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 269-279, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Hong Diep Nguyen, Bogdan Pasca 0001, Thomas B. Preußer |
FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 232-237, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
carry-chain, carry-select, carry-increment, FPGA, addition |
31 | Johannes Grad, James E. Stine |
Low power binary addition using carry increment adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Andrew Beaumont-Smith, Cheng-Chew Lim |
Parallel Prefix Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 218-, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Perumal Mahendran, M. S. Kavitha, R. Radhika, C. Kotteeswaran |
Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 35(6), pp. 1, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
28 | Jeyakumar Ponraj, R. Jeyabharath, P. Veena, Tharumar Srihari |
High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 93, pp. 102055, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
28 | B. Jeevan, K. Bikshalu, E. Hari Krishna, Kosaraju Sivani |
Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 99, pp. 104846, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
28 | Poh Yuin Lyn, Nor Azlin Ghazali, Mohamed Fauzi Packeer Mohamed, Muhammad Firdaus Akbar |
Design of Low-Power and Area-Efficient Square Root Carry Select Adder Using Binary to Excess-1 Converter (BEC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
RoViSP ![In: Proceedings of the 12th International Conference on Robotics, Vision, Signal Processing and Power Applications, RoViSP 2023, Penang, Malaysia, 28-29 August 2023., pp. 141-147, 2023, Springer, 978-981-99-9004-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
28 | Raju Ganna, Shanky Saxena, Govind Singh Patel |
Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(17), pp. 2250292:1-2250292:23, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
28 | Maytham Allahi Rudposhti, Mojtaba Valinataj |
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 79, pp. 61-72, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
28 | R. Jothin, P. Sreelatha, Ahilan Appathurai, M. Peer Mohamed |
High-Performance Carry Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(8), pp. 4169-4185, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
28 | S. Rooban, Prasanna D. Lakshmi, Teja K. B. S. Durga, Kumar P. V. Mani |
Carry Select Adder Design with Testability using Reversible Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Perform. Eng. ![In: Int. J. Perform. Eng. 17(6), pp. 536, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
28 | Bala Sindhuri Kandula, Padma Vasavi Kalluru, Santi Prabha Inty |
Design of area efficient VLSI architecture for carry select adder using logic optimization technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Intell. ![In: Comput. Intell. 37(3), pp. 1155-1165, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
28 | Nikhil Advaith Gudala, Trond Ytterdal, John J. Lee 0001, Maher E. Rizkalla |
Implementation of High Speed and Low Power Carry Select Adder with BEC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 64th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021, Lansing, MI, USA, August 9-11, 2021, pp. 377-381, 2021, IEEE, 978-1-6654-2461-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
28 | Akhilesh G. Naik, Debarshi Deka, Dipankar Pal |
ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 11th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2020, San Jose, Costa Rica, February 25-28, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-3427-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
28 | R. Arun Sekar, S. Sasipriya |
Implementation of FIR filter using reversible modified carry select adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 31(14), 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
28 | Nobutaka Kito, Naofumi Takagi |
Concurrent Error Detectable Carry Select Adder with Easy Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 68(7), pp. 1105-1110, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
28 | K. B. Bavithra, R. Siva Kumar |
High throughput K best MIMO detector using modified final selector based carry select adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 71, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
28 | Mojtaba Valinataj, Abbas Mohammadnezhad, Jari Nurmi |
A low-cost high-speed self-checking carry select adder with multiple-fault detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 81, pp. 16-27, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
28 | Xiao-Ping Cui, Weiqiang Liu 0001, Shumin Wang, Earl E. Swartzlander Jr., Fabrizio Lombardi |
Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 90(3), pp. 409-419, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
28 | Chetan Kamble, Siddharth R. K., Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar |
Design of Area-Power-Delay Efficient Square Root Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018, pp. 80-85, 2018, IEEE, 978-1-5386-9172-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
28 | E. John Alex, M. Vijayaraj |
Energy Efficient BEC Modified Carry Select Adder based PTMAC Architecture for Biomedical Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intell. Autom. Soft Comput. ![In: Intell. Autom. Soft Comput. 23(2), pp. 383-388, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram |
An energy and area efficient yet high-speed square-root carry select adder structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 58, pp. 101-112, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Raghava Katreepalli, Themistoklis Haniotakis |
High Speed Power Efficient Carry Select Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pp. 32-37, 2017, IEEE Computer Society, 978-1-5090-6762-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | G. R. Gokhale, P. D. Bahirgonde |
Design of Vedic-multiplier using area-efficient Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015, Kochi, India, August 10-13, 2015, pp. 576-581, 2015, IEEE, 978-1-4799-8790-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
28 | Sanjay Singh, Srinivasa Rao Karumuri |
Implementation of 4-bit carry select adder using Diode free adiabatic logic (DFAL). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReTIS ![In: 2nd IEEE International Conference on Recent Trends in Information Systems, ReTIS 2015, Kolkata, India, July 9-11, 2015, pp. 481-484, 2015, IEEE, 978-1-4799-8349-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
28 | Venkatachalam Nithish Kumar, Pani Prithvi Raj, Gopalakrishnan Lakshminarayanan, Mathini Sellathurai |
Low Power and Area Efficient Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 10(4), pp. 593-601, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
28 | Muhammad Ali Akbar, Jeong-A Lee |
Comments on "Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7), pp. 2212-2214, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
28 | Basant Kumar Mohanty, Sujit Kumar Patel |
Area-Delay-Power Efficient Carry-Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 61-II(6), pp. 418-422, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
28 | A. Ramakrishna Reddy, M. Parvathi |
Efficient carry select adder using 0.12µm technology for low power applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: International Conference on Advances in Computing, Communications and Informatics, ICACCI 2013, Mysore, India, August 22-25, 2013, pp. 550-553, 2013, IEEE, 978-1-4799-2432-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
28 | Muhammad Ali Akbar, Jeong-A Lee |
Self-Checking Carry Select Adder with Fault Localization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013, pp. 863-869, 2013, IEEE Computer Society, 978-1-4799-2978-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
28 | Amit Grover, Neeti Grover |
Comparative Analysis: Area-Efficient Carry Select Adders 180 Nm Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: Proceedings of the Asia Modelling Symposium 2013, Seventh Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2013, 23 July, 2013, Hong Kong, China / 25 July, 2013, Kuala Lumpur, Malaysia, pp. 99-102, 2013, IEEE, 978-0-7695-5101-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
28 | B. Ramkumar, Harish M. Kittur |
Low-Power and Area-Efficient Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(2), pp. 371-375, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | Nobutaka Kito, Shinichi Fujii, Naofumi Takagi |
A C-Testable Multiple-Block Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 95-D(4), pp. 1084-1092, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | Kai Du, Peter J. Varman, Kartik Mohanram |
High performance reliable variable latency carry select addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, pp. 1257-1262, 2012, IEEE, 978-1-4577-2145-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Optimized design of parallel carry-select adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 44(1), pp. 62-74, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Feng Liu 0029, Xiaoyu Song, Qingping Tan, Gang Chen 0004 |
Formal Analysis of Hybrid Prefix/Carry-Select Arithmetic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. J. ![In: Comput. J. 54(6), pp. 894-904, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Huan Minh Vo, Chul-Moon Jung, Eun-Sub Lee, Kyeong-Sik Min |
Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 8(16), pp. 1322-1329, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Feng Liu 0029, QingPing Tan, Xiaoyu Song, Gang Chen 0004 |
Formal Proof for a General Architecture of Hybrid Prefix/Carry-Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP (1) ![In: Algorithms and Architectures for Parallel Processing, 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings. Part I, pp. 193-204, 2010, Springer, 978-3-642-13118-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Yan Sun, Xin Zhang, Xi Jin |
Low-power carry select adder using fast all-one finding logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoSE ![In: 3rd IEEE International Conference on System of Systems Engineering, SoSE 2008, Singapore, 2-4 June 2008, pp. 1-5, 2008, IEEE, 978-1-4244-2172-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson |
Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(12), pp. 2696-2705, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Amaury Nève, Helmut Schettler, Thomas Ludwig 0004, Denis Flandre |
Power-delay product minimization in high-performance 64-bit carry-select adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(3), pp. 235-244, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
A gate-level strategy to design Carry Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 465-468, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
28 | Woopyo Jeong, Kaushik Roy 0001 |
Robust high-performance low-power carry select adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 503-506, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | M.-J. Liao, C.-F. Su, Alex C.-Y. Chang, Allen C.-H. Wu |
A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 81-84, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Amaury Nève, Denis Flandre |
Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France, pp. 169-180, 2001, Kluwer, 1-4020-7148-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
28 | M. Shamanna, Sterling R. Whitaker |
A Carry Select Adder with Conflict Free Bypass Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 363-366, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
28 | Akhilesh Tyagi |
A reduced area scheme for carry-select adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1990, Cambridge, MA, USA, 17-19 September, 1990, pp. 255-258, 1990, IEEE Computer Society, 0-8186-2079-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
28 | Orest J. Bedrij |
Carry-Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRE Trans. Electron. Comput. ![In: IRE Trans. Electron. Comput. 11(3), pp. 340-346, 1962. The full citation details ...](Pics/full.jpeg) |
1962 |
DBLP DOI BibTeX RDF |
|
22 | Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo |
Fast Low-Power 64-Bit Modular Hybrid Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 609-617, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Rumi Zhang, Wei Wang 0003, Konrad Walus, Graham A. Jullien |
Performance comparison of quantum-dot cellular automata adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2522-2526, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Yajuan He, Chip-Hong Chang |
A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Roger Endrigo Carvalho Porto, Luciano Volcan Agostini |
Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 224-229, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Oscal T.-C. Chen, Robin R.-B. Sheen, S. Wang |
A low-power adder operating on effective dynamic data ranges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(4), pp. 435-453, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Mircea R. Stan |
Synchronous Up/Down Counter with Clock Period Independent of Counter Size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 274-281, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
up/down counters, constant time counters, prescalers |
16 | Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis |
Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 127-134, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Sheng Sun, Carl Sechen |
Post-layout comparison of high performance 64b static adders in energy-delay space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 401-408, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Peter Celinski, Sorin Cotofana, Derek Abbott |
A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN (2) ![In: Artificial Neural Nets Problem Solving Methods, 7th International Work-Conference on Artificial and Natural Neural Networks, IWANN2003, Maó, Menorca, Spain, June 3-6, 2003 Proceedings, Part II, pp. 73-80, 2003, Springer, 3-540-40211-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Hoang Q. Dao, Vojin G. Oklobdzija |
Performance Comparison of VLSI Adders Using Logical Effort. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 25-34, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Mauro Olivieri |
Design of synchronous and asynchronous variable-latency pipelined multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 365-376, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
13 | Sheng Sun, Larry McMurchie, Carl Sechen |
A High-Performance 64-bit Adder Implemented in Output Prediction Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA, pp. 213-223, 2001, IEEE Computer Society, 0-7695-1037-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
13 | Shanzhen Xing, William W. H. Yu |
FPGA Adders: Performance Evaluation and Optimal Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 15(1), pp. 24-29, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
13 | Uming Ko, T. Balsara, Wai Lee |
Low-power design techniques for high-performance CMOS adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(2), pp. 327-333, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
8 | Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi |
An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 116-119, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Fatemeh Kashfi, Sied Mehdi Fakhraie, Saeed Safari |
A 65nm 10GHz pipelined MAC structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 460-463, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima |
ROM based logic (RBL) design: High-performance and low-power adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 796-799, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|