Search results for "carry-select"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
101	Yan Sun, Xin Zhang, Xi Jin	High-Performance Carry Select Adder Using Fast All-One Finding Logic.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	fast all-one finding circuit, add-one circuit, carry-select adder
99	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders.	ISQED	2005	DBLP DOI BibTeX RDF
97	Akhilesh Tyagi	A Reduced-Area Scheme for Carry-Select Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders
95	Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld	Modulo p=3 Checking for a Carry Select Adder.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	concurrent checking, modulo checking, carry select adder
92	Vitit Kantabutra	A Recursive Carry-Lookahead/Carry-Select Hybrid Adder.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	recursive carry-lookahead/carry-select hybrid adder, double-precision mantissas, spanning tree carry lookahead adder, redundant cell adder, Am29050 microprocessor, Manchester carry chains, delays, adders
82	Keshab K. Parhi	Low-energy CSMT carry generators and binary adders.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
79	Youngjoon Kim, Lee-Sup Kim	A low power carry select adder with reduced area.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
73	Vitalij Ocheretnij, Daniel Marienfeld, Egor S. Sogomonyan, Michael Gössel	Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits.	IOLTS	2004	DBLP DOI BibTeX RDF
70	Yiran Chen 0001, Hai Li 0001, Kaushik Roy 0001, Cheng-Kok Koh	Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.	ISLPED	2005	DBLP DOI BibTeX RDF	low-power, carry-select adder
70	Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy 0001	Low-power carry-select adder using adaptive supply voltage based on input vector patterns.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive supply voltage, low power adder, carry-select adder
61	Jin-Fu Li 0001, Jiunn-Der Yu, Yu-Jen Huang	A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
61	Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld	A Modulo p Checked Self-Checking Carry Select Adder.	IOLTS	2003	DBLP DOI BibTeX RDF
57	Egor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel	A New Self-Checking Sum-Bit Duplicated Carry-Select Adder.	DATE	2004	DBLP DOI BibTeX RDF
56	Morteza Dorrigiv, Ghassem Jaberipur	Low area/power decimal addition with carry-select correction and carry-select sum-digits.	Integr.	2014	DBLP DOI BibTeX RDF
54	Yajuan He, Chip-Hong Chang, Jiangmin Gu	An area efficient 64-bit square root carry-select adder for low power applications.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
52	Dilip P. Vasudevan, Parag K. Lala	A Technique for Modular Design of Self-Checking Carry-Select Adder.	DFT	2005	DBLP DOI BibTeX RDF
49	Youngjoon Kim, Ki-Hyuk Sung, Lee-Sup Kim	A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
45	Scott Hauck, Matthew M. Hosler, Thomas W. Fry	High-performance carry chains for FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
45	Scott Hauck, Matthew M. Hosler, Thomas W. Fry	High-Performance Carry Chains for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
43		Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter.	J. Ambient Intell. Humaniz. Comput.	2021	DBLP DOI BibTeX RDF
43	Mehedi Hasan, Muhammad Saddam Hossain, Abdul Hasib Siddique, Mainul Hossain, Hasan U. Zaman, Sharnali Islam	A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
43	Minho Nam, Yeonhun Choi, Kyoung-Rok Cho	High-speed and energy efficient carry select adder (CSLA) dominated by carry generation logic.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
43	Habib Ghasemizadeh Tamar, Akbar Ghasemizadeh Tamar, Khayrollah Hadidi, Abdollah Khoei, Pourya Hoseini	High speed area reduced 64-bit static hybrid carry-lookahead/carry-select adder.	ICECS	2011	DBLP DOI BibTeX RDF
43	Yajuan He, Chip-Hong Chang	A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
43	Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy 0001	Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
43	Gustavo A. Ruiz, Mercedes Granda	An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit.	Microelectron. J.	2004	DBLP DOI BibTeX RDF
43	Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka	A fast hybrid carry-lookahead/carry-select adder design.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF	CMOS, domino logic, carry lookahead adder
42	Jongsun Park 0001, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy 0001	High performance and low power FIR filter design based on sharing multiplication.	ISLPED	2002	DBLP DOI BibTeX RDF	FIR filter design, computation sharing, conditional capture flip-flop, high performance and low power carry select adder
42	Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto	A 13.3ns double-precision floating-point ALU and multiplier.	ICCD	1995	DBLP DOI BibTeX RDF	double-precision floating-point ALU, floating-point multiplier, carry select addition, prerounding techniques, noise tolerant precharge circuit, two-cycle latency, 13.3 ns, 0.3 micron, 2.5 V, 150 MHz, normalization, floating point arithmetic, CMOS integrated circuits, multiplying circuits, CMOS technology, arithmetic logic unit
38	Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait	Area-time optimal adder with relative placement generator.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
36	Alireza Namazi, Seyed Ghassem Miremadi, Alireza Ejlali	A High Speed and Low Cost Error Correction Technique for the Carry Select Adder.	ARES	2009	DBLP DOI BibTeX RDF
36	B. Kiran Kumar, Parag K. Lala	On-line Detection of Faults in Carry-Select Adders.	ITC	2003	DBLP DOI BibTeX RDF
36	Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig 0004, Gerhard Hellner	Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	SOI technology, logic design styles, circuit Design
36	Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris	Fast adders in modern FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
36	Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis	A Low-Power Carry Skip Adder with Fast Saturation.	ASAP	2004	DBLP DOI BibTeX RDF
34	Hong Diep Nguyen, Bogdan Pasca 0001, Thomas B. Preußer	FPGA-Specific Arithmetic Optimizations of Short-Latency Adders.	FPL	2011	DBLP DOI BibTeX RDF	carry-chain, carry-select, carry-increment, FPGA, addition
31	Johannes Grad, James E. Stine	Low power binary addition using carry increment adders.	ISCAS	2006	DBLP DOI BibTeX RDF
31	Andrew Beaumont-Smith, Cheng-Chew Lim	Parallel Prefix Adder Design.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
28	Perumal Mahendran, M. S. Kavitha, R. Radhika, C. Kotteeswaran	Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application.	Concurr. Comput. Pract. Exp.	2023	DBLP DOI BibTeX RDF
28	Jeyakumar Ponraj, R. Jeyabharath, P. Veena, Tharumar Srihari	High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system.	Integr.	2023	DBLP DOI BibTeX RDF
28	B. Jeevan, K. Bikshalu, E. Hari Krishna, Kosaraju Sivani	Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
28	Poh Yuin Lyn, Nor Azlin Ghazali, Mohamed Fauzi Packeer Mohamed, Muhammad Firdaus Akbar	Design of Low-Power and Area-Efficient Square Root Carry Select Adder Using Binary to Excess-1 Converter (BEC).	RoViSP	2023	DBLP DOI BibTeX RDF
28	Raju Ganna, Shanky Saxena, Govind Singh Patel	Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
28	Maytham Allahi Rudposhti, Mojtaba Valinataj	High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic.	Integr.	2021	DBLP DOI BibTeX RDF
28	R. Jothin, P. Sreelatha, Ahilan Appathurai, M. Peer Mohamed	High-Performance Carry Select Adders.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
28	S. Rooban, Prasanna D. Lakshmi, Teja K. B. S. Durga, Kumar P. V. Mani	Carry Select Adder Design with Testability using Reversible Gates.	Int. J. Perform. Eng.	2021	DBLP DOI BibTeX RDF
28	Bala Sindhuri Kandula, Padma Vasavi Kalluru, Santi Prabha Inty	Design of area efficient VLSI architecture for carry select adder using logic optimization technique.	Comput. Intell.	2021	DBLP DOI BibTeX RDF
28	Nikhil Advaith Gudala, Trond Ytterdal, John J. Lee 0001, Maher E. Rizkalla	Implementation of High Speed and Low Power Carry Select Adder with BEC.	MWSCAS	2021	DBLP DOI BibTeX RDF
28	Akhilesh G. Naik, Debarshi Deka, Dipankar Pal	ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder.	LASCAS	2020	DBLP DOI BibTeX RDF
28	R. Arun Sekar, S. Sasipriya	Implementation of FIR filter using reversible modified carry select adder.	Concurr. Comput. Pract. Exp.	2019	DBLP DOI BibTeX RDF
28	Nobutaka Kito, Naofumi Takagi	Concurrent Error Detectable Carry Select Adder with Easy Testability.	IEEE Trans. Computers	2019	DBLP DOI BibTeX RDF
28	K. B. Bavithra, R. Siva Kumar	High throughput K best MIMO detector using modified final selector based carry select adder.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
28	Mojtaba Valinataj, Abbas Mohammadnezhad, Jari Nurmi	A low-cost high-speed self-checking carry select adder with multiple-fault detection.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
28	Xiao-Ping Cui, Weiqiang Liu 0001, Shumin Wang, Earl E. Swartzlander Jr., Fabrizio Lombardi	Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders.	J. Signal Process. Syst.	2018	DBLP DOI BibTeX RDF
28	Chetan Kamble, Siddharth R. K., Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar	Design of Area-Power-Delay Efficient Square Root Carry Select Adder.	iSES	2018	DBLP DOI BibTeX RDF
28	E. John Alex, M. Vijayaraj	Energy Efficient BEC Modified Carry Select Adder based PTMAC Architecture for Biomedical Processors.	Intell. Autom. Soft Comput.	2017	DBLP DOI BibTeX RDF
28	Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram	An energy and area efficient yet high-speed square-root carry select adder structure.	Comput. Electr. Eng.	2017	DBLP DOI BibTeX RDF
28	Raghava Katreepalli, Themistoklis Haniotakis	High Speed Power Efficient Carry Select Adder Design.	ISVLSI	2017	DBLP DOI BibTeX RDF
28	G. R. Gokhale, P. D. Bahirgonde	Design of Vedic-multiplier using area-efficient Carry Select Adder.	ICACCI	2015	DBLP DOI BibTeX RDF
28	Sanjay Singh, Srinivasa Rao Karumuri	Implementation of 4-bit carry select adder using Diode free adiabatic logic (DFAL).	ReTIS	2015	DBLP DOI BibTeX RDF
28	Venkatachalam Nithish Kumar, Pani Prithvi Raj, Gopalakrishnan Lakshminarayanan, Mathini Sellathurai	Low Power and Area Efficient Carry Select Adder.	J. Low Power Electron.	2014	DBLP DOI BibTeX RDF
28	Muhammad Ali Akbar, Jeong-A Lee	Comments on "Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding".	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
28	Basant Kumar Mohanty, Sujit Kumar Patel	Area-Delay-Power Efficient Carry-Select Adder.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
28	A. Ramakrishna Reddy, M. Parvathi	Efficient carry select adder using 0.12µm technology for low power applications.	ICACCI	2013	DBLP DOI BibTeX RDF
28	Muhammad Ali Akbar, Jeong-A Lee	Self-Checking Carry Select Adder with Fault Localization.	DSD	2013	DBLP DOI BibTeX RDF
28	Amit Grover, Neeti Grover	Comparative Analysis: Area-Efficient Carry Select Adders 180 Nm Technology.	Asia International Conference on Modelling and Simulation	2013	DBLP DOI BibTeX RDF
28	B. Ramkumar, Harish M. Kittur	Low-Power and Area-Efficient Carry Select Adder.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
28	Nobutaka Kito, Shinichi Fujii, Naofumi Takagi	A C-Testable Multiple-Block Carry Select Adder.	IEICE Trans. Inf. Syst.	2012	DBLP DOI BibTeX RDF
28	Kai Du, Peter J. Varman, Kartik Mohanram	High performance reliable variable latency carry select addition.	DATE	2012	DBLP DOI BibTeX RDF
28	Massimo Alioto, Gaetano Palumbo, Massimo Poli	Optimized design of parallel carry-select adders.	Integr.	2011	DBLP DOI BibTeX RDF
28	Feng Liu 0029, Xiaoyu Song, Qingping Tan, Gang Chen 0004	Formal Analysis of Hybrid Prefix/Carry-Select Arithmetic Systems.	Comput. J.	2011	DBLP DOI BibTeX RDF
28	Huan Minh Vo, Chul-Moon Jung, Eun-Sub Lee, Kyeong-Sik Min	Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs.	IEICE Electron. Express	2011	DBLP DOI BibTeX RDF
28	Feng Liu 0029, QingPing Tan, Xiaoyu Song, Gang Chen 0004	Formal Proof for a General Architecture of Hybrid Prefix/Carry-Select Adders.	ICA3PP (1)	2010	DBLP DOI BibTeX RDF
28	Yan Sun, Xin Zhang, Xi Jin	Low-power carry select adder using fast all-one finding logic.	SoSE	2008	DBLP DOI BibTeX RDF
28	Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson	Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding.	IEEE Trans. Circuits Syst. I Regul. Pap.	2007	DBLP DOI BibTeX RDF
28	Amaury Nève, Helmut Schettler, Thomas Ludwig 0004, Denis Flandre	Power-delay product minimization in high-performance 64-bit carry-select adders.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
28	Massimo Alioto, Gaetano Palumbo, Massimo Poli	A gate-level strategy to design Carry Select Adders.	ISCAS (2)	2004	DBLP BibTeX RDF
28	Woopyo Jeong, Kaushik Roy 0001	Robust high-performance low-power carry select adder.	ASP-DAC	2003	DBLP DOI BibTeX RDF
28	M.-J. Liao, C.-F. Su, Alex C.-Y. Chang, Allen C.-H. Wu	A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
28	Amaury Nève, Denis Flandre	Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies.	VLSI-SOC	2001	DBLP BibTeX RDF
28	M. Shamanna, Sterling R. Whitaker	A Carry Select Adder with Conflict Free Bypass Circuit.	VLSI Design	1993	DBLP DOI BibTeX RDF
28	Akhilesh Tyagi	A reduced area scheme for carry-select adders.	ICCD	1990	DBLP DOI BibTeX RDF
28	Orest J. Bedrij	Carry-Select Adder.	IRE Trans. Electron. Comput.	1962	DBLP DOI BibTeX RDF
22	Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo	Fast Low-Power 64-Bit Modular Hybrid Adder.	PATMOS	2005	DBLP DOI BibTeX RDF
22	Rumi Zhang, Wei Wang 0003, Konrad Walus, Graham A. Jullien	Performance comparison of quantum-dot cellular automata adders.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
17	Yajuan He, Chip-Hong Chang	A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Roger Endrigo Carvalho Porto, Luciano Volcan Agostini	Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation.	DATE	2004	DBLP DOI BibTeX RDF
17	Oscal T.-C. Chen, Robin R.-B. Sheen, S. Wang	A low-power adder operating on effective dynamic data ranges.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
17	Mircea R. Stan	Synchronous Up/Down Counter with Clock Period Independent of Counter Size.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	up/down counters, constant time counters, prescalers
16	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis	Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.	ISVLSI	2004	DBLP DOI BibTeX RDF
13	Sheng Sun, Carl Sechen	Post-layout comparison of high performance 64b static adders in energy-delay space.	ICCD	2007	DBLP DOI BibTeX RDF
13	Peter Celinski, Sorin Cotofana, Derek Abbott	A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder.	IWANN (2)	2003	DBLP DOI BibTeX RDF
13	Hoang Q. Dao, Vojin G. Oklobdzija	Performance Comparison of VLSI Adders Using Logical Effort.	PATMOS	2002	DBLP DOI BibTeX RDF
13	Mauro Olivieri	Design of synchronous and asynchronous variable-latency pipelined multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
13	Sheng Sun, Larry McMurchie, Carl Sechen	A High-Performance 64-bit Adder Implemented in Output Prediction Logic.	ARVLSI	2001	DBLP DOI BibTeX RDF
13	Shanzhen Xing, William W. H. Yu	FPGA Adders: Performance Evaluation and Optimal Design.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
13	Uming Ko, T. Balsara, Wai Lee	Low-power design techniques for high-performance CMOS adders.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
8	Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi	An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition.	ISQED	2009	DBLP DOI BibTeX RDF
8	Fatemeh Kashfi, Sied Mehdi Fakhraie, Saeed Safari	A 65nm 10GHz pipelined MAC structure.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima	ROM based logic (RBL) design: High-performance and low-power adders.	ISCAS	2008	DBLP DOI BibTeX RDF