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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 11758 occurrences of 3468 keywords
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Results
Found 30195 publication records. Showing 30139 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
76 | H. Bernhard Pogge |
The next chip challenge: effective methods for viable mixed technology SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 84-87, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
SoCs (System on a Chip), chip fabrication methods, chip subsector concepts, chip/packing integration |
65 | Guy Even, Ami Litman |
Overcoming chip-to-chip delays and clock skews. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 199-208, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews |
54 | Noel Eisley, Li-Shiuan Peh, Li Shang |
Leveraging on-chip networks for data cache migration in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 197-207, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
network-driven computing, interconnection network, CMP, chip-multiprocessor, migration |
51 | Jaime H. Moreno |
Chip-level integration: the new frontier for microprocessor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30 - August 2, 2006, pp. 328, 2006, ACM, 1-59593-452-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
chip-level integration, microprocessor architecture |
50 | Partha Kundu, Li-Shiuan Peh |
Guest Editors' Introduction: On-Chip Interconnects for Multicores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(5), pp. 3-5, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
embedded systems, system on chip, network on chip, multicore architectures, on-chip interconnection networks |
48 | Shirish Bahirat, Sudeep Pasricha |
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 129-136, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
photonic interconnect, network-on-chip, chip multiprocessor |
47 | Rob Aitken, Krisztián Flautner, John Goodacre |
High-Performance Multiprocessor System on Chip: Trends in Chip Architecture for the Mass Market. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiprocessor System-on-Chip ![In: Multiprocessor System-on-Chip - Hardware Design and Tool Integration., pp. 223-239, 2011, Springer, 978-1-4419-6459-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
47 | Suboh A. Suboh, Mohamed Bakhouya, Tarek A. El-Ghazawi |
Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 205-206, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
System on Chip, Network on Chip, Modeling and simulation, On Chip Interconnects |
46 | Tobias Bjerregaard, Shankar Mahadevan |
A survey of research and practices of Network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 38(1), pp. 1, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions |
45 | Luciano Lavagno, Sujit Dey, Rajesh K. Gupta 0001 |
Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 21-23, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
45 | T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael |
Faulty chip identification in a multi chip module system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 254-259, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
faulty chip identification, multi chip module, linear space compressor, field programmable gate array, fault diagnosis, data compression, data compression, built-in self test, built-in self test, integrated circuit testing, fault detection, comparator, multichip modules |
45 | Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese |
Impact of Chip-Level Integration on Performance of OLTP Workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 3-14, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
chip-level integration, database workloads, multiprocessors, memory system performance |
44 | Roman L. Lysecky, Frank Vahid |
On-chip logic minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 334-337, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
on-chip logic minimization, on-chip synthesis, embedded systems, dynamic optimization, system-on-a-chip, logic minimization |
43 | Michael Ferdman, Babak Falsafi |
Last-Touch Correlated Data Streaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 105-115, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
predictor lookahead, last-touch correlated data streaming, address-correlating predictor, cache block address identification, correlation data storage, program active memory footprint, prediction lookahead, off-chip correlation data lookup, scalable on-chip table, low-latency lookup, on-chip storage, last-touch predictor, prefetch, superscalar processor, cycle-accurate simulation |
42 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan |
Compiler directed network-on-chip reliability enhancement for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems, LCTES 2010, Stockholm, Sweden, April 13-15, 2010, pp. 85-94, 2010, ACM, 978-1-60558-953-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
reliability, compiler, noc, chip multiprocessors |
42 | Daniel Wiklund, Dake Liu |
Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 252-256, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
basestation, scheduling, Network on chip, 3G, WCDMA |
42 | Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin |
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 811-816, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power distribution grids, power noise, decoupling capacitors, power distribution systems |
42 | Hyung Gyu Lee, Naehyuck Chang, Ümit Y. Ogras, Radu Marculescu |
On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(3), pp. 23:1-23:20, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MPEG-2 encoder, system-on-chip, Networks-on-chip, FPGA prototype, point-to-point |
42 | John Kim |
Low-cost router microarchitecture for on-chip networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 255-266, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
router microarchitecture, complexity, on-chip network |
42 | Louis Scheffer |
An overview of on-chip interconnect variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 27-28, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
causes of variability, on-chip variation, design rules |
42 | Mohamed Shalan, Vincent John Mooney III |
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002, pp. 79-84, 2002, ACM, 1-58113-542-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Atalanta, SoCDMMU, real-time operating systems., two-level memory management, real-time systems, embedded systems, System-on-a-Chip, dynamic memory management |
41 | Andreas Hansson 0001, Kees Goossens |
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 99-108, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
system on chip, network on chip, programming model, protocol stack |
41 | Ricardo Reis 0001 |
Design Tools and Methods for Chip Physical Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiprocessor System-on-Chip ![In: Multiprocessor System-on-Chip - Hardware Design and Tool Integration., pp. 155-166, 2011, Springer, 978-1-4419-6459-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Lionel Torres, Pascal Benoit, Gilles Sassatelli, Michel Robert, Fabien Clermidy, Diego Puschini |
An Introduction to Multi-Core System on Chip - Trends and Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiprocessor System-on-Chip ![In: Multiprocessor System-on-Chip - Hardware Design and Tool Integration., pp. 1-21, 2011, Springer, 978-1-4419-6459-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Diana Göhringer, Michael Hübner 0001, Jürgen Becker 0001 |
Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiprocessor System-on-Chip ![In: Multiprocessor System-on-Chip - Hardware Design and Tool Integration., pp. 127-151, 2011, Springer, 978-1-4419-6459-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano |
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low Power Networks-on-Chip ![In: Low Power Networks-on-Chip., pp. 21-43, 2011, Springer, 978-1-4419-6910-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Sai-Wang Tam, Eran Socher, Mau-Chung Frank Chang, Jason Cong, Glenn D. Reinman |
RF-Interconnect for Future Network-On-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low Power Networks-on-Chip ![In: Low Power Networks-on-Chip., pp. 255-280, 2011, Springer, 978-1-4419-6910-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Yuho Jin, Ki Hwan Yum, Eun Jung Kim 0001 |
Adaptive Data Compression for Low-Power On-Chip Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low Power Networks-on-Chip ![In: Low Power Networks-on-Chip., pp. 151-174, 2011, Springer, 978-1-4419-6910-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania |
Application-Specific Routing Algorithms for Low Power Network on Chip Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low Power Networks-on-Chip ![In: Low Power Networks-on-Chip., pp. 113-150, 2011, Springer, 978-1-4419-6910-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Mark A. Anders 0001, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar Y. Borkar |
Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low Power Networks-on-Chip ![In: Low Power Networks-on-Chip., pp. 3-20, 2011, Springer, 978-1-4419-6910-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Miltos D. Grammatikakis, Marcello Coppola, Fabrizio Sensini |
Software for Multiprocessor Networks on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 281-303, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Shashi Kumar |
On Packet Switched Networks for On-Chip Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 85-106, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Axel Jantsch, Hannu Tenhunen |
Will Networks on Chip Close the Productivity Gap? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 3-18, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Kees Goossens, John Dielissen, Jef L. van Meerbergen, Peter Poplavko, Andrei Radulescu, Edwin Rijpkema, Erwin Waterlander, Paul Wielage |
Guaranteeing the Quality of Services in Networks on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 61-82, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Raimund Ubar, Jaan Raik |
Testing Strategies for Networks on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 131-152, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Ilkka Saastamoinen, David A. Sigüenza-Tortosa, Jari Nurmi |
An IP-Based On-Chip Packet-Switched Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 193-213, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Johnny Öberg |
Clocking Strategies for Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 153-172, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos |
A buffered crossbar-based chip interconnection framework supporting quality of service. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 90-95, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
chip interconnect, quality of service, system on chip, network on chip, multi-processor, buffered crossbar |
41 | Roman L. Lysecky, Frank Vahid |
A codesigned on-chip logic minimizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 109-113, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
embedded CAD, on-chip logic minimization, on-chip synthesis, embedded systems, dynamic optimization, system-on-a-chip, hardware/software codesign, logic minimization |
41 | Mario Kovac, N. Ranganathan |
JAGUAR: a high speed VLSI chip for JPEG image compression standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 220-224, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
JAGUAR, high speed VLSI chip, JPEG image compression standard, pipelined single chip VLSI architecture, entropy encoder, clock rate, input rate, CMOS VLSI chip, Huffman entropy coding, 1024 pixel, 1048576 pixel, VLSI, parallel architectures, data compression, image coding, discrete cosine transforms, discrete cosine transform, pipeline processing, color images, image colour analysis, digital signal processing chips, Huffman codes, high throughput, CMOS digital integrated circuits, entropy codes, 100 MHz |
41 | Chen Wang 0001, Jianhua Xuan, Li Chen 0018, Po Zhao, Yue Joseph Wang, Robert Clarke, Eric P. Hoffman |
Integrative Network Component Analysis for Regulatory Network Reconstruction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISBRA ![In: Bioinformatics Research and Applications, Fourth International Symposium, ISBRA 2008, Atlanta, GA, USA, May 6-9, 2008. Proceedings, pp. 196-207, 2008, Springer, 978-3-540-79449-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Network component analysis, ChIP-on-chip, muscle regeneration, gene regulatory networks, microarray data analysis |
39 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(3), pp. 682-704, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
system design, data cache, data partitioning, system synthesis, scratch-pad memory, on-chip memory, memory synthesis |
39 | Li Shang, Li-Shiuan Peh, Amit Kumar 0002, Niraj K. Jha |
Thermal Modeling, Characterization and Management of On-Chip Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 67-78, 2004, IEEE Computer Society, 0-7695-2126-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Björn Osterloh, Harald Michalik, Björn Fiethe |
SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings, pp. 50-59, 2009, Springer, 978-3-642-00453-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SoCWire, dynamic reconfigurable system, Sytem-on-Chip, Network-on-Chip, SRAM-based FPGA, VMC |
39 | Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar |
A design methodology for application-specific networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(2), pp. 263-280, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
regular topology, architecture, methodology, networks-on-chip, Application-specific |
39 | Sung-Hsien Sun, Shie-Jue Lee |
A JPEG Chip for Image Compression and Decompression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 35(1), pp. 43-60, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
image compression/decompression, standard cell design, FPGA, VHDL, CAD tools, VLSI chip |
39 | Xiaohong Jiang 0001, Susumu Horiguchi, Yue Hao |
Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 30-, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Antonio Flores, Juan L. Aragón, Manuel E. Acacio |
An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 45(3), pp. 341-364, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Power dissipation model, Microarchitectural level simulator, Heterogeneus on-chip interconnection network, Chip-multiprocessor, Parallel scientific applications |
38 | Hyunmin Kim, Katherina J. Kechris, Lawrence Hunter |
Mining Discriminative Distance Context of Transcription Factor Binding Sites on ChIP Enriched Regions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISBRA ![In: Bioinformatics Research and Applications, Third International Symposium, ISBRA 2007, Atlanta, GA, USA, May 7-10, 2007, Proceedings, pp. 338-349, 2007, Springer, 978-3-540-72030-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ChIP-chip data analysis, ensemble learning, transcription factor |
38 | Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter |
Combined DRAM and logic chip for massively parallel systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 4-16, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits |
38 | Thomas William Ainsworth, Timothy Mark Pinkston |
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 18-29, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Element Interconnect Bus, heterogeneous multicore, network characterization, interconnection networks, network-on-chip, Cell Broadband Engine, on-chip network, performance bottleneck |
37 | Xudong Shi 0003, Feiqi Su, Jih-Kwon Peir, Ye Xia 0001, Zhen Yang |
Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 126-135, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiple cache organization, single-pass simulation, on-chip storage space, on-chip cache capacity, single-pass stack simulation, global stack, shared stack, per-core private stack, single simulation pass, average memory access time, chip-multiprocessor, data replication, data accessibility, abstract model, reuse distances |
37 | Federico Rota, Shantanu Dutt, Sahithi Krishna |
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 507-515, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Woo Hyung Lee, Sanjay Pant, David T. Blaauw |
Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 131-136, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy |
System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 225-230, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
voltage/frequency scaling, embedded systems, design space, power-performance trade-offs |
36 | Yuan Cao 0003, Wanyi Liu, Yue Zheng, Shuai Chen, Jing Ye 0001, Lei Qian, Chip-Hong Chang |
A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(12), pp. 4900-4913, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
36 | Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest |
Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(2), pp. 139-153, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC) |
36 | Marcelo Daniel Berejuck, César Albenes Zeferino |
Adding mechanisms for QoS to a network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, systems-on-chip, networks-on-chip |
36 | Donald J. Dent |
Project Management for System-on-Chip Using Multi-Chip Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 283-290, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Multi-Chip Modules, System-on Chip, Project Management |
36 | Charles M. Higgins, Christof Koch |
Multi-Chip Neuromorphic Motion Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 309-325, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
vision chip, AER, motion, disparity, neuromorphic |
35 | Suboh A. Suboh, Mohamed Bakhouya, Jaafar Gaber, Tarek A. El-Ghazawi |
An interconnection architecture for network-on-chip systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Telecommun. Syst. ![In: Telecommun. Syst. 37(1-3), pp. 137-144, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Switching and routing, Network on chip, Network analysis, Modeling and simulation, On-chip interconnects |
35 | Xinping Zhu, Sharad Malik |
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 6:1-6:24, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
on-chip communication architecture, network-on-chip, multiprocessor system, object-oriented modeling, packet-switching network, design exploration, bus, Retargetable simulation |
35 | Baojun Qiao, Feng Shi 0009, Weixing Ji |
THIN: A New Hierarchical Interconnection Network-on-Chip for SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP ![In: Algorithms and Architectures for Parallel Processing, 7th International Conference, ICA3PP 2007, Hangzhou, China, June 11-14, 2007, Proceedings, pp. 446-457, 2007, Springer, 978-3-540-72904-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multicast, System-on-Chip, Network-on-Chip, network topology |
35 | Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli |
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(2), pp. 113-129, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
architecture, Systems-on-chip, mapping, networks on chip, synthesis |
35 | Kanishka Lahiri, Anand Raghunathan |
Power analysis of system-level on-chip communication architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 236-241, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
system-on-chip, network-on-chip, low-power design, power analysis, communication architectures |
35 | John D. Owens, William J. Dally, Ron Ho, Doddaballapur Narasimha-Murthy Jayasimha, Stephen W. Keckler, Li-Shiuan Peh |
Research Challenges for On-Chip Interconnection Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(5), pp. 96-108, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
embedded systems, system on chip, network on chip, multicore architectures, on-chip interconnection networks |
35 | Noel Eisley, Vassos Soteriou, Li-Shiuan Peh |
High-level power analysis for multi-core chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 389-400, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
simulation, chip multiprocessor (CMP), multi-core, power analysis, system-on-a-chip (SoC) |
35 | Abderrahim Doumar, Hideo Ito |
Testing approach within FPGA-based fault tolerant systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 411-416, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase |
34 | Roman Obermaisser, Hubert Kraut, Christian El Salloum |
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Seventh European Dependable Computing Conference, EDCC-7 2008, Kaunas, Lithuania, 7-9 May 2008, pp. 123-134, 2008, IEEE Computer Society, 978-0-7695-3138-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Paul Ampadu, Bo Fu, David Wolpert 0001, Qiaoyan Yu |
Adaptive Voltage Control for Energy-Efficient NoC Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low Power Networks-on-Chip ![In: Low Power Networks-on-Chip., pp. 45-69, 2011, Springer, 978-1-4419-6910-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Stanislavs Golubcovs, Alex Yakovlev |
Asynchronous Communications for NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low Power Networks-on-Chip ![In: Low Power Networks-on-Chip., pp. 71-109, 2011, Springer, 978-1-4419-6910-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli |
Design and Analysis of NoCs for Low-Power 2D and 3D SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low Power Networks-on-Chip ![In: Low Power Networks-on-Chip., pp. 199-222, 2011, Springer, 978-1-4419-6910-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny |
Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low Power Networks-on-Chip ![In: Low Power Networks-on-Chip., pp. 175-195, 2011, Springer, 978-1-4419-6910-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Jung Ho Ahn, Raymond G. Beausoleil, Nathan L. Binkert, Al Davis, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, Matteo Monchiero, Naveen Muralimanohar, Robert Schreiber, Dana Vantrease |
CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low Power Networks-on-Chip ![In: Low Power Networks-on-Chip., pp. 223-254, 2011, Springer, 978-1-4419-6910-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Michael J. Anderson, Bryan Catanzaro, Jike Chong, Ekaterina Gonina, Kurt Keutzer, Chao-Yue Lai, Mark Murphy, Bor-Yiing Su, Narayanan Sundaram |
PALLAS: Mapping Applications onto Manycore. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiprocessor System-on-Chip ![In: Multiprocessor System-on-Chip - Hardware Design and Tool Integration., pp. 89-113, 2011, Springer, 978-1-4419-6459-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Jürgen Teich, Jörg Henkel, Andreas Herkersdorf, Doris Schmitt-Landsiedel, Wolfgang Schröder-Preikschat, Gregor Snelting |
Invasive Computing: An Overview. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiprocessor System-on-Chip ![In: Multiprocessor System-on-Chip - Hardware Design and Tool Integration., pp. 241-268, 2011, Springer, 978-1-4419-6459-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Benny Akesson, Anca Mariana Molnos, Andreas Hansson 0001, Jude Angelo Ambrose, Kees Goossens |
Composability and Predictability for Independent Application Development, Verification, and Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiprocessor System-on-Chip ![In: Multiprocessor System-on-Chip - Hardware Design and Tool Integration., pp. 25-56, 2011, Springer, 978-1-4419-6459-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Dac Pham, Jim Holt, Sanjay Deshpande |
Embedded Multicore Systems: Design Challenges and Opportunities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiprocessor System-on-Chip ![In: Multiprocessor System-on-Chip - Hardware Design and Tool Integration., pp. 197-222, 2011, Springer, 978-1-4419-6459-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Miltos D. Grammatikakis, George Kornaros, Marcello Coppola |
Power-Aware Multicore SoC and NoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiprocessor System-on-Chip ![In: Multiprocessor System-on-Chip - Hardware Design and Tool Integration., pp. 167-193, 2011, Springer, 978-1-4419-6459-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Rakesh Kumar 0002, Timothy G. Mattson, Gilles Pokam, Rob F. Van der Wijngaart |
The Case for Message Passing on Many-Core Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiprocessor System-on-Chip ![In: Multiprocessor System-on-Chip - Hardware Design and Tool Integration., pp. 115-123, 2011, Springer, 978-1-4419-6459-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Andreas Herkersdorf, Andreas Lankes, Michael Meitinger, Rainer Ohlendorf, Stefan Wallentowitz, Thomas Wild, Johannes Zeppenfeld |
Hardware Support for Efficient Resource Utilization in Manycore Processor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiprocessor System-on-Chip ![In: Multiprocessor System-on-Chip - Hardware Design and Tool Integration., pp. 57-87, 2011, Springer, 978-1-4419-6459-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Juha-Pekka Soininen, Hannu Heusala |
A Design Methodology for NOC-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 19-38, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Eric Verhulst |
Beyond the Von Neumann Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 217-238, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Martti Forsell |
A Parallel Computer as a NOC Region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 173-192, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Andrew Mihal, Kurt Keutzer |
Mapping Concurrent Applications onto Architectural Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 39-59, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Davide Bertozzi, Luca Benini, Giovanni De Micheli |
Energy-Reliability trade-Off for NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 107-129, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Sungjoo Yoo, Gabriela Nicolescu, Iuliana Bacivarov, Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya |
Multi-Level Software Validation for NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 261-279, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Zhonghai Lu, Raimo Haukilahti |
NoC Application Programming Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networks on Chip ![In: Networks on Chip, pp. 239-260, 2003, Kluwer / Springer, 978-1-4020-7392-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger |
On-Chip Interconnection Networks of the TRIPS Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(5), pp. 41-50, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
communication, networking, distributed architectures, packet-switching networks, multicore architectures, on-chip interconnection networks |
33 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin |
Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 87-92, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
data compression, chip multiprocessors, optimizing compiler |
33 | Mahmut T. Kandemir, Ozcan Ozturk 0001, Mustafa Karaköy |
Dynamic on-chip memory management for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 14-23, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
chip multiprocessors, optimizing compiler, memory bank |
33 | Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos |
Practical off-chip meta-data for temporal memory streaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 79-90, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Xu Wang, Ge Gan, Joseph B. Manzano, Dongrui Fan, Shuxu Guo |
A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 14th International Conference on Parallel and Distributed Systems, ICPADS 2008, Melbourne, Victoria, Australia, December 8-10, 2008, pp. 689-696, 2008, IEEE Computer Society, 978-0-7695-3434-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo |
Low-power network-on-chip for high-performance SoC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(2), pp. 148-160, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Zhao Zhang 0010, Zhichun Zhu, Xiaodong Zhang 0001 |
Design and Optimization of Large Size and Low Overhead Off-Chip Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(7), pp. 843-855, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Jörg Henkel, Wayne H. Wolf, Srimat T. Chakradhar |
On-chip networks: A scalable, communication-centric embedded system design paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 845-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Andreas G. Andreou |
Programmable Kernel Analog VLSI Convolution Chip for Real Time Vision Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN (4) ![In: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, IJCNN 2000, Neural Computing: New Challenges and Perspectives for the New Millennium, Como, Italy, July 24-27, 2000, Volume 4, pp. 62-65, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Duo Ding, David Z. Pan |
OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 11-18, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
photonic networks-on-chip, low power, computer aided design, high performance |
33 | James M. Baker Jr., Brian T. Gold, Mark Bucciero, Sidney Bennett, Rajneesh Mahajan, Priyadarshini Ramachandran, Jignesh Shah |
SCMP: A Single-Chip Message-Passing Parallel Computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 30(2), pp. 133-149, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
single-chip parallel computers, parallel architecture, high-performance computing, computer architecture, embedded computing |
33 | Sudarshan Banerjee, Nikil D. Dutt |
FIFO power optimization for on-chip networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 187-191, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
wide flits, low power design, shared memory, switches, FIFO, on-chip networks |
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