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PATMOS(927) DAC(547) IEEE Trans. Comput. Aided Des....(462) ICCAD(338) CoRR(336) DATE(336) ASP-DAC(223) IEEE Trans. Commun.(210) IEEE Trans. Very Large Scale I...(198) ISCAS(197) ISQED(179) VLSI Design(142) ISPD(131) RTSS(127) ICCD(126) ACM Great Lakes Symposium on V...(125) More (+10 of total 2487)
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Found 16149 publication records. Showing 16145 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
80Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer A new framework for static timing analysis, incremental timing refinement, and timing simulation. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation
77Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin How accurately can we model timing in a placement engine? Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF differential timing analysis, linear programming, static timing analysis, timing-driven placement
73John V. A. Janeri, Daylan B. Darby, Daniel D. Schnackenberg Building higher resolution synthetic clocks for signaling in covert timing channels. Search on Bibsonomy CSFW The full citation details ... 1995 DBLP  DOI  BibTeX  RDF higher resolution synthetic clocks, timing channel countermeasure, Boeing multilevel secure local area network, secure network server, internal timing channels, time reference clock granularity, fine-grained signaling clock, timing channel throughput, timing channel capacities, local area networks, security of data, worst-case analysis, covert timing channels
69Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li 0001, Charles J. Alpert, Shyam Ramji, Chris Chu ITOP: integrating timing optimization within placement. Search on Bibsonomy ISPD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF placement, timing optimization, physical synthesis
67Aloysius K. Mok, Guangtian Liu Early detection of timing constraint violation at runtime. Search on Bibsonomy RTSS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF timing constraint violation detection, timing constraint compliance, conditional guarantees, satisfiability checking algorithm, timing constraint monitoring, time terms, timing constraint specification, real-time systems, real time applications
65Avi Efrati, Moshe Kleyner Timing analysis challenges for high speed CPUs at 90nm and below. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
64Jeffrey J. P. Tsai, Steve Jennhwa Yang, Yao-Hsiung Chang Timing Constraint Petri Nets and Their Application to Schedulability Analysis of Real-Time System Specifications. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF real-time systems, Petri nets, synthesis, timing analysis, Timing constraints, time Petri nets, timed Petri nets, specification and verification
60Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta 0001 A timing-driven design and validation methodology for embedded real-time systems. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF period assignment, period derivation, rate assignment, rate derivation, timing-driven codesign, requirements analysis, timing analysis, system-level design, performance verification
58Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula Statistical timing analysis using bounds and selective enumeration. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
57Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu 0001 Test structures for delay variability. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
57Louis Scheffer Explicit computation of performance as a function of process variation. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF static timing, process variation, yield, statistical timing
56Leo Motus, R. Kinksaar, Tonu Naks, M. Pall Enhancing object modelling technique with timing analysis capabilities. Search on Bibsonomy ICECCS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF enhanced object modelling technique, timing analysis capabilities, timing correctness, software implementation problems, specification problems, time-constraint elicitation, Q-model, noncontradiction analysis, time modelling requirements, performance, software engineering, real-time systems, real-time systems, data integrity, timing, scheduling algorithms, timing constraints, object-oriented methods, consistency checking, application domain, integrity checking, design problems
55Shuo Zhou, Yi Zhu 0002, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng Timing model reduction for hierarchical timing analysis. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF biclique-star replacement, hierarchical timing analysis
54Tai M. Chung, Henry G. Dietz Static scheduling of hard real-time code with instruction-level timing accuracy. Search on Bibsonomy RTCSA The full citation details ... 1996 DBLP  DOI  BibTeX  RDF timing fault, instruction-level timing accuracy, high-level language code, instruction-level, compiler code scheduling, genetic search algorithm, real-time systems, timing analysis, processor scheduling, search space
54Lo Ko, Christopher A. Healy, Emily Ratliff, Robert D. Arnold, David B. Whalley, Marion G. Harmon Supporting the specification and analysis of timing constraints. Search on Bibsonomy IEEE Real Time Technology and Applications Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF timing constraints analysis, real-time programmers, user-friendly environment, user specification, real-time systems, user interface, formal specification, timing, synchronisation, timing constraints, computer aided software engineering, C language, C program, project support environments
53Zhuo Feng, Peng Li 0001 A methodology for timing model characterization for statistical static timing analysis. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
53Mukund Sivaraman, Andrzej J. Strojwas Timing analysis based on primitive path delay fault identification. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF primitive path delay faults, correlated delay, floating mode, timing analysis, timing verification, false path, path delay fault testing
52Ali Dasdan Efficient algorithms for debugging timing constraint violations. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF over-constraint resolution, scheduling, high-level synthesis, constraint satisfaction, timing constraints, behavioral synthesis, rate analysis
52Markus Lindgren, Hans Hansson, Henrik Thane Using measurements to derive the worst-case execution time. Search on Bibsonomy RTCSA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF execution time analysis, program flow analysis, low level timing information, low level timing analysis, program execution times, timing measurements, instrumented version, program fragments, non-exhaustive measurements, program paths, realistic processor model, scheduling, real-time systems, real time systems, embedded systems, worst-case execution time, pipeline processing, schedulability analysis, program diagnostics, architectural modeling, pipeline architectures, flow graphs, timing estimates, target architecture, system of linear equations
51Steven Gianvecchio, Haining Wang Detecting covert timing channels: an entropy-based approach. Search on Bibsonomy CCS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF detection, covert timing channels
50Kurt Keutzer, Michael Orshansky From blind certainty to informed uncertainty. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
49Christopher J. Thompson, Andrew L. Goertzen A Method for Determination of the Timing Stability of PET Scanners. Search on Bibsonomy IEEE Trans. Medical Imaging The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
49Aloysius K. Mok, Guangtian Liu Efficient Run-Time Monitoring of Timing Constraints. Search on Bibsonomy IEEE Real Time Technology and Applications Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
49Vinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer Static timing analysis for self resetting circuits. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
49Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim An Accurate Worst Case Timing Analysis for RISC Processors. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF pipelined execution, real-time system, Cache memory, worst case execution time, RISC processor
49Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF overclocking, timing error detection, timing error recovery, fpga
49Ho Kyoung Lee, Woo Jin Lee, Heung Seok Chae, Yong Rae Kwon Specification and analysis of timing requirements for real-time systems in the CBD approach. Search on Bibsonomy Real Time Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Real-time system, Petri nets, Component, Timing analysis, Timing constraints, CBD, Compositional analysis
49Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer TA-PSV - Timing Analysis for Partially Specified Vectors. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF timing analysis for partially specified vectors (TA-PSV), crosstalk test generation (ATPG), static timing analysis (STA), delay model
47Uwe Fassnacht, Jürgen Schietke Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Timing, static timing analysis, timing optimization
46Bhavana Thudi, David T. Blaauw Efficient switching window computation for cross-talk noise. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
46Ed Grochowski, Murali Annavaram, Paul Reed Implications of device timing variability on full chip timing. Search on Bibsonomy ISPD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
46Murali Annavaram, Ed Grochowski, Paul Reed Implications of Device Timing Variability on Full Chip Timing. Search on Bibsonomy HPCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Min Pan, Chris C. N. Chu, Hai Zhou 0001 Timing yield estimation using statistical static timing analysis. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
46Tobias Thiel Have I Really Met Timing? - Validating PrimeTime Timing Reports with Spice. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
45Musab AlTurki, Dinakar Dhurjati, Dachuan Yu, Ajay Chander, Hiroshi Inamura Formal Specification and Analysis of Timing Properties in Software Systems. Search on Bibsonomy FASE The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
45Guilan Dai, Rujuan Liu, Chongchong Zhao, Changjun Hu Timing Constraints Specification and Verification for Web Service Compositions. Search on Bibsonomy APSCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
45Dipankar Das 0002, P. P. Chakrabarti 0001, Rajeev Kumar 0004 Scenario-based timing verification of multiprocessor embedded applications. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF execution scenarios, real time systems, static timing analysis, Timing verification
45David A. Papa, Tao Luo 0002, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li 0001, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. Search on Bibsonomy ISPD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF static timing analysis, timing-driven placement
45Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia "Timing closure by design, " a high frequency microprocessor design methodology. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF chip integration, dynamic circuits0, CAD, methodology, microprocessor, timing analysis, PLA, timing closure
43Wei-Tek Tsai, Hessam S. Sarjoughian, Wu Li, Xin Sun 0003 Timing specification and analysis for service-oriented simulation. Search on Bibsonomy SpringSim The full citation details ... 2009 DBLP  DOI  BibTeX  RDF service-oriented simulation, timing specifications and analysis, DEVS
43Shihheng Tsai, Chung-Yang Huang A false-path aware formal static timing analyzer considering simultaneous input transitions. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF critical path selection, multiple input transitioning, formal method, static timing analysis, false path
43Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer SACI: statistical static timing analysis of coupled interconnects. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF coupled interconnect, sources of variation, crosstalk noise, statistical timing analysis
43Mike Hutton, David Karchmer, Bryan Archell, Jason Govig Efficient static timing analysis and applications using edge masks. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF cut-path, multicycle, thru-x, FPGA, placement, timing analysis
43Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan First-order incremental block-based statistical timing analysis. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF variability, incremental, statistical timing
43Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate
43Rajesh K. Gupta 0001 A framework for interactive analysis of timing constraints in embedded systems. Search on Bibsonomy CODES The full citation details ... 1996 DBLP  DOI  BibTeX  RDF constraint satisfiability, performance evaluation, real-time systems, embedded systems, timing, computability, logic design, satisfiability, timing constraints, interactive analysis, timing performance
43Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan PEPPER - a timing driven early floorplanner. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay
43Anirudh Devgan Accurate device modeling techniques for efficient timing simulation of integrated circuits. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF device modeling techniques, Fast-to-evaluate and Accurate Simplified Transistor, aggressive MOS technologies, FAST models, timing, AGES, circuit analysis computing, integrated circuits, circuit simulators, transient analysis, transistors, transistor, transient simulator, timing simulation, timing simulator, electronic engineering computing, semiconductor device models
43Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray Concurrent timing optimization of latch-based digital systems. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
43Steve Brown, Germán Gutiérrez, Reed Nelson, Chris VanKrevelen A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF emitter-coupled logic, triple channel ATE controller, timing verniers, precision edge timing, drive waveforms, returning signals, system clock frequency, ECL, 500 MHz, 40 ps, timing, clocks, automatic test equipment, logic arrays, programmable controllers, gate array, high speed testing
43Hatice Kose-Bagci, Frank Broz, Qiming Shen, Kerstin Dautenhahn, Chrystopher L. Nehaniv As Time Goes By: Representing and Reasoning About Timing in Human-Robot Interaction Studies. Search on Bibsonomy AAAI Spring Symposium: It's All in the Timing The full citation details ... 2010 DBLP  BibTeX  RDF
43Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula Statistical timing analysis using bounds and selective enumeration. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
42Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
42Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen Block based statistical timing analysis with extended canonical timing model. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
42Cristinel Ababei, Kia Bazargan Timing Minimization by Statistical Timing hMetis-based Partitioning. Search on Bibsonomy VLSI Design The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
42Farid N. Najm, Noel Menezes Statistical timing analysis based on a timing yield model. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF statistical timing analysis, principal components, timing yield
41Parimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar Optimization strategies to improve statistical timing. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
41Euiseok Hwang, Rohit Negi, B. V. K. Vijaya Kumar Extended Kalman Filter Based Acquisition Timing Recovery for Magnetic Recording Read Channels. Search on Bibsonomy ICC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
41Chan-Gun Lee, Aloysius K. Mok, Prabhudev Konana Monitoring of Timing Constraints with Confidence Threshold Requirements. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF fault tolerance, Constraints, monitors, temporal logic, real-time and embedded systems
41Chee Sing Lee 0002, Wei Ting Loke, Wenjuan Zhang, Yajun Ha Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, Jeff Piaget, Natesan Venkateswaran, Jeffrey G. Hemmett First-Order Incremental Block-Based Statistical Timing Analysis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Aravind R. Nayak, John R. Barry, German S. Feyh, Steven W. McLaughlin Timing Recovery With Frequency Offset and Random Walk: Cramer-Rao Bound and a Phase-Locked Loop Postprocessor. Search on Bibsonomy IEEE Trans. Commun. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Aravind R. Nayak, John R. Barry, German S. Feyh, Steven W. McLaughlin Timing Recovery With Frequency Offset and Random Walk: Cramér-Rao Bound and a Phase- Locked Loop Postprocessor. Search on Bibsonomy IEEE Trans. Commun. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Chan-Gun Lee, Aloysius K. Mok, Prabhudev Konana Monitoring of Timing Constraints with Confidence Threshold Requirements. Search on Bibsonomy RTSS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Sibin Mohan, Frank Mueller 0001 Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions. Search on Bibsonomy IEEE Real-Time and Embedded Technology and Applications Symposium The full citation details ... 2008 DBLP  DOI  BibTeX  RDF hybrid timing anlalysis, hardware/software interactions, real-time systems, embedded systems, computer architecture, timing analysis, worst-case execution time, out-of-order execution
41Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang A methodology to improve timing yield in the presence of process variations. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF timing analysis, gate sizing, timing yield
41Peter A. Beerel, Ken S. Stevens, Hoshik Kim Relative Timing Based Verification of Timed Circuits and Systems. Search on Bibsonomy ASYNC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Relative Timing, Verification and Timed Circuits, Timing Constraints
41Martin Foltin, Brian Foutz, Sean Tyler Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF timing analysis, VLSI design, timing model, circuit optimization
41Karim Khordoc, Eduard Cerny Semantics and verification of action diagrams with linear timing. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF compatibility of interfaces, hardware interfaces, causality, timing verification, timing diagrams
41Sung-Kwan Kim, Sang Lyul Min, Rhan Ha Efficient worst case timing analysis of data caching. Search on Bibsonomy IEEE Real Time Technology and Applications Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF efficient worst case timing analysis, accurate timing analysis, pipelined execution, multiple memory locations, pointer based references, dynamic load/store instructions, WCET overestimation, global data flow analysis, benchmark programs, real-time systems, computational complexity, data caching, cache storage, instruction sets, reduced instruction set computing, data dependence analysis, cache block
41Shuichi Oikawa, Hideyuki Tokuda Efficient timing management for user-level real-time threads. Search on Bibsonomy IEEE Real Time Technology and Applications Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF efficient timing management, user-level real-time threads, specified time, upcalled user-level scheduler, user-level scheduler overhead, shared user-level timers, shared kernel/user structure, upcall performance, scheduling, performance evaluations, software engineering, real-time systems, resource allocation, timing, shared memory systems, kernel, processor scheduling, software performance evaluation, operating system kernels, hints, virtual processor
40Serge Egelman, Janice Y. Tsai, Lorrie Faith Cranor, Alessandro Acquisti Timing is everything?: the effects of timing and placement of online privacy indicators. Search on Bibsonomy CHI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF website indicators, privacy, timing, mental models, privacy policies, usable privacy and security
40Lei Ju 0001, Bach Khoa Huynh, Abhik Roychoudhury, Samarjit Chakraborty Timing analysis of esterel programs on general-purpose multiprocessors. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF multiprocessor, timing analysis, synchronous language, esterel
40Wilsaan M. Joiner, Mark Shelhamer A model of time estimation and error feedback in predictive timing behavior. Search on Bibsonomy J. Comput. Neurosci. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Error feedback, Prediction, Timing, Saccade
40Steven Gianvecchio, Haining Wang, Duminda Wijesekera, Sushil Jajodia Model-Based Covert Timing Channels: Automated Modeling and Evasion. Search on Bibsonomy RAID The full citation details ... 2008 DBLP  DOI  BibTeX  RDF traffic modeling, evasion, covert timing channels
40Khaled R. Heloue, Farid N. Najm Parameterized timing analysis with general delay models and arbitrary variation sources. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF nonlinear delay, parameterized timing analysis, variability
40Stephan Thesing Modeling a system controller for timing analysis. Search on Bibsonomy EMSOFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF aiT, verification, static analysis, VHDL, timing analysis, WCET, worst-case execution time, avionics, peripherals
40Alan Wassyng, Mark Lawford, Xiayong Hu Timing Tolerances in Safety-Critical Software. Search on Bibsonomy FM The full citation details ... 2005 DBLP  DOI  BibTeX  RDF timing tolerances, real-time, requirements, safety-critical
40Alejandro Hevia, Marcos A. Kiwi Strength of two data encryption standard implementations under timing attacks. Search on Bibsonomy ACM Trans. Inf. Syst. Secur. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF cryptography, cryptanalysis, data encryption standard, timing attack
40Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF spice verification, primary-path, secondary-path, timing analysis, assertion, assertibility
40S. Balajee, Ananta K. Majhi Automated AC (Timing) Characterization for Digital Circuit Testing. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Timing Characterization, STIL, Setup and Hold Time
40Supratik Chakraborty, David L. Dill, Kun-Yung Chang, Kenneth Y. Yun Timing Analysis of Extended Burst-Mode Circuits. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Extended burst-mode circuits, 3D design style, global timing constraints, uncertain component delays, thirteen-valued signal algebra, polynomial-time
39Zhuo Li 0001, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou Ultra-fast interconnect driven cell cloning for minimizing critical path delay. Search on Bibsonomy ISPD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF gate duplication, physical synthesis, timing-driven placement
39Ratnakar Goyal, Harindranath Parameswaran, Sachin Shrivastava Computation of Waveform Sensitivity Using Geometric Transforms for SSTA. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Timing Library, Accuracy, SSTA
39Salim Chowdhury, John Lillis Repeater insertion for concurrent setup and hold time violations with power-delay trade-off. Search on Bibsonomy ISPD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF early-mode timing, hold violation, late-mode timing, setup violation, timing optimization, repeater insertion
39Aloysius K. Mok, Duu-Chung Tsou, Ruud C. M. de Rooij The MSP.RTL real-time scheduler synthesis tool. Search on Bibsonomy RTSS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF MSP RTL real time scheduler synthesis tool, scheduler synthesis algorithm, real time scheduling problem, temporal constraint satisfaction problem, temporal constraint graph, input timing specification, incremental positive cycle detection algorithm, real time scheduling theory, Boeing 777 Integrated Airplane Information Management System, AIMS, constraint satisfaction, processor scheduling, timing constraints, resource constraints, application domains, search strategies, cyclic schedules, feasible schedule, timing semantics, real time logic
39Tapan J. Chakraborty, Vishwani D. Agrawal Simulation of at-speed tests for stuck-at faults. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test
39Hai Zhou 0001 Clock schedule verification with crosstalk. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF verification, delay, coupling, clock schedule
39Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer Minimum-power retiming for dual-supply CMOS circuits. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF dual-supply, retiming theory, low-power, synthesis, low-power design
39Kanak Agarwal, Dennis Sylvester, David T. Blaauw A library compatible driving point model for on-chip RLC interconnects. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
39Baris Taskin, Ivan S. Kourtev Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF optimization, linear programming, clock skew, cycle stealing
38Bing Li 0005, Christoph Knoth, Walter Schneider 0001, Manuel Schmidt, Ulf Schlichtmann Static Timing Model Extraction for Combinational Circuits. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
38Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38David E. Wallace, Carlo H. Séquin Plug-in timing models for an abstract timing verifier. Search on Bibsonomy DAC The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
38Liangjun Shao, Peng Song, Yufan Yan, Xintao Zhang, Mianjun Xiao, Fang Liu, Huajun Liu, Timing Qu Numerical Analysis of Screening-Current Induced Strain in a 16 T REBCO Insert Within a 20 T Background Field. Search on Bibsonomy IEEE Access The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
38Yimin Dou, Kewen Li, Hongjie Duan, Timing Li, Lin Dong, Zongchao Huang MDA GAN: Adversarial-Learning-Based 3-D Seismic Data Interpolation and Reconstruction for Complex Missing. Search on Bibsonomy IEEE Trans. Geosci. Remote. Sens. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
38Zhihao Liu, Yuanyuan Shang, Timing Li, Guanlin Chen, Yu Wang 0106, Qinghua Hu, Pengfei Zhu 0001 Robust Multi-Drone Multi-Target Tracking to Resolve Target Occlusion: A Benchmark. Search on Bibsonomy IEEE Trans. Multim. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
38Yimin Dou, Timing Li, Kewen Li, Hongjie Duan, Zhifeng Xu ContrasInver: Voxel-wise Contrastive Semi-supervised Learning for Seismic Inversion. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
38Yimin Dou, Kewen Li, Jianbing Zhu, Timing Li, Shaoquan Tan, Zongchao Huang MD Loss: Efficient Training of 3-D Seismic Fault Segmentation Network Under Sparse Labels by Weakening Anomaly Annotation. Search on Bibsonomy IEEE Trans. Geosci. Remote. Sens. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
38Yimin Dou, Kewen Li, Hongjie Duan, Timing Li, Lin Dong, Zongchao Huang MDA GAN: Adversarial-Learning-based 3-D Seismic Data Interpolation and Reconstruction for Complex Missing. Search on Bibsonomy CoRR The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
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