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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2225 occurrences of 1302 keywords
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Results
Found 4812 publication records. Showing 4812 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
72 | David Sheldon, Frank Vahid |
Making good points: application-specific pareto-point generation for design space exploration using statistical methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 123-132, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
configurable platform, fpga, low-power, exploration, speedup, pruning, pareto-optimal, design of experiments |
68 | Sebastien Vagnier, Hassane Essafi, Alain Mérigot |
A Configurable Processor Network for Document Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 232-239, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
configurable processor network, European STRETCH project, imaged document, component extraction, configurable network, information retrieval, document management, configurable processor, content-based information retrieval |
64 | Roman L. Lysecky, Frank Vahid |
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 480-485, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA fabric, self-improving chips, synthesis, reconfigurable computing, dynamic optimization, system-on-a-chip, platforms, codesign, Hardware/software partitioning, just-in-time compilation, configurable logic, place and route, warp processors |
64 | Carl Ebeling, Darren C. Cronquist, Paul Franklin |
Configurable computing: the catalyst for high-performance architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 364-373, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
high-performance architectures, cost-performance, application-specific computation pipelines, static configuration, FPGAs, computational complexity, computer architectures, configurable computing, dynamic control, RaPiD, application-specific hardware |
60 | Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu |
An FPGA-based re-configurable functional tester for memory chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 51-57, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
re-configurable tester, memory chips, re-configurable hardware platform, prototype tester, compiler, integrated circuit testing, reconfigurable architectures, integrated memory circuits |
58 | S. Kumar, Luiz Pires, Subburajan Ponnuswamy, C. Nanavati, J. Golusky, M. Vojta, S. Wadi, D. Pandalai, Henk A. E. Spaanenburg |
A benchmark suite for evaluating configurable computing systems--status, reflections, and future directions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 126-134, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
adaptive computing ssytems, configurable computing systems, stressmarks, specifications, benchmarks, methodology |
56 | Jingzhao Ou, Viktor K. Prasanna |
Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(2), pp. 355-382, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, design space exploration, processor, cosimulation |
53 | Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin |
Design, Debug, Deploy: The Creation of Configurable Computing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 187-196, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CAD for configurable computing, FPGA, design environments, configurable computing |
53 | Ann Gordon-Ross, Jeremy Lau, Brad Calder |
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 379-382, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cache tuning, phase prediction, phase-based reconfiguration, phase-based tuning, caches, configurable caches, configurable architecture |
51 | Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt |
Fast configurable-cache tuning with a unified second-level cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 323-326, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cache exploration, embedded systems, low power, low energy, cache optimization, architecture tuning, cache hierarchy, configurable cache |
51 | Fei Li 0003, Yan Lin 0001, Lei He 0001 |
FPGA power reduction using configurable dual-Vdd. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 735-740, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, low power, configurable, power efficient, dual-Vdd |
49 | Gorn Tepvorachai, Christos A. Papachristou |
A Configurable FIR Filter Scheme based on an Adaptive Multilayer Network Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 176-183, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Yajun Ran, Malgorzata Marek-Sadowska |
Designing via-configurable logic blocks for regular fabric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(1), pp. 1-14, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Florian Gottschalk, Wil M. P. van der Aalst, Monique H. Jansen-Vullers |
SAP WebFlow Made Configurable: Unifying Workflow Templates into a Configurable Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BPM ![In: Business Process Management, 5th International Conference, BPM 2007, Brisbane, Australia, September 24-28, 2007, Proceedings, pp. 262-270, 2007, Springer, 978-3-540-75182-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Workflow Template, Reference Model, Process Configuration |
47 | P. Greve, J. Hoffman, R. E. Smith |
Using Type Enforcement to Assure a Configurable Guard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 13th Annual Computer Security Applications Conference (ACSAC 1997), 8-12 December 1997, San Diego, CA, USA, pp. 146-, 1997, IEEE Computer Society, 0-8186-8274-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
type enforcement, configurable guard, guard systems, administrator configurable guard, input channel, connected output channel, assured processes, assurance arguments, operational guards, pipeline, electronic mail, electronic mail, trusted components |
45 | Grant Martin |
Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 113-127, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MPSoC, programming models, dataflow, instruction-set extension, multiprocessor system-on-chip, configurable processor, electronic system-level design |
45 | Takuji Narumi, Tomohiro Akagawa, Young Ah Seong, Michitaka Hirose |
Absolute field: proposal for a re-configurable spatial structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Advances in Computer Entertainment Technology ![In: Proceedings of the International Conference on Advances in Computer Entertainment Technology, ACE 2008, Yokohama, Japan, December 3-5, 2008, pp. 67-70, 2008, ACM, 978-1-60558-393-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
re-configurable spatial structure, spatial structures in memory, physical computing, art installation |
45 | Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid |
Configurable cache subsetting for fast cache tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 695-700, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
configurable cache tuning, low energy, cache optimization |
45 | Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang |
Instruction set extension with shadow registers for configurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 99-106, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
shadow register, compilation, ASIP, configurable processor |
45 | Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang |
Application-specific instruction generation for configurable processor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 183-189, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
binate covering, compilation, ASIP, technology mapping, configurable processor |
45 | Zhen Luo, Margaret Martonosi, Pranav Ashar |
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 158-167, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Scanline Algorithm, Configurable Hardware, FPGA, DRC |
43 | Xiaofang Wang, Sotirios G. Ziavras |
A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, parallel processing, multiprocessor, dynamic load balancing, LU factorization |
43 | Chien-In Henry Chen, Kiran George |
Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 111-116, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Greg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid |
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 143-151, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Thirunavukkarasu Sivaharan, Gordon S. Blair, Geoff Coulson |
GREEN: A Configurable and Re-configurable Publish-Subscribe Middleware for Pervasive Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OTM Conferences (1) ![In: On the Move to Meaningful Internet Systems 2005: CoopIS, DOA, and ODBASE, OTM Confederated International Conferences CoopIS, DOA, and ODBASE 2005, Agia Napa, Cyprus, October 31 - November 4, 2005, Proceedings, Part I, pp. 732-749, 2005, Springer, 3-540-29736-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Christian Siemers, Volker Winterstein |
The Universal Configurable Block/Machine-- An Approach for a Configurable SoC-Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 26(3), pp. 309-331, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
block-based architecture, reconfigurable computing, space-time mapping |
40 | Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar |
A Compiler Intermediate Representation for Reconfigurable Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 36(5), pp. 493-520, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, VHDL, Configurable computing, Intermediate representation |
38 | Chih-Hao Sun, Ka-Hang Lok, You-Ming Tsao, Chia-Ming Chang, Shao-Yi Chien |
CFU: multi-purpose configurable filtering unit for mobile multimedia applications on graphics hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
High Performance Graphics ![In: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on High Performance Graphics 2009, New Orleans, Louisiana, USA, August 1-3, 2009, pp. 29-36, 2009, Eurographics Association, 978-1-60558-603-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
configurable filtering unit, texture filtering, streaming architecture |
38 | Matthew Collin Jordan, Ramachandran Vaidyanathan |
Configurable decoders with application in fast partial reconfiguration of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 259, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, decoder, look-up table, configurable logic |
38 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Instruction set synthesis with efficient instruction encoding for configurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 9:1-9:37, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding |
38 | Jeffrey M. Arnold |
The Architecture and Development Flow of the S5 Software Configurable Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 47(1), pp. 3-14, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
software configurable processor, reconfigurable architectures, embedded computing, instruction set extension |
38 | Hsin-hung Lin, Chih-wen Hsueh |
COS: A Configurable OS for Embedded SoC Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 16-18 August 2006, Sydney, Australia, pp. 242-245, 2006, IEEE Computer Society, 0-7695-2676-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Configurable OS, Embedded OS, Service-Oriented Architecture, SoC |
38 | Hongyi Wu, Chong Wang, Nian-Feng Tzeng |
Novel self-configurable positioning technique for multihop wireless networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 13(3), pp. 609-621, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
GPS-free, positioning techniques, wireless networks, self-configurable |
38 | Chuanjun Zhang, Frank Vahid, Walid A. Najjar |
A highly configurable cache for low energy embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(2), pp. 363-387, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, low power, Cache, microprocessor, configurable, memory hierarchy, low energy, architecture tuning |
38 | John Wei, Chris Rowen |
Implementing low-power configurable processors: practical options and tradeoffs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 706-711, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
PVT (process, voltage, temperature), configurable embedded processor, dynamic power efficiency, scaled VDD, low-power, leakage power, SOC (system on chip), dynamic power |
38 | Yajun Ran, Malgorzata Marek-Sadowska |
On designing via-configurable cell blocks for regular fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 198-203, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
via configurable, layout, regular fabric |
38 | Renate Henftling, Wolfgang Ecker, Andreas Zinn, Martin Zambaldi, Matthias Bauer 0003 |
An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 187, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
re-configurable architecture, hardware testbenches, acceleration of functional simulation, coarse-granular, fine-granular |
38 | Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas |
Verification of configurable processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 426-431, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
configurable processor cores, system-on-chip, test generation, design verification, co-simulation, coverage analysis |
37 | Brian Robinson, Lee J. White |
Testing of User-Configurable Software Systems Using Firewalls. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 19th International Symposium on Software Reliability Engineering (ISSRE 2008), 11-14 November 2008, Seattle/Redmond, WA, USA, pp. 177-186, 2008, IEEE Computer Society, 978-0-7695-3405-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Guy Gogniat, Wayne P. Burleson, Lilian Bossuet |
Configurable Computing for High-Security/High-Performance Ambient Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings, pp. 72-81, 2005, Springer, 3-540-26969-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Eivind Naess, Deborah A. Frincke, A. David McKinnon, David E. Bakken |
Configurable Middleware-Level Intrusion Detection for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS Workshops ![In: 25th International Conference on Distributed Computing Systems Workshops (ICDCS 2005 Workshops), 6-10 June 2005, Columbus, OH, USA, pp. 144-151, 2005, IEEE Computer Society, 0-7695-2328-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Krishna Sekar, Kanishka Lahiri, Sujit Dey |
Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 307-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Mikko Raatikainen, Timo Soininen, Tomi Männistö, Antti Mattila |
A Case Study of Two Configurable Software Product Families. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PFE ![In: Software Product-Family Engineering, 5th International Workshop, PFE 2003, Siena, Italy, November 4-6, 2003, Revised Papers, pp. 403-421, 2003, Springer, 3-540-21941-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Juha-Pekka Soininen, Antti Pelkonen, Jussi Roivainen |
Configurable Memory Organisation for Communication Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 86-93, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | David M. Brooks, Margaret Martonosi |
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANPC ![In: Network-Based Parallel Computing: Communication, Architecture, and Applications, Third International Workshop, CANPC '99, Orlando, Forida, USA, January 9, 1999, Proceedings, pp. 181-195, 1999, Springer, 3-540-65915-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Xiao Qu, Myra B. Cohen, Gregg Rothermel |
Configuration-aware regression testing: an empirical study of sampling and prioritization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSTA ![In: Proceedings of the ACM/SIGSOFT International Symposium on Software Testing and Analysis, ISSTA 2008, Seattle, WA, USA, July 20-24, 2008, pp. 75-86, 2008, ACM, 978-1-60558-050-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
regression testing, prioritization, combinatorial interaction testing, configurable software |
32 | Chia Hsiang Hsu, Cheng-Juei Yu, Sheng-De Wang |
Energy Saving Based on CPU Voltage Scaling and Hardware Software Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 17-19 December, 2007, Melbourne, Victoria, Australia, pp. 217-223, 2007, IEEE Computer Society, 0-7695-3054-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson |
Flexibility and low power: a contradiction in terms? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 375, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Ted Hills |
Response to A Note on Structured Interrupts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGOPS Oper. Syst. Rev. ![In: ACM SIGOPS Oper. Syst. Rev. 28(4), pp. 31-33, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
32 | Song Guo 0001, Zhuzhong Qian, Sanglu Lu |
A general energy optimization model for wireless networks using configurable antennas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 246-250, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
configurable antenna, mathematical formulation, energy efficiency |
32 | Yu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su |
Via configurable three-input lookup-tables for structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 49-54, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
via-configurable, layout, look-up-table, vlsi, structured ASIC |
32 | Murat Yuksel, Jayasri Akella, Shivkumar Kalyanaraman, Partha Dutta |
Free-space-optical mobile ad hoc networks: Auto-configurable building blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Networks ![In: Wirel. Networks 15(3), pp. 295-312, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Free space optical communication, Angular diversity, Auto-configurable |
32 | Guohan Lu, Yunfeng Shi, Chuanxiong Guo, Yongguang Zhang |
CAFE: a configurable packet forwarding engine for data center networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRESTO ![In: Proceedings of the ACM SIGCOMM 2009 Workshop on Programmable Routers for Extensible Services of Tomorrow, PRESTO 2009, Barcelona, Spain, August 21, 2009, pp. 25-30, 2009, ACM, 978-1-60558-446-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
configurable packet forwarding engine, data center networking, netfpga |
32 | Nastaran Baradaran, Pedro C. Diniz |
A compiler approach to managing storage and memory bandwidth in configurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(4), pp. 61:1-61:26, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
high-level hardware synthesis, storage allocation and management, Compiler analysis, configurable architectures |
32 | Eero Aho, Jarno Vanne, Timo D. Hämäläinen |
Configurable Data Memory for Multimedia Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 50(2), pp. 231-249, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
stride access, configurable, parallel memory, skewing scheme, SIMD processing |
32 | Anastasios D. Doulamis, Dimitrios I. Kosmopoulos, Manolis Sardis, Theodora A. Varvarigou |
An architecture for a self configurable video supervision. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AREA ![In: Proceedings of the 1st ACM Workshop on Analysis and Retrieval of Events/Actions and Workflows in Video Streams, AREA 2008, Vancouver, British Columbia, Canada, October 31, 2008, pp. 97-104, 2008, ACM, 978-1-60558-318-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
self configurable system, visual surveillance |
32 | Chen Huang 0005, David Sheldon, Frank Vahid |
Dynamic tuning of configurable architectures: the AWW online algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 97-102, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGAs, cache, online algorithms, dynamic optimization, tuning, configurable architecture, runtime configuration |
32 | Ricardo E. Gonzalez |
A Software-Configurable Processor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 26(5), pp. 42-51, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
software-configurable processor |
32 | Matti A. Hiltunen, François Taïani, Richard D. Schlichting |
Reflections on aspects and configurable protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AOSD ![In: Proceedings of the 5th International Conference on Aspect-Oriented Software Development, AOSD 2006, Bonn, Germany, March 20-24, 2006, pp. 87-98, 2006, ACM, 1-59593-300-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
extensible software, configurable software |
32 | Steve Leibson, James Kim |
Configurable Processors: A New Era in Chip Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 38(7), pp. 51-59, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
nanometer silicon lithography, microprocessors, multiprocessor systems, MPSoCs, configurable processors |
32 | Sadik Ezer, Scott Johnson |
Smart diagnostics for configurable processor verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 789-794, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded test-bench control, coverage, functional verification, diagnostics, configurable processors |
32 | Dilma Da Silva, Karsten Schwan, Greg Eisenhauer |
CTK: Configurable Object Abstractions for Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 27(6), pp. 531-549, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
high-performance objects, object fragmentation, complex parallel programming, library operating systems, dynamic adaptation, Configurable systems |
32 | Xiaoling Sun, Jian Xu, Pieter M. Trouborst |
Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 221-, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
configurable logic blocks, fault diagnosis, BIST, FPGA testing |
32 | Xiaojie Dong, Fan Du, Lionel M. Ni |
DWINS: A Dynamically Configurable Web-Based Information System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WECWIS ![In: Second International Workshop on Advance Issues of E-Commerce and Web-Based Information Systems (WECWIS 2000), Milpitas, California, USA, June 8-9, 2000, pp. 85-92, 2000, IEEE Computer Society, 0-7695-0610-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Web-based Information System and Active System, Dynamically Configurable |
32 | Nina T. Bhatti, Matti A. Hiltunen, Richard D. Schlichting, Wanda Chiu |
Coyote: A System for Constructing Fine-Grain Configurable Communication Services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 16(4), pp. 321-366, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
x-kernal, configurable sevices, event handlers, event-driven execution, microprotocols, mobile computing, protocols, multicast, modularity, customization, remote procedure call, membership |
32 | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1037-1046, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
IDDQ Tes t, Configurable Logic Blocks, FPGA, Testing, Bridging Fault, Programming Phase |
30 | Marius Nita, David Notkin |
White-box approaches for improved testing and analysis of configurable software systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE Companion ![In: 31st International Conference on Software Engineering, ICSE 2009, May 16-24, 2009, Vancouver, Canada, Companion Volume, pp. 307-310, 2009, IEEE, 978-1-4244-3494-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Thomas Jacob Koickal, Luiz Carlos Gouveia, Alister Hamilton |
Bio-inspired Event Coded Configurable Analog Circuit Block. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings, pp. 285-295, 2008, Springer, 978-3-540-85856-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Adam Prout, Joanne M. Atlee, Nancy A. Day, Pourya Shaker |
Semantically Configurable Code Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MoDELS ![In: Model Driven Engineering Languages and Systems, 11th International Conference, MoDELS 2008, Toulouse, France, September 28 - October 3, 2008. Proceedings, pp. 705-720, 2008, Springer, 978-3-540-87874-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Shih-Chang Hsia, Si-Hong Wang, Ying-Chao Chou |
A Configurable IP for Mode Decision of H.264/AVC Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 146-152, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Lipo Chan, Shanika Karunasekera |
Designing Configurable Publish-Subscribe Scheme for Decentralised Overlay Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: 21st International Conference on Advanced Information Networking and Applications (AINA 2007), May 21-23, 2007, Niagara Falls, Canada, pp. 102-109, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, Manas Pandey |
A design flow for configurable embedded processors based on optimized instruction set extension synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 581-586, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Rong-Jian Chen, Yi-Te Lai, Jui-Lin Lai |
Architecture design and VLSI hardware implementation of image encryption/decryption system using re-configurable 2D Von Neumann cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Carl Ebeling |
Configurable Computing Platforms - Promises, Promises. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 3-4, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Patrick Lysaght, P. A. Subrahmanyam |
Guest Editors' Introduction: Advances in Configurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(2), pp. 85-89, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Masaharu Imai, Akira Kitajima |
Verification Challenges in Configurable Processor Design with ASIP Meister. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 2, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Zhi Yang, Jiajun Bu, Chun Chen 0001, Linjian Mo |
Configurable Complexity-Bounded Motion Estimation for Real-Time Video Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIVS ![In: Advanced Concepts for Intelligent Vision Systems, 7th International Conference, ACIVS 2005, Antwerp, Belgium, September 20-23, 2005, Proceedings, pp. 555-562, 2005, Springer, 3-540-29032-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Bill Pontikakis, François R. Boyer, Yvon Savaria |
Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 454-458, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Krishna Sekar, Kanishka Lahiri, Sujit Dey |
Dynamic Platform Management for Configurable Platform-Based System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 641-649, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
ASIC |
30 | Takayuki Shiga, Mizuho Iwaihara, Yahiko Kambayashi |
Designing Web Menu for Configurable Goods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EC-Web ![In: E-Commerce and Web Technologies, 4th International Conference, EC-Web, Prague, Czech Republic, September 2-5, 2003, Proceedings, pp. 348-358, 2003, Springer, 3-540-40808-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Chien-In Henry Chen, Kiran George |
Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 521-524, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Chuanjun Zhang, Frank Vahid |
A power-configurable bus for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 809-812, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Michael J. Wirthlin, Steve Morrison, Paul S. Graham, Brian Bray |
Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 267-278, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik |
Using configurable computing to accelerate Boolean satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6), pp. 861-868, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Peter Zipf, Claude Stötzler, Manfred Glesner |
A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 266-267, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Seungrok Jung, Jungsoo Kim, Sangkwon Na, Chong-Min Kyung |
Energy-aware instruction-set customization for real-time embedded multiprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 335-338, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
DVFS, instruction set extensions, configurable processors |
28 | Chuanjun Zhang, Frank Vahid, Roman L. Lysecky |
A Self-Tuning Cache Architecture for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 142-147, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
on-chip CAD, embedded systems, low power, Cache, configurable, dynamic optimization, low energy, architecture tuning |
28 | Krister Brink, Magnus Olsson, Gunnar S. Bolmsjö |
Increased Autonomy in Industrial Robotic Systems: A Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 19(4), pp. 357-373, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
event based control, task oriented programming, configurable corrections, reactive re-planning, autonomy |
26 | Marcello La Rosa, Marlon Dumas, Arthur H. M. ter Hofstede, Jan Mendling, Florian Gottschalk |
Beyond Control-Flow: Extending Business Process Configuration to Roles and Objects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ER ![In: Conceptual Modeling - ER 2008, 27th International Conference on Conceptual Modeling, Barcelona, Spain, October 20-24, 2008. Proceedings, pp. 199-215, 2008, Springer, 978-3-540-87876-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
object flow, Process model, configuration, resource |
26 | Chul Kim, A. M. Rassau, Mike Myung-Ok Lee |
3D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 270, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Cristinel Ababei, Hushrav Mogal, Kia Bazargan |
3D FPGAs: placement, routing, and architecture evaluation (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 263, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Jan Recker, Michael Rosemann, Wil M. P. van der Aalst, Jan Mendling |
On the Syntax of Reference Model Configuration - Transforming the C-EPC into Lawful EPC Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Business Process Management Workshops ![In: Business Process Management Workshops, BPM 2005 International Workshops, BPI, BPD, ENEI, BPRM, WSCOBPM, BPS, Nancy, France, September 5, 2005, Revised Selected Papers, pp. 497-511, 2005, 3-540-32595-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Uwe Zdun |
Dynamically generating web application fragments from page templates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), March 10-14, 2002, Madrid, Spain, pp. 1113-1120, 2002, ACM, 1-58113-445-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
object-Oriented Scripting, web engineering, dynamic software architecture |
26 | Wesley J. Landaker, Michael J. Wirthlin, Brad L. Hutchings |
Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 806-815, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
Testing the Local Interconnect Resources of SRAM-Based FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 513-520, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, VLSI, test, ATPG |
26 | Maya B. Gokhale, Janice M. Stone, Edson Gomersall |
Co-Synthesis to a Hybrid RISC/FPGA Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 24(2-3), pp. 165-180, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Kang-Ngee Chia, Hea Joung Kim, Shane Lansing, William H. Mangione-Smith, J. Villasensor |
High-performance automatic target recognition through data-specific VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(3), pp. 364-371, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
26 | Jürgen Teich, Lothar Thiele |
Control generation in the design of processor arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 3(1-2), pp. 77-92, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
26 | Kevin Kratzer, Axel Böttcher |
Using an RTSJ-compatible MVC pattern as basis for configurable event-driven real-time software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JTRES ![In: Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems, JTRES 2010, Prague, Czech Republic, August 19-21, 2010, pp. 8-15, 2010, ACM, 978-1-4503-0122-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
real-time design patterns, real-time programming idioms, real-time Java, RTSJ, configurable software |
26 | Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz |
Using a configurable processor generator for computer architecture prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 358-369, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design |
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