Search results for "configurable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
72	David Sheldon, Frank Vahid	Making good points: application-specific pareto-point generation for design space exploration using statistical methods.	FPGA	2009	DBLP DOI BibTeX RDF	configurable platform, fpga, low-power, exploration, speedup, pruning, pareto-optimal, design of experiments
68	Sebastien Vagnier, Hassane Essafi, Alain Mérigot	A Configurable Processor Network for Document Management.	CAMP	2000	DBLP DOI BibTeX RDF	configurable processor network, European STRETCH project, imaged document, component extraction, configurable network, information retrieval, document management, configurable processor, content-based information retrieval
64	Roman L. Lysecky, Frank Vahid	A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning.	DATE	2004	DBLP DOI BibTeX RDF	FPGA fabric, self-improving chips, synthesis, reconfigurable computing, dynamic optimization, system-on-a-chip, platforms, codesign, Hardware/software partitioning, just-in-time compilation, configurable logic, place and route, warp processors
64	Carl Ebeling, Darren C. Cronquist, Paul Franklin	Configurable computing: the catalyst for high-performance architectures.	ASAP	1997	DBLP DOI BibTeX RDF	high-performance architectures, cost-performance, application-specific computation pipelines, static configuration, FPGAs, computational complexity, computer architectures, configurable computing, dynamic control, RaPiD, application-specific hardware
60	Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu	An FPGA-based re-configurable functional tester for memory chips.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	re-configurable tester, memory chips, re-configurable hardware platform, prototype tester, compiler, integrated circuit testing, reconfigurable architectures, integrated memory circuits
58	S. Kumar, Luiz Pires, Subburajan Ponnuswamy, C. Nanavati, J. Golusky, M. Vojta, S. Wadi, D. Pandalai, Henk A. E. Spaanenburg	A benchmark suite for evaluating configurable computing systems--status, reflections, and future directions.	FPGA	2000	DBLP DOI BibTeX RDF	adaptive computing ssytems, configurable computing systems, stressmarks, specifications, benchmarks, methodology
56	Jingzhao Ou, Viktor K. Prasanna	Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	FPGA, design space exploration, processor, cosimulation
53	Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin	Design, Debug, Deploy: The Creation of Configurable Computing Applications.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	CAD for configurable computing, FPGA, design environments, configurable computing
53	Ann Gordon-Ross, Jeremy Lau, Brad Calder	Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	cache tuning, phase prediction, phase-based reconfiguration, phase-based tuning, caches, configurable caches, configurable architecture
51	Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt	Fast configurable-cache tuning with a unified second-level cache.	ISLPED	2005	DBLP DOI BibTeX RDF	cache exploration, embedded systems, low power, low energy, cache optimization, architecture tuning, cache hierarchy, configurable cache
51	Fei Li 0003, Yan Lin 0001, Lei He 0001	FPGA power reduction using configurable dual-Vdd.	DAC	2004	DBLP DOI BibTeX RDF	FPGA, low power, configurable, power efficient, dual-Vdd
49	Gorn Tepvorachai, Christos A. Papachristou	A Configurable FIR Filter Scheme based on an Adaptive Multilayer Network Structure.	AHS	2007	DBLP DOI BibTeX RDF
49	Yajun Ran, Malgorzata Marek-Sadowska	Designing via-configurable logic blocks for regular fabric.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
47	Florian Gottschalk, Wil M. P. van der Aalst, Monique H. Jansen-Vullers	SAP WebFlow Made Configurable: Unifying Workflow Templates into a Configurable Model.	BPM	2007	DBLP DOI BibTeX RDF	Workflow Template, Reference Model, Process Configuration
47	P. Greve, J. Hoffman, R. E. Smith	Using Type Enforcement to Assure a Configurable Guard.	ACSAC	1997	DBLP DOI BibTeX RDF	type enforcement, configurable guard, guard systems, administrator configurable guard, input channel, connected output channel, assured processes, assurance arguments, operational guards, pipeline, electronic mail, electronic mail, trusted components
45	Grant Martin	Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	MPSoC, programming models, dataflow, instruction-set extension, multiprocessor system-on-chip, configurable processor, electronic system-level design
45	Takuji Narumi, Tomohiro Akagawa, Young Ah Seong, Michitaka Hirose	Absolute field: proposal for a re-configurable spatial structure.	Advances in Computer Entertainment Technology	2008	DBLP DOI BibTeX RDF	re-configurable spatial structure, spatial structures in memory, physical computing, art installation
45	Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid	Configurable cache subsetting for fast cache tuning.	DAC	2006	DBLP DOI BibTeX RDF	configurable cache tuning, low energy, cache optimization
45	Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang	Instruction set extension with shadow registers for configurable processors.	FPGA	2005	DBLP DOI BibTeX RDF	shadow register, compilation, ASIP, configurable processor
45	Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang	Application-specific instruction generation for configurable processor architectures.	FPGA	2004	DBLP DOI BibTeX RDF	binate covering, compilation, ASIP, technology mapping, configurable processor
45	Zhen Luo, Margaret Martonosi, Pranav Ashar	An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking.	FCCM	1999	DBLP DOI BibTeX RDF	Scanline Algorithm, Configurable Hardware, FPGA, DRC
43	Xiaofang Wang, Sotirios G. Ziavras	A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization.	IPDPS	2004	DBLP DOI BibTeX RDF	FPGA, parallel processing, multiprocessor, dynamic load balancing, LU factorization
43	Chien-In Henry Chen, Kiran George	Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.	ISQED	2003	DBLP DOI BibTeX RDF
43	Greg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid	Using On-Chip Configurable Logic to Reduce Embedded System Software Energy.	FCCM	2002	DBLP DOI BibTeX RDF
41	Thirunavukkarasu Sivaharan, Gordon S. Blair, Geoff Coulson	GREEN: A Configurable and Re-configurable Publish-Subscribe Middleware for Pervasive Computing.	OTM Conferences (1)	2005	DBLP DOI BibTeX RDF
41	Christian Siemers, Volker Winterstein	The Universal Configurable Block/Machine-- An Approach for a Configurable SoC-Architecture.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	block-based architecture, reconfigurable computing, space-time mapping
40	Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar	A Compiler Intermediate Representation for Reconfigurable Fabrics.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	FPGA, VHDL, Configurable computing, Intermediate representation
38	Chih-Hao Sun, Ka-Hang Lok, You-Ming Tsao, Chia-Ming Chang, Shao-Yi Chien	CFU: multi-purpose configurable filtering unit for mobile multimedia applications on graphics hardware.	High Performance Graphics	2009	DBLP DOI BibTeX RDF	configurable filtering unit, texture filtering, streaming architecture
38	Matthew Collin Jordan, Ramachandran Vaidyanathan	Configurable decoders with application in fast partial reconfiguration of FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, decoder, look-up table, configurable logic
38	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	Instruction set synthesis with efficient instruction encoding for configurable processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding
38	Jeffrey M. Arnold	The Architecture and Development Flow of the S5 Software Configurable Processor.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	software configurable processor, reconfigurable architectures, embedded computing, instruction set extension
38	Hsin-hung Lin, Chih-wen Hsueh	COS: A Configurable OS for Embedded SoC Systems.	RTCSA	2006	DBLP DOI BibTeX RDF	Configurable OS, Embedded OS, Service-Oriented Architecture, SoC
38	Hongyi Wu, Chong Wang, Nian-Feng Tzeng	Novel self-configurable positioning technique for multihop wireless networks.	IEEE/ACM Trans. Netw.	2005	DBLP DOI BibTeX RDF	GPS-free, positioning techniques, wireless networks, self-configurable
38	Chuanjun Zhang, Frank Vahid, Walid A. Najjar	A highly configurable cache for low energy embedded systems.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, microprocessor, configurable, memory hierarchy, low energy, architecture tuning
38	John Wei, Chris Rowen	Implementing low-power configurable processors: practical options and tradeoffs.	DAC	2005	DBLP DOI BibTeX RDF	PVT (process, voltage, temperature), configurable embedded processor, dynamic power efficiency, scaled VDD, low-power, leakage power, SOC (system on chip), dynamic power
38	Yajun Ran, Malgorzata Marek-Sadowska	On designing via-configurable cell blocks for regular fabrics.	DAC	2004	DBLP DOI BibTeX RDF	via configurable, layout, regular fabric
38	Renate Henftling, Wolfgang Ecker, Andreas Zinn, Martin Zambaldi, Matthias Bauer 0003	An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures.	IPDPS	2003	DBLP DOI BibTeX RDF	re-configurable architecture, hardware testbenches, acceleration of functional simulation, coarse-granular, fine-granular
38	Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas	Verification of configurable processor cores.	DAC	2000	DBLP DOI BibTeX RDF	configurable processor cores, system-on-chip, test generation, design verification, co-simulation, coverage analysis
37	Brian Robinson, Lee J. White	Testing of User-Configurable Software Systems Using Firewalls.	ISSRE	2008	DBLP DOI BibTeX RDF
37	Guy Gogniat, Wayne P. Burleson, Lilian Bossuet	Configurable Computing for High-Security/High-Performance Ambient Systems.	SAMOS	2005	DBLP DOI BibTeX RDF
37	Eivind Naess, Deborah A. Frincke, A. David McKinnon, David E. Bakken	Configurable Middleware-Level Intrusion Detection for Embedded Systems.	ICDCS Workshops	2005	DBLP DOI BibTeX RDF
37	Krishna Sekar, Kanishka Lahiri, Sujit Dey	Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips.	VLSI Design	2004	DBLP DOI BibTeX RDF
37	Mikko Raatikainen, Timo Soininen, Tomi Männistö, Antti Mattila	A Case Study of Two Configurable Software Product Families.	PFE	2003	DBLP DOI BibTeX RDF
37	Juha-Pekka Soininen, Antti Pelkonen, Jussi Roivainen	Configurable Memory Organisation for Communication Applications.	DSD	2002	DBLP DOI BibTeX RDF
37	David M. Brooks, Margaret Martonosi	Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware.	CANPC	1999	DBLP DOI BibTeX RDF
34	Xiao Qu, Myra B. Cohen, Gregg Rothermel	Configuration-aware regression testing: an empirical study of sampling and prioritization.	ISSTA	2008	DBLP DOI BibTeX RDF	regression testing, prioritization, combinatorial interaction testing, configurable software
32	Chia Hsiang Hsu, Cheng-Juei Yu, Sheng-De Wang	Energy Saving Based on CPU Voltage Scaling and Hardware Software Partitioning.	PRDC	2007	DBLP DOI BibTeX RDF
32	Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson	Flexibility and low power: a contradiction in terms?	ISLPED	2006	DBLP DOI BibTeX RDF
32	Ted Hills	Response to A Note on Structured Interrupts.	ACM SIGOPS Oper. Syst. Rev.	1994	DBLP DOI BibTeX RDF
32	Song Guo 0001, Zhuzhong Qian, Sanglu Lu	A general energy optimization model for wireless networks using configurable antennas.	SAC	2010	DBLP DOI BibTeX RDF	configurable antenna, mathematical formulation, energy efficiency
32	Yu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su	Via configurable three-input lookup-tables for structured ASICs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	via-configurable, layout, look-up-table, vlsi, structured ASIC
32	Murat Yuksel, Jayasri Akella, Shivkumar Kalyanaraman, Partha Dutta	Free-space-optical mobile ad hoc networks: Auto-configurable building blocks.	Wirel. Networks	2009	DBLP DOI BibTeX RDF	Free space optical communication, Angular diversity, Auto-configurable
32	Guohan Lu, Yunfeng Shi, Chuanxiong Guo, Yongguang Zhang	CAFE: a configurable packet forwarding engine for data center networks.	PRESTO	2009	DBLP DOI BibTeX RDF	configurable packet forwarding engine, data center networking, netfpga
32	Nastaran Baradaran, Pedro C. Diniz	A compiler approach to managing storage and memory bandwidth in configurable architectures.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	high-level hardware synthesis, storage allocation and management, Compiler analysis, configurable architectures
32	Eero Aho, Jarno Vanne, Timo D. Hämäläinen	Configurable Data Memory for Multimedia Processing.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	stride access, configurable, parallel memory, skewing scheme, SIMD processing
32	Anastasios D. Doulamis, Dimitrios I. Kosmopoulos, Manolis Sardis, Theodora A. Varvarigou	An architecture for a self configurable video supervision.	AREA	2008	DBLP DOI BibTeX RDF	self configurable system, visual surveillance
32	Chen Huang 0005, David Sheldon, Frank Vahid	Dynamic tuning of configurable architectures: the AWW online algorithm.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	FPGAs, cache, online algorithms, dynamic optimization, tuning, configurable architecture, runtime configuration
32	Ricardo E. Gonzalez	A Software-Configurable Processor Architecture.	IEEE Micro	2006	DBLP DOI BibTeX RDF	software-configurable processor
32	Matti A. Hiltunen, François Taïani, Richard D. Schlichting	Reflections on aspects and configurable protocols.	AOSD	2006	DBLP DOI BibTeX RDF	extensible software, configurable software
32	Steve Leibson, James Kim	Configurable Processors: A New Era in Chip Design.	Computer	2005	DBLP DOI BibTeX RDF	nanometer silicon lithography, microprocessors, multiprocessor systems, MPSoCs, configurable processors
32	Sadik Ezer, Scott Johnson	Smart diagnostics for configurable processor verification.	DAC	2005	DBLP DOI BibTeX RDF	embedded test-bench control, coverage, functional verification, diagnostics, configurable processors
32	Dilma Da Silva, Karsten Schwan, Greg Eisenhauer	CTK: Configurable Object Abstractions for Multiprocessors.	IEEE Trans. Software Eng.	2001	DBLP DOI BibTeX RDF	high-performance objects, object fragmentation, complex parallel programming, library operating systems, dynamic adaptation, Configurable systems
32	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules.	DFT	2001	DBLP DOI BibTeX RDF	configurable logic blocks, fault diagnosis, BIST, FPGA testing
32	Xiaojie Dong, Fan Du, Lionel M. Ni	DWINS: A Dynamically Configurable Web-Based Information System.	WECWIS	2000	DBLP DOI BibTeX RDF	Web-based Information System and Active System, Dynamically Configurable
32	Nina T. Bhatti, Matti A. Hiltunen, Richard D. Schlichting, Wanda Chiu	Coyote: A System for Constructing Fine-Grain Configurable Communication Services.	ACM Trans. Comput. Syst.	1998	DBLP DOI BibTeX RDF	x-kernal, configurable sevices, event handlers, event-driven execution, microprotocols, mobile computing, protocols, multicast, modularity, customization, remote procedure call, membership
32	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ.	ITC	1998	DBLP DOI BibTeX RDF	IDDQ Tes t, Configurable Logic Blocks, FPGA, Testing, Bridging Fault, Programming Phase
30	Marius Nita, David Notkin	White-box approaches for improved testing and analysis of configurable software systems.	ICSE Companion	2009	DBLP DOI BibTeX RDF
30	Thomas Jacob Koickal, Luiz Carlos Gouveia, Alister Hamilton	Bio-inspired Event Coded Configurable Analog Circuit Block.	ICES	2008	DBLP DOI BibTeX RDF
30	Adam Prout, Joanne M. Atlee, Nancy A. Day, Pourya Shaker	Semantically Configurable Code Generation.	MoDELS	2008	DBLP DOI BibTeX RDF
30	Shih-Chang Hsia, Si-Hong Wang, Ying-Chao Chou	A Configurable IP for Mode Decision of H.264/AVC Encoder.	AHS	2007	DBLP DOI BibTeX RDF
30	Lipo Chan, Shanika Karunasekera	Designing Configurable Publish-Subscribe Scheme for Decentralised Overlay Networks.	AINA	2007	DBLP DOI BibTeX RDF
30	Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, Manas Pandey	A design flow for configurable embedded processors based on optimized instruction set extension synthesis.	DATE	2006	DBLP DOI BibTeX RDF
30	Rong-Jian Chen, Yi-Te Lai, Jui-Lin Lai	Architecture design and VLSI hardware implementation of image encryption/decryption system using re-configurable 2D Von Neumann cellular automata.	ISCAS	2006	DBLP DOI BibTeX RDF
30	Carl Ebeling	Configurable Computing Platforms - Promises, Promises.	ASAP	2006	DBLP DOI BibTeX RDF
30	Patrick Lysaght, P. A. Subrahmanyam	Guest Editors' Introduction: Advances in Configurable Computing.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF
30	Masaharu Imai, Akira Kitajima	Verification Challenges in Configurable Processor Design with ASIP Meister.	CHARME	2005	DBLP DOI BibTeX RDF
30	Zhi Yang, Jiajun Bu, Chun Chen 0001, Linjian Mo	Configurable Complexity-Bounded Motion Estimation for Real-Time Video Encoding.	ACIVS	2005	DBLP DOI BibTeX RDF
30	Bill Pontikakis, François R. Boyer, Yvon Savaria	Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period.	IWSOC	2005	DBLP DOI BibTeX RDF
30	Krishna Sekar, Kanishka Lahiri, Sujit Dey	Dynamic Platform Management for Configurable Platform-Based System-on-Chips.	ICCAD	2003	DBLP DOI BibTeX RDF	ASIC
30	Takayuki Shiga, Mizuho Iwaihara, Yahiko Kambayashi	Designing Web Menu for Configurable Goods.	EC-Web	2003	DBLP DOI BibTeX RDF
30	Chien-In Henry Chen, Kiran George	Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].	ISCAS (5)	2003	DBLP DOI BibTeX RDF
30	Chuanjun Zhang, Frank Vahid	A power-configurable bus for embedded systems.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
30	Michael J. Wirthlin, Steve Morrison, Paul S. Graham, Brian Bray	Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware.	FCCM	2000	DBLP DOI BibTeX RDF
30	Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik	Using configurable computing to accelerate Boolean satisfiability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
28	Peter Zipf, Claude Stötzler, Manfred Glesner	A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture.	ISVLSI	2004	DBLP DOI BibTeX RDF
28	Seungrok Jung, Jungsoo Kim, Sangkwon Na, Chong-Min Kyung	Energy-aware instruction-set customization for real-time embedded multiprocessor systems.	ISLPED	2009	DBLP DOI BibTeX RDF	DVFS, instruction set extensions, configurable processors
28	Chuanjun Zhang, Frank Vahid, Roman L. Lysecky	A Self-Tuning Cache Architecture for Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF	on-chip CAD, embedded systems, low power, Cache, configurable, dynamic optimization, low energy, architecture tuning
28	Krister Brink, Magnus Olsson, Gunnar S. Bolmsjö	Increased Autonomy in Industrial Robotic Systems: A Framework.	J. Intell. Robotic Syst.	1997	DBLP DOI BibTeX RDF	event based control, task oriented programming, configurable corrections, reactive re-planning, autonomy
26	Marcello La Rosa, Marlon Dumas, Arthur H. M. ter Hofstede, Jan Mendling, Florian Gottschalk	Beyond Control-Flow: Extending Business Process Configuration to Roles and Objects.	ER	2008	DBLP DOI BibTeX RDF	object flow, Process model, configuration, resource
26	Chul Kim, A. M. Rassau, Mike Myung-Ok Lee	3D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
26	Cristinel Ababei, Hushrav Mogal, Kia Bazargan	3D FPGAs: placement, routing, and architecture evaluation (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
26	Jan Recker, Michael Rosemann, Wil M. P. van der Aalst, Jan Mendling	On the Syntax of Reference Model Configuration - Transforming the C-EPC into Lawful EPC Models.	Business Process Management Workshops	2005	DBLP DOI BibTeX RDF
26	Uwe Zdun	Dynamically generating web application fragments from page templates.	SAC	2002	DBLP DOI BibTeX RDF	object-Oriented Scripting, web engineering, dynamic software architecture
26	Wesley J. Landaker, Michael J. Wirthlin, Brad L. Hutchings	Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System.	FPL	2002	DBLP DOI BibTeX RDF
26	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	Testing the Local Interconnect Resources of SRAM-Based FPGA's.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	FPGA, VLSI, test, ATPG
26	Maya B. Gokhale, Janice M. Stone, Edson Gomersall	Co-Synthesis to a Hybrid RISC/FPGA Architecture.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
26	Kang-Ngee Chia, Hea Joung Kim, Shane Lansing, William H. Mangione-Smith, J. Villasensor	High-performance automatic target recognition through data-specific VLSI.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
26	Jürgen Teich, Lothar Thiele	Control generation in the design of processor arrays.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
26	Kevin Kratzer, Axel Böttcher	Using an RTSJ-compatible MVC pattern as basis for configurable event-driven real-time software.	JTRES	2010	DBLP DOI BibTeX RDF	real-time design patterns, real-time programming idioms, real-time Java, RTSJ, configurable software
26	Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz	Using a configurable processor generator for computer architecture prototyping.	MICRO	2009	DBLP DOI BibTeX RDF	computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design