Search results for "digital-CMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
27	Antti Mäntyniemi, Timo Rahkonen, Juha Kostamovaara	A high resolution digital CMOS time-to-digital converter based on nested delay locked loops.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
25	Nishant Chandra, Apoorva Kumar Yati, A. B. Bhattacharyya	Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
24	Robert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold	Digital RF Processing Techniques for SoC Radios, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
23	Jeff Y. F. Hsieh, Teresa H.-Y. Meng	Low-Power Parallel Video Compression Architecture for a Single-Chip Digital CMOS Camera.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
22	Tonia G. Morris, Denise M. Wilson, Stephen P. DeWeerth	Analog VLSI circuits for manufacturing inspection.	ARVLSI	1995	DBLP DOI BibTeX RDF	analog VLSI circuits, manufacturing inspection, programmable structuring elements, oriented edge detection, high speed preprocessors, serial/parallel processing, focal-plane processing, vertical bipolar phototransistors, digital CMOS process, adaptive image threshold, 2.0 micron, computer vision, VLSI, edge detection, mathematical morphology, machine vision, manufacture, morphological operations, selective attention, massively parallel architectures, CMOS analogue integrated circuits, automatic optical inspection, focal planes, analogue processing circuits
22	Maitham Shams, Mohamed I. Elmasry	Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions.	ICCD	1999	DBLP DOI BibTeX RDF
20	Zeynep Toprak Deniz, Yusuf Leblebici	Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
20	Kazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Kobayashi 0001, Nobukazu Takai, Masao Hotta	A Time-to-Digital Converter with small circuitry.	ASP-DAC	2009	DBLP DOI BibTeX RDF
20	Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt	High speed digital CMOS divide-by-N fequency divider.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Maitham Shams, Mohamed I. Elmasry	A formulation for quick evaluation and optimization of digital CMOS circuits.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
20	Haluk Konuk, F. Joel Ferguson	Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
20	Atila Alvandpour, Per Larsson-Edefors, Christer Svensson	Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits.	ISLPED	1998	DBLP DOI BibTeX RDF	short-circuit current, power consumption, power estimation
18	Daniele Bonomi, Giorgio Boselli, Gabriella Trucco, Valentino Liberali	Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs.	SBCCI	2006	DBLP DOI BibTeX RDF	crosstalk, mixed-signal ICs
18	Tonia Morris, Erica Fletcher, Cyrus Afghahi, Sami Issa, Kevin Connolly, Jean-Charles Korta	A Column-based Processing Array for High-speed Digital Image Processing.	ARVLSI	1999	DBLP DOI BibTeX RDF
18	Subhadeep Banik, Daibashish Gangopadhyay, T. K. Bhattacharyya	A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18µ Digital CMOS.	VLSI Design	2006	DBLP DOI BibTeX RDF
18	Chengming He, Degang Chen 0001, Randall L. Geiger	A low-voltage compatible two-stage amplifier with ≥120 dB gain in standard digital CMOS.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
18	Bedabrata Pain, Bruce Hancock, Thomas Cunningham, Guang Yang 0003, Suresh Seshadri, Julie Heynssens, Chris Wrigley	CMOS Digital Imager Design from a System-on-a-chip Perspective.	VLSI Design	2003	DBLP DOI BibTeX RDF
17	K. Wayne Current	Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch.	ISMVL	2000	DBLP DOI BibTeX RDF	quaternary, memory, circuit, latch
16	Kurt Schweiger, Horst Zimmermann	Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology.	DDECS	2008	DBLP DOI BibTeX RDF
16	Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino	Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.	DSD	2008	DBLP DOI BibTeX RDF
16	Sudhakar M. Reddy, Irith Pomeranz, Chen Liu	On tests to detect via opens in digital CMOS circuits.	DAC	2008	DBLP DOI BibTeX RDF	constrained stuck-at tests, test generation, DFT, open defects
16	Fikret Dülger, Sher Jiun Fang, Ahmed Nader Mohieldin, Paul Fontaine, Abdellatif Bellaouar, Michel Frechette	A quad-band receiver for GSM/GPRS/EDGE in 90 nm digital CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Manuel Delgado-Restituto, Jesús Ruiz-Amaya, José M. de la Rosa 0001, Juan Francisco Fernández-Bootello, Leila Díez, Rocío del Río Fernández, Ángel Rodríguez-Vázquez	An embedded 12-bit 80MS/s A/D/A interface for power-line communications in 0.13µm pure digital CMOS technology.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
16	Terje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor	A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS.	DATE	2004	DBLP DOI BibTeX RDF
16	Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera	A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process.	ASP-DAC	2004	DBLP DOI BibTeX RDF
16	Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui	Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process.	ASP-DAC	2004	DBLP DOI BibTeX RDF
16	Alain-Serge Porret, Thierry Melly, Eric A. Vittoz, Christian C. Enz	Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process.	ISLPED	2000	DBLP DOI BibTeX RDF	low-power, CMOS, low-voltage, RF, transceiver
16	Payam Heydari, Massoud Pedram	Analysis and Optimization of Ground Bounce in Digital CMOS Circuits.	ICCD	2000	DBLP DOI BibTeX RDF
16	José Antonio Sainz, R. Muñoz, J. A. Maiz, L. A. Aguado, Miquel Roca 0001	A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits.	IOLTW	2000	DBLP DOI BibTeX RDF	VLSI, Sensor, CMOS, Crosstalk, Digital
16	Massoud Pedram, Qing Wu 0002	Battery-Powered Digital CMOS Design.	DATE	1999	DBLP DOI BibTeX RDF
16	Bradley A. Minch, Paul E. Hasler	A floating-gate technology for digital CMOS processes.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
16	Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano	Partitioning and analysis of static digital CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
16	Venkata S. Rangavajjhala, Bharat L. Bhuva, Sherra E. Kerns	Statistical degradation analysis of digital CMOS IC's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
16	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah	A Low Power Approach to Floating Point Adder Design for DSP Applications.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	digital-CMOS, power-consumption-model, VLSI, low-power-design, computer-arithmetic, floating-point, switching-activity
16	Dejan Markovic, Borivoje Nikolic, Robert W. Brodersen	Analysis and design of low-energy flip-flops.	ISLPED	2001	DBLP DOI BibTeX RDF	digital CMOS, VLSI, low-power design, flip-flops, low-voltage
16	Nestoras Tzartzanis, William C. Athas	Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing.	ARVLSI	1999	DBLP DOI BibTeX RDF	low-power digital CMOS, adiabatic switching, clock-powered logic, energy recovery
16	Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang	Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.	ICCD	1996	DBLP DOI BibTeX RDF	pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
16	W. W. Bachmann, Sorin A. Huss	Efficient algorithms for multilevel power estimation of VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
16	Pui-Tak So, Cheong-Fat Chan, Chiu-sing Choy, Kong-Pang Pun	Ramp voltage supply using adiabatic charging principle.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
14	Josep Maria Margarit, Lluís Terés, Francisco Serra-Graells	A Sub-µW fully programmable CMOS DPS for uncooled infrared fast imaging.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Jussi-Pekka Jansson, Antti Mäntyniemi, Juha Kostamovaara	A delay line based CMOS time digitizer IC with 13 ps single-shot precision.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
14	Yijun Zhou, Jiren Yuan	An 8-Bit, 100-MHz low glitch interpolation DAC.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
14	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	Design of Variable Input Delay Gates for Low Dynamic Power Circuits.	PATMOS	2005	DBLP DOI BibTeX RDF
14	Christian Jesús B. Fayomi, Gordon W. Roberts, Mohamad Sawan	Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
14	Mehdi Jafaripanah, Bashir M. Al-Hashimi, Neil M. White	Adaptive sensor response correction using analog filter compatible with digital technology [load cell sensor applications].	ISCAS (6)	2005	DBLP DOI BibTeX RDF
14	F. Hashemi, Khayrollah Hadidi, Abdollah Khoei	Design of a CMOS image sensor with pixel-level ADC in 0.35µm process.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
14	Alex G. Dickinson, Bryan D. Ackland, El-Sayed Eid, David A. Inglis, Eric R. Fossum	Standard CMOS active pixel image sensors for multimedia applications.	ARVLSI	1995	DBLP DOI BibTeX RDF	CMOS active pixel image sensors, single chip video cameras, color filter array, document capture, 1024 pixel, multimedia, multimedia systems, CMOS integrated circuits, image sensors, transistors, video cameras, gain
13	Chun-Chi Chen, Chao-Lieh Chen, Wei Fang, Yen-Chan Chu	All-Digital CMOS Time-to-Digital Converter With Temperature-Measuring Capability.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
13	Elisa Sacco, Jorge Marin, Johan Vergauwen, Georges G. E. Gielen	Controlled-Oscillator Optimization for Highly-Digital CMOS Time-Based Sensor-to-Digital Converter Architectures.	SMACD	2018	DBLP DOI BibTeX RDF
13	Siliang Hua, Donghui Wang, Leiou Wang, Yan Liu, Jiarui Li	A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme.	ASICON	2015	DBLP DOI BibTeX RDF
13	Takamoto Watanabe, Yu Hou, Masaya Miyahara, Akira Matsuzawa	All-digital 0.016mm2 reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS.	ICECS	2014	DBLP DOI BibTeX RDF
13	Jonathan Borremans, Kameswaran Vengattaramane, Vito Giannini, Björn Debaillie, Wim Van Thillo, Jan Craninckx	A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
13	Jonathan Borremans, Kameswaran Vengattaramane, Kameswaran Giannini, Jan Craninckx	A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS.	ISSCC	2010	DBLP DOI BibTeX RDF
13	Takamoto Watanabe, Tomohito Terasawa	An all-digital ADC/TDC for sensor interface with TAD architecture in 0.18-µm digital CMOS.	ICECS	2009	DBLP DOI BibTeX RDF
13	Takamoto Watanabe, Shigenori Yamauchi, Tomohito Terasawa	A 0.0027-mm2 9.5-bit 50-MS/s all-digital A/D converter TAD in 65-nm digital CMOS.	ICECS	2009	DBLP DOI BibTeX RDF
13	Srini Ramaswamy, J. Krishnan, Brett Forejt, J. Joy, M. Burns, Gangadhar Burra	A High-Performance Digital-Input Class-D Amplifier with Direct Battery Connection in a 90nm Digital CMOS Process.	ISSCC	2008	DBLP DOI BibTeX RDF
13	Young-Chan Jang, Jun-Hyun Bae, Hong-June Park	A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
13	Yat-Fong Yung, Amine Bermak	A Digital CMOS Imager with Pixel Level Analog-to-digital Converter and Reconfigurable SRAM/Counter.	IWSOC	2004	DBLP DOI BibTeX RDF
12	Xavier Redondo, Jofre Pallares, Francisco Serra-Graells	A 1.2V 130µA 10-bit MOS-Only Log-Domain Sigma Delta Modulator.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Mohammad Danaie, Hamed Aminzadeh, Sasan Naseh	On the Linearization of MOSFET Capacitors.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Rajarshi Mukhopadhyay, S. W. Yoon, Y. Park, Chang-Ho Lee, S. Nuttinck, Joy Laskar	Investigation of inductors for digital Si-CMOS technologies.	ISCAS	2006	DBLP DOI BibTeX RDF
12	A. Seedher, Preetam Tadeparthy, K. A. S. Satheesh, V. T. Anuroop	Automated design of a 10-bit, 80MSPS WLAN DAC for linearity and low-area.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
12	Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede	A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.	DAC	2005	DBLP DOI BibTeX RDF	security IC, encryption, smart card, side-channel attack, differential power analysis, countermeasure
12	Gabriella Trucco, Giorgio Boselli, Valentino Liberali	A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
12	Gabriella Trucco, Giorgio Boselli, Valentino Liberali	An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs.	SBCCI	2004	DBLP DOI BibTeX RDF	crosstalk, mixed-signal ICs
12	Huseyin Dine, Franco Maloberti	An 8-bit current mode ripple folding A/D converter.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
12	V. Boonsobhak, Apisak Worapishet	A pixel-level ADC with improved performance trade-off for high-speed CMOS imagers.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
10	Hooman Farkhani, Mohammad Maymandi-Nejad, Manoj Sachdev	A fully digital ADC using a new delay element with enhanced linearity.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Hamed Aminzadeh, Mohammad Danaie, Reza Lotfi	Design of high-resolution MOSFET-only pipelined ADCs with digital calibration.	DATE	2007	DBLP DOI BibTeX RDF
10	Alistair Kitchen, Abdesselam Bouzerdoum, Amine Bermak	Time Domain Analogue to Digital Conversion in a Digital Pixel Sensor Array.	DELTA	2004	DBLP DOI BibTeX RDF
10	Jesper Steensgaard	High-resolution mismatch-shaping digital-to-analog converters.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
10	Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen	A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
10	Chun-Chi Chen, Chao-Lieh Chen, Yen-Chan Chu, Guan-Yu Lin	An Area-Effective High-Resolution All-Digital CMOS Time-Domain Smart Temperature Sensor.	Circuits Syst. Signal Process.	2024	DBLP DOI BibTeX RDF
10	Ang Yuan, Huidong Zhao, Xiao Wang, Zhi Li, Shushan Qiao	An Ultra-Low Leakage and Wide-Range Voltage Level Shifter for Low-Power Digital CMOS VLSIs.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
10	Woojun Choi, Jan A. Angevare, Injun Park, Kofi A. A. Makinwa, Youngcheol Chae	A 0.9-V 28-MHz Highly Digital CMOS Dual-RC Frequency Reference With ±200 ppm Inaccuracy From -40 °C to 85 °C.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
10	Fuyue Qian, Ye Li, Xiaowei Zhang, Jianxiong Xi, Lenian He	An all-digital CMOS temperature sensor with a wide supply voltage range.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
10	Chunfeng Bai, Donghai Qiao, Heming Zhao	A Compact Single-Transistor Current Source for Analog Design in Nanometer Digital CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
10	Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal	A 2.3 mW Multi-Frequency Clock Generator with -137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
10	Hamed Aminzadeh, Mohammad Mahdi Valinezhad	0.7-V supply, 21-nW All-MOS voltage reference using a MOS-Only current-driven reference core in digital CMOS.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
10	Mst Shamim Ara Shawkat, Nicole McFarlane	A Digital CMOS Silicon Photomultiplier Using Perimeter Gated Single Photon Avalanche Diodes With Asynchronous AER Readout.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
10	Seyed Mahmoud Anisheh, Hamed Abbasizadeh, Hossein Shamsi, Chitra Dadkhah, Kang-Yoon Lee	98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process.	IEEE Access	2019	DBLP DOI BibTeX RDF
10	Di Li 0003, Chunlong Fei, Xiaopeng Wu, Yintang Yang	A 6-bit digital CMOS variable gain attenuator with large dynamic range and high linearity-in-dB for ultrasound imaging applications.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
10	Mantas Sakalas, Jens Wagner, Niko Joram, Frank Ellinger	Design Approach for a Broadband Class-D Power Amplifier for Low Power Application in a 28 nm Digital CMOS Technology.	PRIME	2019	DBLP DOI BibTeX RDF
10	Daniel S. Truesdell, Benton H. Calhoun	A 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution.	CICC	2019	DBLP DOI BibTeX RDF
10	Dang Cong Thinh, Le Thanh Toi, Hoang Trang	Technology Education Challenges and Solution to Design a Process Design Kit for Digital CMOS Technology in Vietnam.	ISCIT	2019	DBLP DOI BibTeX RDF
10	Kang-Lun Chiu, Hsun-Wei Chan, Wei-Che Lee, Chang-Ting Wu, Henry Lopez Davila, Hung-Chih Liu, Meng-Yuan Huang, Chun-Yi Liu 0001, Tsai-Hua Lee, Hsin-Ting Chang, Chih-Wei Jen, Nien-Hsiang Chang, Pei-Yun Tsai, Yen-Cheng Kuan, Shyh-Jye Jou	A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN Applications.	A-SSCC	2019	DBLP DOI BibTeX RDF
10	Ankur Pokhara, Biswajit Mishra, Purvi Patel	All-Digital CMOS On-Chip Temperature Sensor with Time-Assisted Analytical Model.	VDAT	2019	DBLP DOI BibTeX RDF
10	Tong Fang, Runjiang Dou, Liyuan Liu, Jian Liu 0021, Nanjian Wu	A 25 fps 32 × 24 Digital CMOS Terahertz Image Sensor.	A-SSCC	2018	DBLP DOI BibTeX RDF
10	Gustavo Della Colletta, Luis Henrique de Carvalho Ferreira, Sameer R. Sonkusale, Giseli V. Rocha	A 20-nW 0.25-V Inverter-Based Asynchronous Delta-Sigma Modulator in 130-nm Digital CMOS Process.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
10	Anil Singh, Veena Rawat, Alpana Agarwal	Low-power 10-bit 100 MS/s pipelined ADC in digital CMOS technology.	IET Circuits Devices Syst.	2017	DBLP DOI BibTeX RDF
10	Shaan Sengupta, Hyunkyu Ouh, Matthew L. Johnston	An all-digital CMOS ambient light sensor using a single photon avalanche diode.	IEEE SENSORS	2017	DBLP DOI BibTeX RDF
10	Rodrigo A. S. Braga, Luis Henrique de Carvalho Ferreira, Gustavo Della Colletta, Odilon O. Dutra	Calibration-less Nauta OTA operating at 0.25-V power supply in a 130-nm digital CMOS process.	LASCAS	2017	DBLP DOI BibTeX RDF
10	Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, George L. Geannopoulos, Jonathan Douglas, Nasser A. Kurd	A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
10	Hans G. Kerkhoff, Hassan Ebrahimi	Investigation of Intermittent Resistive Faults in Digital CMOS Circuits.	J. Circuits Syst. Comput.	2016	DBLP DOI BibTeX RDF
10	Brian Aull	Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.	Sensors	2016	DBLP DOI BibTeX RDF
10	Thomas Polzer, Andreas Steininger	A general approach for comparing metastable behavior of digital CMOS gates.	DDECS	2016	DBLP DOI BibTeX RDF
10	Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski	Transistor stuck-on fault detection tests for digital CMOS circuits.	ETS	2016	DBLP DOI BibTeX RDF
10	Kiichi Niitsu, Atsuki Kobayashi, Yudai Ogawa, Matsuhiko Nishizawa, Kazuo Nakazato	Design of an energy-autonomous, disposable, supply-sensing biosensor using bio fuel cell and 0.23-V 0.25-µm zero-Vth all-digital CMOS supply-controlled ring oscillator with inductive transmitter.	ASP-DAC	2016	DBLP DOI BibTeX RDF
10	Asli Yelkenci, Okan Zafer Batur, Baykal Sarioglu	Ultra low power all-digital CMOS sensor read out circuit for optically powered biomedical systems.	CISP-BMEI	2016	DBLP DOI BibTeX RDF
10	Hassan Ebrahimi, Alireza Rohani, Hans G. Kerkhoff	Detecting intermittent resistive faults in digital CMOS circuits.	DFT	2016	DBLP DOI BibTeX RDF