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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 85 occurrences of 64 keywords
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Results
Found 142 publication records. Showing 142 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
96 | Razak Hossain, Leszek D. Wronski, Alexander Albicki |
Low power design using double edge triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(2), pp. 261-265, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
65 | Bill Pontikakis, Mohamed Nekili |
A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 101-104, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
52 | Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija |
Comparative analysis of double-edge versus single-edge triggered clocked storage elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 105-108, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
51 | Fatemeh Aezinia, S. Najafzadeh, Ali Afzali-Kusha |
Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1383-1386, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Nikola Nedovic, Vojin G. Oklobdzija |
Dual-edge triggered storage elements and clocking strategy for low-power systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(5), pp. 577-590, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija |
Conditional pre-charge techniques for power-efficient dual-edge clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 56-59, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
clocked storage elements, dual edge-triggered flip-flop, power consumption, clocking, clock distribution |
46 | Kumar N. Lalgudi, Marios C. Papaefthymiou |
Efficient retiming under a general delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 368-382, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
retiming algorithm, general delay model, edge-triggered circuits, load-dependent gate delays, register delays, integer linear programming constraints, integer phonotonic programming formulation, linear programming, delays, timing, integer programming, logic design, logic design, logic circuits, clock skew, propagation delays, interconnect delays |
44 | Syed Irfan Ahmed, Ralph D. Mason |
A dual edge-triggered phase-frequency detector architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 721-724, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Kuo-Hsing Cheng, Yung-Hsiang Lin |
A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 425-428, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou |
A high-performance low-power static differential double edge-triggered flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 802-805, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Yukiya Miura |
Dual Edge Triggered Flip-Flops for Noise Aware Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, pp. 217, 2011, IEEE Computer Society, 978-0-7695-4433-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
data signal, dependable design, edge triggered flip-flop, noise, synchronous circuits |
35 | Branka Medved Rogina, Bozidar Vojnovic |
Metastability evaluation method by propagation delay distribution measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 40-44, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement |
35 | W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi |
A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 398-402, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron |
34 | Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, Weidong Kuang |
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(3), pp. 338-345, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Tomasz S. Czajkowski, Stephen Dean Brown |
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 324-329, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino |
Analysis of power dissipation in double edge-triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(5), pp. 624-629, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Aliakbar Ghadiri, Hamid Mahmoodi-Meimand |
Dual-Edge Triggered Static Pulsed Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 846-849, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De |
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001, pp. 147-152, 2001, ACM, 1-58113-371-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
dual edge, low power, flip-flops, clocking, triggered, latches |
25 | Radu Negulescu, Xiaohua Kong |
Semi-Hiding Operators and the Analysis of Active-Edge Specifications for Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 2nd International Conference on Application of Concurrency to System Design (ACSD 2001), 25-30 June 2001, Newcastle upon Tyne, UK, pp. 189-, 2001, IEEE Computer Society, 0-7695-1071-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
protocol compliance, interface recasting, edge-triggered, verification, interface design, handshake |
25 | Stephen H. Unger, Chung-Jen Tan |
Clocking Schemes for High-Speed Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(10), pp. 880-895, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
clock pulses, edge-triggered flip-flops, edge tolerances, one-phase clocking, delays, timing, Clocking, digital systems, skew, latches, synchronous circuits |
24 | Lih-Yih Chiou, Shien-Chun Luo |
An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1157-1160, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | S. H. Rasouli, Amir Amirabadi, A. Seyedi, Ali Afzali-Kusha |
Double edge triggered Feedback Flip-Flop in sub 100NM technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 297-302, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen |
Engery-Efficient Double-Edge Triggered Flip-Flop Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1791-1794, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Myint Wai Phyu, Wang Ling Goh, Kiat Seng Yeo |
A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2429-2432, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Pradeep Varma, Ashutosh Chakraborty |
Low-Voltage, Double-Edge-Triggered Flip Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 11-20, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Wai Chung, Timothy Lo, Manoj Sachdev |
A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(6), pp. 913-918, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Li Ding 0002, Pinaki Mazumder, N. Srinivas |
A dual-rail static edge-triggered latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 645-648, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Kumar N. Lalgudi, Marios C. Papaefthymiou |
Retiming edge-triggered circuits under general delay models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12), pp. 1393-1408, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
20 | Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang |
Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Baris Taskin, Ivan S. Kourtev |
Delay insertion method in clock skew scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 47-54, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
delay insertion, re-convergent paths, optimization, linear programming, clock skew |
17 | Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti |
Model checking on timed-event structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5), pp. 601-611, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Carl Ebeling, Brian Lockyear |
On the performance of level-clocked circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 342-357, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits |
17 | Brian Lockyear, Carl Ebeling |
Optimal retiming of level-clocked circuits using symmetric clock schedules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9), pp. 1097-1109, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
14 | Eunji Song, Seyoung Jeong, Sung-Ho Hwang 0001 |
Edge-Triggered Three-Dimensional Object Detection Using a LiDAR Ring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 24(6), pp. 2005, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Shengnan Gao, Zhouhua Peng, Lu Liu 0003, Dan Wang 0001, Qing-Long Han |
Fixed-Time Resilient Edge-Triggered Estimation and Control of Surface Vehicles for Cooperative Target Tracking Under Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Intell. Veh. ![In: IEEE Trans. Intell. Veh. 8(1), pp. 547-556, January 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Sekeon Kim, Keonhee Cho, Kyeongrim Baek, Hyunjun Kim, Younmee Bae, Mijung Kim, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung |
A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Bingzheng Yang, Zhixian Deng, Huizhen Jenny Qian, Xun Luo |
71-to-89GHz 12Gb/s Double-Edge-Triggered Quadrature RFDAC with LO Leakage Suppression Achieving 20.5dBm Peak Output Power and 20.4% System Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 286-287, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Zhengfeng Huang, Wanshu Zhong, Lanxi Duan, Yue Zhang, Huaguo Liang, Jianan Wang, Tai Song, Yingchun Lu |
Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(13), pp. 2250231:1-2250231:17, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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14 | Siyue Qiu, Maoqun Yao, Zhiqiang Liu |
Low-Power Double-Edge Triggered D Flip-Flop Based on the Conditional Discharge Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCT ![In: 22nd IEEE International Conference on Communication Technology, ICCT 2022, Nanjing, China, November 11-14, 2022, pp. 1501-1505, 2022, IEEE, 978-1-6654-7067-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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14 | Xin Cheng 0001, Bin Li, Haowen Zhu, Yongqiang Zhang 0006, Zhang Zhang |
A high-resolution hybrid digital pulse width modulator with dual-edge-triggered flip-flops and hardware compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 49(1), pp. 159-168, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | S. Prema, N. Karthikeyan, S. Karthik 0001 |
Ultra-Low Power and High Sensitivity of Joint Clock Gating Based Dual Feedback Edge Triggered Flip Flop for Biomedical Imaging Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Medical Imaging Health Informatics ![In: J. Medical Imaging Health Informatics 11(12), pp. 3215-3222, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Zipeng Huang, Robert Bauer 0004, Ya-Jun Pan 0001 |
Distributed Formation Tracking Control with Edge-Triggered Communication Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: IECON 2021 - 47th Annual Conference of the IEEE Industrial Electronics Society, Toronto, ON, Canada, October 13-16, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-3554-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Uday Kiran Naidu Ekkurthi, Venkatesh Dasari, Jyoshnavi Akiri, Chua-Chin Wang |
A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-4, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Hemavathy Sriramulu, V. S. Kanchana Bhaaskaran |
Double Edge-Triggered Tristate Flip-Flop Physical Unclonable Function for Secure IoT Ecosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2021, Jaipur, India, December 18-22, 2021, pp. 44-47, 2021, IEEE, 978-1-7281-8753-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Yongmin Lee, Gicheol Shin, Yoonmyung Lee |
A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in IoT Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 40232-40245, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | L. Punitha, J. Sundararajan |
FPGA based design and implementation of low power dual edge triggered flipflop using dynamic signal driving scheme for memory applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 76, pp. 103098, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Neethu Anna Sabu, K. Batri |
Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 29(8), pp. 2050123:1-2050123:37, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | M. Prithivi Raj, G. Kavithaa |
Dynamic signal driving strategy based high speed and low powered dual edge triggered flip flop design used memory applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 71, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
14 | Yongmin Lee, Yoonmyung Lee |
A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 16(20), pp. 20190528, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
14 | Bin Liu 0041, Shuai Nie, Yaping Zhang, Shan Liang, Zhanlei Yang, Wenju Liu |
Loss and Double-edge-triggered Detector for Robust Small-footprint Keyword Spotting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2019, Brighton, United Kingdom, May 12-17, 2019, pp. 6361-6365, 2019, IEEE, 978-1-4799-8131-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
14 | Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang |
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), Fredericton, NB, Canada, May 21-23, 2019, pp. 37-42, 2019, IEEE, 978-1-7281-0092-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
14 | Sajid Khan 0001, Neha Gupta, Abhinav Vishwakarma, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma |
Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers, pp. 298-307, 2019, Springer, 978-981-32-9766-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
14 | Saeid Zoka, Mohammad Gholami |
A novel rising Edge Triggered Resettable D flip-flop using five input majority gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 61, pp. 327-335, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Inhak Han, Youngsoo Shin |
Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 23(5), pp. 61:1-61:21, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Ahmedullah Aziz, Roman Engel-Herbert, Sumeet Kumar Gupta, Nikhil Shukla |
A Three-Terminal Edge-Triggered Mott Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: 76th Device Research Conference, DRC 2018, Santa Barbara, CA, USA, June 24-27, 2018, pp. 1-2, 2018, IEEE, 978-1-5386-3027-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Dimitris Konstantinou, Anastasios Psarras, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos |
Low-power dual-edge-triggered synchronous latency-insensitive systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018, Thessaloniki, Greece, May 7-9, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-4788-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Xijiang Lin |
On applying scan based structural test for designs with dual-edge triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2017, Fort Worth, TX, USA, October 31 - Nov. 2, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-3413-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
14 | Reza Faghih Mirzaee, Niloofar Farahani |
Design of a Ternary Edge-Triggered D Flip-Flap-Flop for Multiple-Valued Sequential Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1609.03897, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
14 | Andrea Bonetti, Adam Teman, Andreas Burg |
An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 1850-1853, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Mariam Zomorodi Moghadam, Keivan Navi, Mahmood Kalemati |
A novel reversible design for double edge triggered flip-flops and new designs of reversible sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Syst. Sci. Eng. ![In: Comput. Syst. Sci. Eng. 29(3), 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
14 | Masashi Imai, Tomohiro Yoneda |
Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 141-144, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Seyed Ebrahim Esmaeili, Asim J. Al-Khalili |
10 GHz throughput FinFET dual-edge triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: IEEE 27th Canadian Conference on Electrical and Computer Engineering, CCECE 2014, Toronto, ON, Canada, May 4-7, 2014, pp. 1-4, 2014, IEEE, 978-1-4799-3099-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Li-Rong Wang, Kai-Yu Lo, Shyh-Jye Jou |
A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 96-C(10), pp. 1351-1355, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Keisuke Inoue, Mineo Kaneko |
Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12), pp. 2689-2697, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Kazuteru Namba, Takashi Katagiri, Hideo Ito |
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 29(4), pp. 545-554, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Anurag, Gurmohan Singh, Vemu Sulochana |
Low Power Dual Edge-Triggered Static D Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1307.3075, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
14 | Michael Trakimas, Robert D'Angelo, Shuchin Aeron, Timothy M. Hancock, Sameer R. Sonkusale |
A Compressed Sensing Analog-to-Information Converter With Edge-Triggered SAR ADC Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(5), pp. 1135-1148, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Xiaowen Wang, William H. Robinson |
Asynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9), pp. 2401-2411, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Sriram Muthukumar, GoangSeog Choi |
Low-power and area-efficient 9-transistor double-edge triggered flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 10(18), pp. 20130639, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Guoqiang Hang, Xuanchang Zhou, Yang Yang 0013, Xiaohui Hu, Xiaohu You 0001 |
Quaternary edge-triggered flip-flop with neuron-MOS literal circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNC ![In: Ninth International Conference on Natural Computation, ICNC 2013, Shenyang, China, July 23-25, 2013, pp. 1743-1747, 2013, IEEE, 978-1-4673-4714-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Inhak Han, Youngsoo Shin |
Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: Proceedings of 2013 International Conference on IC Design & Technology, ICICDT 2013, Pavia, Italy, May 29-31, 2013, pp. 17-20, 2013, IEEE, 978-1-4673-4740-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Guoqiang Hang, Xiaohui Hu, Hongli Zhu, Xiaohu You 0001 |
Differential Edge-Triggered Flip-Flops Using Neuron-MOS Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIS ![In: Ninth International Conference on Computational Intelligence and Security, CIS 2013, Emei Mountain, Sichan Province, China, December 14-15, 2013, pp. 313-317, 2013, IEEE Computer Society, 978-1-4799-2548-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Lin-rong Xiao, Xie-xiong Chen, Shi-yan Ying |
Design of dual-edge triggered flip-flops based on quantum-dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Zhejiang Univ. Sci. C ![In: J. Zhejiang Univ. Sci. C 13(5), pp. 385-392, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Abdoul Rjoub, Muna M. Al-Durrah |
The performance and behaviour of dual edge triggered flip-flops in nanotechnology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Aided Eng. Technol. ![In: Int. J. Comput. Aided Eng. Technol. 4(1), pp. 49-71, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung |
A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9), pp. 1860-1870, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Imran Ahmed Khan, Danish Sheikh, Mirza Tariq Beg |
Analysis of double edge triggered clocked storage elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2012 International Conference on Advances in Computing, Communications and Informatics, ICACCI '12, Chennai, India, August 3-5, 2012, pp. 1100-1103, 2012, ACM, 978-1-4503-1196-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Yoshihiro Ohkawa, Yukiya Miura |
Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, pp. 119-124, 2012, IEEE Computer Society, 978-1-4673-4555-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Seyed Ebrahim Esmaeili, Riadul Islam, Asim J. Al-Khalili, Glenn E. R. Cowan |
Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pp. 292-295, 2012, IEEE, 978-1-4673-1261-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Chien-Cheng Yu, Kuan-Ting Chen |
A novel design of low power double edge-triggered flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMEI ![In: 5th International Conference on BioMedical Engineering and Informatics, BMEI 2012, Chongqing, China, October 16-18, 2012, pp. 1363-1366, 2012, IEEE, 978-1-4673-1183-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Michael Trakimas, Timothy M. Hancock, Sameer R. Sonkusale |
A Compressed sensing analog-to-information converter with edge-triggered SAR ADC Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 3162-3165, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Kazuteru Namba, Takashi Katagiri, Hideo Ito |
Dual-edge-triggered FF with timing error detection capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, pp. 187-192, 2012, IEEE Computer Society, 978-1-4673-3043-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Myint Wai Phyu, Kangkang Fu, Wang Ling Goh, Kiat Seng Yeo |
Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 19(1), pp. 1-9, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Keisuke Inoue, Mineo Kaneko |
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 550-553, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Chun Zhao, W. Pan, C. Z. Zhao, Ka Lok Man, J. Choi, J. Chang |
Performance-effective compaction of standard cell library for edge-triggered latches utilizing 0.5 micron technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2011, Jeju, South Korea, November 17-18, 2011, pp. 313-316, 2011, IEEE, 978-1-4577-0709-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Tsung-Yi Wu, Tzi-Wei Kao, How-Rern Lin |
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12), pp. 2581-2589, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Hossein Karimiyan, Sayed Masoud Sayedi, Hossein Saidi 0001 |
Low-power dual-edge triggered state-retention scan flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 4(5), pp. 410-419, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan |
Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 4(6), pp. 499-514, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Xiaokuo Yang, Li Cai, Xiaohui Zhao, Nansheng Zhang |
Design and simulation of sequential circuits in quantum-dot cellular automata: Falling edge-triggered flip-flop and counter study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 41(1), pp. 56-63, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen |
Energy-Efficient Double-Edge Triggered Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 61(3), pp. 347-352, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin |
Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 444-449, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 321-324, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Lih-Yih Chiou, Shien-Chun Luo |
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 17(11), pp. 1659-1663, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Hossein Karimiyan, Sayed Masoud Sayedi, Hossein Saidi 0001 |
Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers, pp. 156-164, 2009, Springer, 978-3-642-11801-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan |
Dual-edge triggered energy recovery DCCER flip-flop for low energy applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: 19th European Conference on Circuit Theory and Design, ECCTD 2009, Antalya, Turkey, August 23-27, 2009, pp. 57-60, 2009, IEEE, 978-1-4244-3896-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Manoj Sharma, Arti Noor, Satish Chandra Tiwari, Kunwar Singh |
An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARTCom ![In: ARTCom 2009, International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, Kerala, India, 27-28 October 2009, pp. 478-481, 2009, IEEE Computer Society, 978-0-7695-3845-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Saravanan Ramamoorthy, Haibo Wang 0005, Sarma B. K. Vrudhula |
A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 123-126, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low power, memory, circuit design, FIFO |
14 | Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng |
XNOR-based double-edge-triggered flip-flop for two-phase pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 53-II(2), pp. 138-142, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Wei-Li Su, Herming Chiueh |
A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 553-556, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Baris Taskin, Ivan S. Kourtev |
Performance improvement of edge-triggered sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004, Tel Aviv, Israel, December 13-15, 2004, pp. 607-610, 2004, IEEE, 0-7803-8715-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng |
An XNOR-based Double-edge-triggered Flip-Flop for Two-phase Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCCT (1) ![In: Proceedings of the 2nd International Conference Computing, Communications and Control Technologies, CCCT 2004, Austin, TX, USA, August 14-17, 2004, Volume 1., pp. 79-84, 2004, The International Institute of Informatics and Systemics (IIIS). The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
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