Search results for "edge-triggered"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
96	Razak Hossain, Leszek D. Wronski, Alexander Albicki	Low power design using double edge triggered flip-flops.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
65	Bill Pontikakis, Mohamed Nekili	A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
52	Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija	Comparative analysis of double-edge versus single-edge triggered clocked storage elements.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
51	Fatemeh Aezinia, S. Najafzadeh, Ali Afzali-Kusha	Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops.	APCCAS	2006	DBLP DOI BibTeX RDF
48	Nikola Nedovic, Vojin G. Oklobdzija	Dual-edge triggered storage elements and clocking strategy for low-power systems.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
46	Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija	Conditional pre-charge techniques for power-efficient dual-edge clocking.	ISLPED	2002	DBLP DOI BibTeX RDF	clocked storage elements, dual edge-triggered flip-flop, power consumption, clocking, clock distribution
46	Kumar N. Lalgudi, Marios C. Papaefthymiou	Efficient retiming under a general delay model.	ARVLSI	1995	DBLP DOI BibTeX RDF	retiming algorithm, general delay model, edge-triggered circuits, load-dependent gate delays, register delays, integer linear programming constraints, integer phonotonic programming formulation, linear programming, delays, timing, integer programming, logic design, logic design, logic circuits, clock skew, propagation delays, interconnect delays
44	Syed Irfan Ahmed, Ralph D. Mason	A dual edge-triggered phase-frequency detector architecture.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
44	Kuo-Hsing Cheng, Yung-Hsiang Lin	A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
41	Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou	A high-performance low-power static differential double edge-triggered flip-flop.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
39	Yukiya Miura	Dual Edge Triggered Flip-Flops for Noise Aware Design.	ETS	2011	DBLP DOI BibTeX RDF	data signal, dependable design, edge triggered flip-flop, noise, synchronous circuits
35	Branka Medved Rogina, Bozidar Vojnovic	Metastability evaluation method by propagation delay distribution measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
35	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
34	Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, Weidong Kuang	Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
34	Tomasz S. Czajkowski, Stephen Dean Brown	Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits.	DAC	2007	DBLP DOI BibTeX RDF
34	Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino	Analysis of power dissipation in double edge-triggered flip-flops.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
30	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Dual-Edge Triggered Static Pulsed Flip-Flops.	VLSI Design	2005	DBLP DOI BibTeX RDF
27	James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De	Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.	ISLPED	2001	DBLP DOI BibTeX RDF	dual edge, low power, flip-flops, clocking, triggered, latches
25	Radu Negulescu, Xiaohua Kong	Semi-Hiding Operators and the Analysis of Active-Edge Specifications for Digital Circuits.	ACSD	2001	DBLP DOI BibTeX RDF	protocol compliance, interface recasting, edge-triggered, verification, interface design, handshake
25	Stephen H. Unger, Chung-Jen Tan	Clocking Schemes for High-Speed Digital Systems.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	clock pulses, edge-triggered flip-flops, edge tolerances, one-phase clocking, delays, timing, Clocking, digital systems, skew, latches, synchronous circuits
24	Lih-Yih Chiou, Shien-Chun Luo	An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop.	ISCAS	2007	DBLP DOI BibTeX RDF
24	S. H. Rasouli, Amir Amirabadi, A. Seyedi, Ali Afzali-Kusha	Double edge triggered Feedback Flip-Flop in sub 100NM technology.	ASP-DAC	2006	DBLP DOI BibTeX RDF
24	Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen	Engery-Efficient Double-Edge Triggered Flip-Flop Design.	APCCAS	2006	DBLP DOI BibTeX RDF
24	Myint Wai Phyu, Wang Ling Goh, Kiat Seng Yeo	A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
24	Pradeep Varma, Ashutosh Chakraborty	Low-Voltage, Double-Edge-Triggered Flip Flop.	PATMOS	2003	DBLP DOI BibTeX RDF
24	Wai Chung, Timothy Lo, Manoj Sachdev	A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
24	Li Ding 0002, Pinaki Mazumder, N. Srinivas	A dual-rail static edge-triggered latch.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
24	Kumar N. Lalgudi, Marios C. Papaefthymiou	Retiming edge-triggered circuits under general delay models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
20	Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang	Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Baris Taskin, Ivan S. Kourtev	Delay insertion method in clock skew scheduling.	ISPD	2005	DBLP DOI BibTeX RDF	delay insertion, re-convergent paths, optimization, linear programming, clock skew
17	Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti	Model checking on timed-event structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
17	Carl Ebeling, Brian Lockyear	On the performance of level-clocked circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits
17	Brian Lockyear, Carl Ebeling	Optimal retiming of level-clocked circuits using symmetric clock schedules.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
14	Eunji Song, Seyoung Jeong, Sung-Ho Hwang 0001	Edge-Triggered Three-Dimensional Object Detection Using a LiDAR Ring.	Sensors	2024	DBLP DOI BibTeX RDF
14	Shengnan Gao, Zhouhua Peng, Lu Liu 0003, Dan Wang 0001, Qing-Long Han	Fixed-Time Resilient Edge-Triggered Estimation and Control of Surface Vehicles for Cooperative Target Tracking Under Attacks.	IEEE Trans. Intell. Veh.	2023	DBLP DOI BibTeX RDF
14	Sekeon Kim, Keonhee Cho, Kyeongrim Baek, Hyunjun Kim, Younmee Bae, Mijung Kim, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung	A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
14	Bingzheng Yang, Zhixian Deng, Huizhen Jenny Qian, Xun Luo	71-to-89GHz 12Gb/s Double-Edge-Triggered Quadrature RFDAC with LO Leakage Suppression Achieving 20.5dBm Peak Output Power and 20.4% System Efficiency.	ISSCC	2023	DBLP DOI BibTeX RDF
14	Zhengfeng Huang, Wanshu Zhong, Lanxi Duan, Yue Zhang, Huaguo Liang, Jianan Wang, Tai Song, Yingchun Lu	Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
14	Siyue Qiu, Maoqun Yao, Zhiqiang Liu	Low-Power Double-Edge Triggered D Flip-Flop Based on the Conditional Discharge Technique.	ICCT	2022	DBLP DOI BibTeX RDF
14	Xin Cheng 0001, Bin Li, Haowen Zhu, Yongqiang Zhang 0006, Zhang Zhang	A high-resolution hybrid digital pulse width modulator with dual-edge-triggered flip-flops and hardware compensation.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
14	S. Prema, N. Karthikeyan, S. Karthik 0001	Ultra-Low Power and High Sensitivity of Joint Clock Gating Based Dual Feedback Edge Triggered Flip Flop for Biomedical Imaging Applications.	J. Medical Imaging Health Informatics	2021	DBLP DOI BibTeX RDF
14	Zipeng Huang, Robert Bauer 0004, Ya-Jun Pan 0001	Distributed Formation Tracking Control with Edge-Triggered Communication Mechanism.	IECON	2021	DBLP DOI BibTeX RDF
14	Uday Kiran Naidu Ekkurthi, Venkatesh Dasari, Jyoshnavi Akiri, Chua-Chin Wang	A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop.	ISCAS	2021	DBLP DOI BibTeX RDF
14	Hemavathy Sriramulu, V. S. Kanchana Bhaaskaran	Double Edge-Triggered Tristate Flip-Flop Physical Unclonable Function for Secure IoT Ecosystem.	iSES	2021	DBLP DOI BibTeX RDF
14	Yongmin Lee, Gicheol Shin, Yoonmyung Lee	A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in IoT Applications.	IEEE Access	2020	DBLP DOI BibTeX RDF
14	L. Punitha, J. Sundararajan	FPGA based design and implementation of low power dual edge triggered flipflop using dynamic signal driving scheme for memory applications.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
14	Neethu Anna Sabu, K. Batri	Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
14	M. Prithivi Raj, G. Kavithaa	Dynamic signal driving strategy based high speed and low powered dual edge triggered flip flop design used memory applications.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
14	Yongmin Lee, Yoonmyung Lee	A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
14	Bin Liu 0041, Shuai Nie, Yaping Zhang, Shan Liang, Zhanlei Yang, Wenju Liu	Loss and Double-edge-triggered Detector for Robust Small-footprint Keyword Spotting.	ICASSP	2019	DBLP DOI BibTeX RDF
14	Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang	Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic.	ISMVL	2019	DBLP DOI BibTeX RDF
14	Sajid Khan 0001, Neha Gupta, Abhinav Vishwakarma, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma	Dual-Edge Triggered Lightweight Implementation of AES for IoT Security.	VDAT	2019	DBLP DOI BibTeX RDF
14	Saeid Zoka, Mohammad Gholami	A novel rising Edge Triggered Resettable D flip-flop using five input majority gate.	Microprocess. Microsystems	2018	DBLP DOI BibTeX RDF
14	Inhak Han, Youngsoo Shin	Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops.	ACM Trans. Design Autom. Electr. Syst.	2018	DBLP DOI BibTeX RDF
14	Ahmedullah Aziz, Roman Engel-Herbert, Sumeet Kumar Gupta, Nikhil Shukla	A Three-Terminal Edge-Triggered Mott Switch.	DRC	2018	DBLP DOI BibTeX RDF
14	Dimitris Konstantinou, Anastasios Psarras, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos	Low-power dual-edge-triggered synchronous latency-insensitive systems.	MOCAST	2018	DBLP DOI BibTeX RDF
14	Xijiang Lin	On applying scan based structural test for designs with dual-edge triggered flip-flops.	ITC	2017	DBLP DOI BibTeX RDF
14	Reza Faghih Mirzaee, Niloofar Farahani	Design of a Ternary Edge-Triggered D Flip-Flap-Flop for Multiple-Valued Sequential Logic.	CoRR	2016	DBLP BibTeX RDF
14	Andrea Bonetti, Adam Teman, Andreas Burg	An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop.	ISCAS	2015	DBLP DOI BibTeX RDF
14	Mariam Zomorodi Moghadam, Keivan Navi, Mahmood Kalemati	A novel reversible design for double edge triggered flip-flops and new designs of reversible sequential circuits.	Comput. Syst. Sci. Eng.	2014	DBLP BibTeX RDF
14	Masashi Imai, Tomohiro Yoneda	Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits.	ISCAS	2014	DBLP DOI BibTeX RDF
14	Seyed Ebrahim Esmaeili, Asim J. Al-Khalili	10 GHz throughput FinFET dual-edge triggered flip-flops.	CCECE	2014	DBLP DOI BibTeX RDF
14	Li-Rong Wang, Kai-Yu Lo, Shyh-Jye Jou	A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design.	IEICE Trans. Electron.	2013	DBLP DOI BibTeX RDF
14	Keisuke Inoue, Mineo Kaneko	Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2013	DBLP DOI BibTeX RDF
14	Kazuteru Namba, Takashi Katagiri, Hideo Ito	Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop.	J. Electron. Test.	2013	DBLP DOI BibTeX RDF
14	Anurag, Gurmohan Singh, Vemu Sulochana	Low Power Dual Edge-Triggered Static D Flip-Flop.	CoRR	2013	DBLP BibTeX RDF
14	Michael Trakimas, Robert D'Angelo, Shuchin Aeron, Timothy M. Hancock, Sameer R. Sonkusale	A Compressed Sensing Analog-to-Information Converter With Edge-Triggered SAR ADC Core.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
14	Xiaowen Wang, William H. Robinson	Asynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
14	Sriram Muthukumar, GoangSeog Choi	Low-power and area-efficient 9-transistor double-edge triggered flip-flop.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
14	Guoqiang Hang, Xuanchang Zhou, Yang Yang 0013, Xiaohui Hu, Xiaohu You 0001	Quaternary edge-triggered flip-flop with neuron-MOS literal circuit.	ICNC	2013	DBLP DOI BibTeX RDF
14	Inhak Han, Youngsoo Shin	Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops.	ICICDT	2013	DBLP DOI BibTeX RDF
14	Guoqiang Hang, Xiaohui Hu, Hongli Zhu, Xiaohu You 0001	Differential Edge-Triggered Flip-Flops Using Neuron-MOS Transistors.	CIS	2013	DBLP DOI BibTeX RDF
14	Lin-rong Xiao, Xie-xiong Chen, Shi-yan Ying	Design of dual-edge triggered flip-flops based on quantum-dot cellular automata.	J. Zhejiang Univ. Sci. C	2012	DBLP DOI BibTeX RDF
14	Abdoul Rjoub, Muna M. Al-Durrah	The performance and behaviour of dual edge triggered flip-flops in nanotechnology.	Int. J. Comput. Aided Eng. Technol.	2012	DBLP DOI BibTeX RDF
14	Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung	A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
14	Imran Ahmed Khan, Danish Sheikh, Mirza Tariq Beg	Analysis of double edge triggered clocked storage elements.	ICACCI	2012	DBLP DOI BibTeX RDF
14	Yoshihiro Ohkawa, Yukiya Miura	Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection.	Asian Test Symposium	2012	DBLP DOI BibTeX RDF
14	Seyed Ebrahim Esmaeili, Riadul Islam, Asim J. Al-Khalili, Glenn E. R. Cowan	Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity.	ICECS	2012	DBLP DOI BibTeX RDF
14	Chien-Cheng Yu, Kuan-Ting Chen	A novel design of low power double edge-triggered flip-flop.	BMEI	2012	DBLP DOI BibTeX RDF
14	Michael Trakimas, Timothy M. Hancock, Sameer R. Sonkusale	A Compressed sensing analog-to-information converter with edge-triggered SAR ADC Core.	ISCAS	2012	DBLP DOI BibTeX RDF
14	Kazuteru Namba, Takashi Katagiri, Hideo Ito	Dual-edge-triggered FF with timing error detection capability.	DFT	2012	DBLP DOI BibTeX RDF
14	Myint Wai Phyu, Kangkang Fu, Wang Ling Goh, Kiat Seng Yeo	Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
14	Keisuke Inoue, Mineo Kaneko	Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis.	ISCAS	2011	DBLP DOI BibTeX RDF
14	Chun Zhao, W. Pan, C. Z. Zhao, Ka Lok Man, J. Choi, J. Chang	Performance-effective compaction of standard cell library for edge-triggered latches utilizing 0.5 micron technology.	ISOCC	2011	DBLP DOI BibTeX RDF
14	Tsung-Yi Wu, Tzi-Wei Kao, How-Rern Lin	Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2010	DBLP DOI BibTeX RDF
14	Hossein Karimiyan, Sayed Masoud Sayedi, Hossein Saidi 0001	Low-power dual-edge triggered state-retention scan flip-flop.	IET Comput. Digit. Tech.	2010	DBLP DOI BibTeX RDF
14	Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan	Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks.	IET Comput. Digit. Tech.	2010	DBLP DOI BibTeX RDF
14	Xiaokuo Yang, Li Cai, Xiaohui Zhao, Nansheng Zhang	Design and simulation of sequential circuits in quantum-dot cellular automata: Falling edge-triggered flip-flop and counter study.	Microelectron. J.	2010	DBLP DOI BibTeX RDF
14	Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen	Energy-Efficient Double-Edge Triggered Flip-Flop.	J. Signal Process. Syst.	2010	DBLP DOI BibTeX RDF
14	Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin	Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs.	ASP-DAC	2010	DBLP DOI BibTeX RDF
14	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency.	ISCAS	2010	DBLP DOI BibTeX RDF
14	Lih-Yih Chiou, Shien-Chun Luo	Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
14	Hossein Karimiyan, Sayed Masoud Sayedi, Hossein Saidi 0001	Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop.	PATMOS	2009	DBLP DOI BibTeX RDF
14	Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan	Dual-edge triggered energy recovery DCCER flip-flop for low energy applications.	ECCTD	2009	DBLP DOI BibTeX RDF
14	Manoj Sharma, Arti Noor, Satish Chandra Tiwari, Kunwar Singh	An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop.	ARTCom	2009	DBLP DOI BibTeX RDF
14	Saravanan Ramamoorthy, Haibo Wang 0005, Sarma B. K. Vrudhula	A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design.	ISQED	2008	DBLP DOI BibTeX RDF	low power, memory, circuit design, FIFO
14	Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng	XNOR-based double-edge-triggered flip-flop for two-phase pipelines.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
14	Wei-Li Su, Herming Chiueh	A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder.	ICECS	2006	DBLP DOI BibTeX RDF
14	Baris Taskin, Ivan S. Kourtev	Performance improvement of edge-triggered sequential circuits.	ICECS	2004	DBLP DOI BibTeX RDF
14	Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng	An XNOR-based Double-edge-triggered Flip-Flop for Two-phase Pipelines.	CCCT (1)	2004	DBLP BibTeX RDF