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Publication years (Num. hits)
1988-1992 (17) 1993 (24) 1994 (39) 1995 (70) 1996 (91) 1997 (71) 1998 (174) 1999 (146) 2000 (141) 2001 (145) 2002 (189) 2003 (238) 2004 (313) 2005 (324) 2006 (363) 2007 (373) 2008 (466) 2009 (335) 2010 (271) 2011 (275) 2012 (235) 2013 (278) 2014 (297) 2015 (287) 2016 (279) 2017 (270) 2018 (301) 2019 (307) 2020 (269) 2021 (238) 2022 (240) 2023 (265) 2024 (54)
Publication types (Num. hits)
article(1561) book(9) data(1) incollection(32) inproceedings(5688) phdthesis(79) proceedings(15)
Venues (Conferences, Journals, ...)
ReConFig(858) FPL(762) FPGA(529) FCCM(383) CoRR(245) FPT(180) DATE(121) IPDPS(121) IEEE Trans. Very Large Scale I...(119) DAC(114) IEEE Trans. Comput. Aided Des....(114) ACM Trans. Reconfigurable Tech...(107) ARC(96) ICCAD(85) ISCAS(80) DSD(63) More (+10 of total 806)
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Found 7385 publication records. Showing 7385 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
66Sudip K. Nag, Rob A. Rutenbar Performance-driven simultaneous place and route for island-style FPGAs. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Xilinx 4000-series FPGAs, island-style FPGAs, performance-driven simultaneous placement/routing, place and route tools, FPGAs, field programmable gate arrays, logic CAD, network routing, circuit layout CAD, industrial designs, circuit layout
61Jason Cong, Songjie Xu Performance-driven technology mapping for heterogeneous FPGAs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
57Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins Compiling and Optimizing Image Processing Algorithms for FPGAs. Search on Bibsonomy CAMP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF SA-C, language features, SA-C algorithms, performance numbers, image processing routines, Annapolis Microsystems WildForce board, Xilinx 4036XL FPGAs, FPGAs, VHDL, optimizing compiler, high-level language, data flow graphs, data flow graphs, image processing algorithms
53Vinay Verma, Shantanu Dutt, Vishal Suthar Efficient on-line testing of FPGAs with provable diagnosabilities. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability
52Bernard Girau Digital Hardware Implementation of 2D Compatible Neural Networks. Search on Bibsonomy IJCNN (3) The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
49Toshinori Sueyoshi Basic Knowledge to Understand FPGAs. Search on Bibsonomy Principles and Structures of FPGAs The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
49Jeffrey B. Goeders, Graham M. Holland, Lesley Shannon, Steven J. E. Wilton Systems-on-Chip on FPGAs. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
49Hugo A. Andrade, Stephan Ahrends, Simon Hogg Making FPGAs Accessible with LabVIEW. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
49Frank Hannig A Quick Tour of High-Level Synthesis Solutions for FPGAs. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
48Yajun Ran, Malgorzata Marek-Sadowska Crosstalk noise in FPGAs. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF FPGAs, noise, crosstalk, switch box
47Chandra Mulpuri, Scott Hauck Runtime and quality tradeoffs in FPGA placement and routing. Search on Bibsonomy FPGA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF fast CAD for FPGAs, FPGAs, routing, computer-aided design, placement
44Jason Cong, Hui Huang 0001, Xin Yuan 0005 Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPGA, technology mapping, CPLD, PLD
44Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña Power Consumption Management on FPGAs. Search on Bibsonomy CONIELECOMP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Genetic Algorithms, Field Programmable Gate Array, Power Consumption, Partial Reconfiguration, Circuit Design
44Young-Su Kwon, Bong-Il Park, Chong-Min Kyung SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
44Jason Cong, Hui Huang 0001, Xin Yuan 0005 Technology mapping for k/m-macrocell based FPGAs. Search on Bibsonomy FPGA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
43Katarzyna Leijten-Nowak, Jef L. van Meerbergen An FPGA architecture with enhanced datapath functionality. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF adder inverting property, application-domain tuning, logic block architectures, FPGAs, DSP, symmetry
42Steve Trimberger Security in SRAM FPGAs. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF security, FPGAs, reverse-engineering, encryption, bitstream
42Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan Thermal characterization and optimization in platform FPGAs. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Virtex4, platform FPGAs, thermal floorplan, placement, temperature, thermal
40Christophe Bobda, Nils Steenbock A Rapid Prototyping Environment for Distributed Reconfigurable Systems. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Bernard Girau Building a 2D-Compatible Multilayer Neural Network. Search on Bibsonomy IJCNN (2) The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
39Masahiro Iida What Is an FPGA? Search on Bibsonomy Principles and Structures of FPGAs The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
39Masahiro Iida Design Methodology. Search on Bibsonomy Principles and Structures of FPGAs The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
39Tomonori Izumi, Yukio Mitsuyama Design Flow and Design Tools. Search on Bibsonomy Principles and Structures of FPGAs The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
39Kentaro Sano, Hiroki Nakahara Hardware Algorithms. Search on Bibsonomy Principles and Structures of FPGAs The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
39Tsutomu Maruyama, Yoshiki Yamaguchi, Yasunori Osana Programmable Logic Devices (PLDs) in Practical Applications. Search on Bibsonomy Principles and Structures of FPGAs The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
39Motoki Amagasaki, Yuichiro Shibata FPGA Structure. Search on Bibsonomy Principles and Structures of FPGAs The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
39Masato Motomura, Masanori Hariyama, Minoru Watanabe Advanced Devices and Architectures. Search on Bibsonomy Principles and Structures of FPGAs The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
39Moritz Schmid, Christian Schmitt 0003, Frank Hannig, Gorker Alp Malazgirt, Nehir Sönmez, Arda Yurdakul, Adrián Cristal Big Data and HPC Acceleration with Vivado HLS. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39Hayden Kwok-Hay So, Cheng Liu FPGA Overlays. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39Deshanand P. Singh, Peter Yiannacouras OpenCL. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39Andreas Agne, Marco Platzner, Christian Plessl, Markus Happe, Enno Lübbers ReconOS. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39Dirk Koch, Daniel Ziener, Frank Hannig FPGA Versus Software Programming: Why, When, and How? Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39João M. P. Cardoso, Markus Weinhardt High-Level Synthesis. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39Walid A. Najjar, Jason R. Villarreal, Robert J. Halstead ROCCC 2.0. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich HIPAcc. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Dean Brown, Jason Helge Anderson LegUp High-Level Synthesis. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39Jason Cong, Muhuan Huang, Peichen Pan, Yuxin Wang, Peng Zhang 0007 Source-to-Source Optimization for HLS. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39Kermin Fleming, Michael Adler The LEAP FPGA Operating System. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39Oriol Arcas-Abella, Nehir Sönmez Bluespec SystemVerilog. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
39Tobias Becker, Oskar Mencer, Georgi Gaydadjiev Spatial Programming with OpenSPL. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
38David Sheldon, Frank Vahid Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs. Search on Bibsonomy CODES+ISSS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF BRAM, high-throughput design, pattern counting, redesigning circuit, FPGA, design patterns, stream, memory, ASIC
38Luca Sterpone, Massimo Violante A new decompression system for the configuration process of SRAM-based FPGAS. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF configuration mechanisms, compression algorithm, SRAM-based FPGA
38Owen Callanan, David Gregg, Andy Nisbet, Mike Peardon High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Stefan Mohl Innovative technologies I - Using FPGAs in supercomputers: breaking with reconfigurable computing. Search on Bibsonomy SC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Young-Su Kwon, C.-M. Kyung ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica What is the right model for programming and using modern FPGAs? Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
38Adam Donlin, Patrick Lysaght, Brandon Blodget, Gerd Troeger A Virtual File System for Dynamically Reconfigurable FPGAs. Search on Bibsonomy FPL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Mark I. Parsons, Francis W. Wray Programming FPGAs - Programming FPGAs: challenges and successes. Search on Bibsonomy SC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
37John Marty Emmert, Akash Randhar, Dinesh Bhatia Fast Floorplanning for FPGAs. Search on Bibsonomy FPL The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
37Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. Search on Bibsonomy FPL The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
36Jason Lee, Lesley Shannon Predicting the performance of application-specific NoCs implemented on FPGAs. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF performance, FPGAs, topologies, heterogeneous, NoCs, homogeneous, application-specific, routability
36Qiang Wang, Subodh Gupta, Jason Helge Anderson Clock power reduction for virtex-5 FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
36Quang Dinh, Deming Chen, Martin D. F. Wong A routing approach to reduce glitches in low power FPGAs. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF glitch reduction, path balancing, fpgas, routing, low power
36Gang Zhou, Harald Michalik, László Hinsenkamp Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs. Search on Bibsonomy ARC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF AES-GCM, pipelined Karatsuba multiplier, FPGAs, finite field arithmetic
36Stephen Neuendorffer, Kees A. Vissers Streaming Systems in FPGAs. Search on Bibsonomy SAMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF digital convergence, FPGAs, dataflow
36David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF scheduling, optimizations, FPGAs, compilers, binary translation, chaining, hardware synthesis
36Pedro C. Diniz, Joonseok Park Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures. Search on Bibsonomy FCCM The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Custom Computing, Data search and Data Reorganization Engines, Hardware support for Pointer Operations, Field-Programmable- Gate-Arrays (FPGAs)
36Marco Platzner, Bernhard Rinner, Reinhold Weiss A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs. Search on Bibsonomy PDP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF distributed computer architecture, multi-DSP, application-specific computer architecture, constraint-check-function, performance, FPGAs, parallel architectures, computer architecture, digital simulation, hardware design, special purpose computers, design strategies, qualitative simulation
36Jae-Tack Yoo, Erik Brunvand, Kent F. Smith Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
36Stanley Habib, Quan Xu Technology mapping algorithms for sequential circuits using look-up table based FPGAS. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table
34Balasubramanian Sethuraman Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Christophe Bobda, Nils Steenbock Singular Value Decomposition on Distributed Reconfigurable Systems. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
34Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray 0002 Reconfigurable PDA for the Visually Impaired Using FPGAs. Search on Bibsonomy ReConFig The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGAs, embedded systems, Assistive technology, system on a chip
34Bin Zhou, David Hwang Implementations and Optimizations of Pipeline FFTs on Xilinx FPGAs. Search on Bibsonomy ReConFig The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Pipeline FFTs, FPGAs
34Xiaofang Wang, Swetha Thota Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAs. Search on Bibsonomy ReConFig The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGAs, multiprocessor, network-on-chip
33Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra Efficient FPGAs using nanoelectromechanical relays. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF CMOS-NEM FPGA, nanoelectromechanical relay
33Laurent Sauvage, Sylvain Guilley, Yves Mathieu Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module. Search on Bibsonomy ACM Trans. Reconfigurable Technol. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF EMA, security, FPGA, DPA, SCA, cartography
33Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration
33Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau Measuring and modeling variabilityusing low-cost FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF variability
33Victor Dumitriu, Dennis Marcantonio, Lev Kirischian Run-Time Component Relocation in Partially-Reconfigurable FPGAs. Search on Bibsonomy CSE (2) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
33Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert Architectural Modifications to Enhance the Floating-Point Performance of FPGAs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Nan Guan, Qingxu Deng, Zonghua Gu 0001, Wenyao Xu, Ge Yu 0001 Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF reconfigurable devices, FPGA, Real-time scheduling
33Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie 0001, Vijaykrishnan Narayanan Thermal-aware reliability analysis for platform FPGAs. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. Search on Bibsonomy J. Electron. Test. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF reliability, fault tolerant systems, SEU, SRAM-based FPGA
33Reza M. Rad, Mohammad Tehranipoor Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF performance, FPGA, reliability, CMOS, Nanotechnology
33Shilpa Bhoj, Dinesh Bhatia Thermal Modeling and Temperature Driven Placement for FPGAs. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
33Luca Sterpone, Massimo Violante A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF transient fault injection, FPGA, reliability, place and route
33Lei Cheng 0001, Martin D. F. Wong Floorplan Design for Multimillion Gate FPGAs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Suresh Srinivasan, Narayanan Vijaykrishnan Variation Aware Placement for FPGAs. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33François-Xavier Standaert, François Macé, Eric Peeters, Jean-Jacques Quisquater Updates on the Security of FPGAs Against Power Analysis Attacks. Search on Bibsonomy ARC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Suhap Sahin, Yasar Becerikli, Suleyman Yazici Neural Network Implementation in Hardware Using FPGAs. Search on Bibsonomy ICONIP (3) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Rajarshi Mukherjee, Seda Ogrenci Memik Evaluation of dual VDD fabrics for low power FPGAs. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
33K. Scott Hemmert, Keith D. Underwood An Analysis of the Double-Precision Floating-Point FFT on FPGAs. Search on Bibsonomy FCCM The full citation details ... 2005 DBLP  DOI  BibTeX  RDF IEEE floating point, FPGA, FFT, Fast Fourier Transform, reconfigurable computing
33Thomas J. Wollinger, Jorge Guajardo, Christof Paar Security on FPGAs: State-of-the-art implementations and attacks. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF cryptographic applications, security, FPGA, Cryptography, reverse engineering, attacks, reconfigurable hardware
33Paul Kohlbrenner, Kris Gaj An embedded true random number generator for FPGAs. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF TRNG, FPGA, random numbers, RNG, cryptographic
33Mike Hutton Architecture and CAD for FPGAs. Search on Bibsonomy SBCCI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
33Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang Energy-efficient signal processing using FPGAs. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF energy efficient design techniques, matrix multiplicaiton, FPGA, FFT, performance estimation
33Adrian J. Hilton, Gemma Townson, Jon G. Hall FPGAs in critical hardware/software systems. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
33Thomas J. Wollinger, Christof Paar How Secure Are FPGAs in Cryptographic Applications? Search on Bibsonomy FPL The full citation details ... 2003 DBLP  DOI  BibTeX  RDF security, FPGA, cryptography, attacks, reconfigurable hardware
33Herman Schmit Extra-dimensional Island-Style FPGAs. Search on Bibsonomy FPL The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
33Charles E. Stroud, Keshia N. Leach, Thomas A. Slaughter BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
33Shantanu Dutt, Vinay Verma, Hasan Arslan A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Bump-and-refit (B&R) paradigm, ECO (engineering change order), bumping cost, incremental routing, switchbox, field programmable gate arrays, dynamic programming, global routing, detailed routing
33Channakeshav, Kuan Zhou, Jong-Ru Guo, Chao You, Bryan S. Goda, Russell P. Kraft, John F. McDonald 0001 Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Bryan S. Goda, Russell P. Kraft, Steven R. Carlough, Thomas W. Krawczyk Jr., John F. McDonald 0001 Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs. Search on Bibsonomy FPL The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
33John Marty Emmert, Jason A. Cheatham On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router . Search on Bibsonomy DFT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
33Chi-Feng Wu, Cheng-Wen Wu Testing Interconnects of Dynamic Reconfigurable FPGAs. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
33Paul S. Graham, Brent E. Nelson Frequency-Domain Sonar Processing in FPGAs and DSPs. Search on Bibsonomy FCCM The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
33Jason Cong, Songjie Xu Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF technology mapping, programmable logic devices, PLA-style logic blocks
33Maya B. Gokhale, D. Gomersall High level compilation for fine grained FPGAs. Search on Bibsonomy FCCM The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
32John Woodfill, Brian Von Herzen Real-time stereo vision on the PARTS reconfigurable computer. Search on Bibsonomy FCCM The full citation details ... 1997 DBLP  DOI  BibTeX  RDF powerful scalable reconfigurable computer, PARTS engine, real-time stereo vision, Xilinx 4025 FPGAs, partial torus, concurrent SRAM access, standard PCI card, stereo vision algorithm, stereo disparity computation, RISC-equivalent operations, 1 Mbyte, images, SRAMs, stereo image processing, personal computer, workstation, memory access
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