Search results for "full-adder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
112	Sumeer Goel, Ashok Kumar 0001, Magdy A. Bayoumi	Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
85	Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello	New performance/power/area efficient, reliable full adder design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	d3l, reliability, dynamic, full-adder, sub-threshold
82	R. Shalem, Lizy Kurian John, Eugene John	A Novel Low Power Energy Recovery Full Adder Cell.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
79	Ahmed M. Shams, Tarek Darwish, Magdy A. Bayoumi	Performance analysis of low-power 1-bit CMOS full adder cells.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
77	Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai	High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability.	APCCAS	2006	DBLP DOI BibTeX RDF
71	Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho	A high speed and energy efficient full adder design using complementary & level restoring carry logic.	ISCAS	2006	DBLP DOI BibTeX RDF
70	Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang	A review of 0.18-μm full adder performances for tree structured arithmetic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
69	Mariano Aguirre, Mónico Linares Aranda	An alternative logic approach to implement high-speed low-power full adder cells.	SBCCI	2005	DBLP DOI BibTeX RDF	low-power, high-speed, full adder
68	Jerry W. Bruce, Mitchell A. Thornton, L. Shivakumaraiah, P. S. Kokate, X. Li	Efficient Adder Circuits Based on a Conservative Reversible Logic Gate.	ISVLSI	2002	DBLP DOI BibTeX RDF
63	Ayman A. Fayed, Magdy A. Bayoumi	A low power 10-transistor full adder cell for embedded architectures.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
63	Hanan A. Mahmoud, Magdy A. Bayoumi	A 10-transistor low-power high-speed full adder cell.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
63	Hafiz Md. Hasan Babu, Md. Rafiqul Islam 0001, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury	Reversible Logic Synthesis for Minimization of Full-Adder Circuit.	DSD	2003	DBLP DOI BibTeX RDF
63	Hanho Lee, Gerald E. Sobelman	A New Low-Voltage Full Adder Circuit.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
62	Himanshu Thapliyal, M. B. Srinivas	A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
56	Himanshu Thapliyal, A. Prasad Vinod 0001	Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures.	APCCAS	2006	DBLP DOI BibTeX RDF
54	Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet	Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures.	IWANN	2005	DBLP DOI BibTeX RDF
52	Vahid Moalemi, Ali Afzali-Kusha	Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies.	ISVLSI	2007	DBLP DOI BibTeX RDF
52	Massimo Alioto, Gaetano Palumbo	High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
52	Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre	Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.	PATMOS	2004	DBLP DOI BibTeX RDF
52	Mohammed Sayed, Wael M. Badawy	Performance analysis of single-bit full adder cells using 0.18, 0.25, and 0.35 µm CMOS technologies.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
49	P. Balasubramanian 0001, David A. Edwards, Charlie Brej	Self-timed full adder designs based on hybrid input encoding.	DDECS	2009	DBLP DOI BibTeX RDF
49	Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang	A novel hybrid pass logic with static CMOS output drive full-adder cell.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
47	Lihui Ni, Zhijin Guan, Wenying Zhu	A General Method of Constructing the Reversible Full-Adder.	IITSI	2010	DBLP DOI BibTeX RDF	reversible full-adder, reversible gates, gate count, garbage outputs
46	Deepanjan Datta, Samiran Ganguly	Design of Multi-bit SET Adder and Its Fault Simulation.	VLSI Design	2006	DBLP DOI BibTeX RDF
46	Jiajia Chen 0002, Chip-Hong Chang, A. Prasad Vinod 0001	Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics.	APCCAS	2006	DBLP DOI BibTeX RDF
46	Gin Yee, Carl Sechen	Clock-Delayed Domino for Adder and Combinational Logic Desig.	ICCD	1996	DBLP DOI BibTeX RDF
41	Massimo Alioto, Gaetano Palumbo	Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
41	Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga	A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
38	S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
38	Amir Fijany, Farrokh Vatan, Mohammad M. Mojarradi, Nikzad Benny Toomarian, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Pierre Gentil	The G4-FET: a universal and programmable logic gate.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	G4-FET, programmable gate, universal logic gate, full adder
38	Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama	Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition.	ISMVL	2002	DBLP DOI BibTeX RDF	Ferroelectric capacitor, multiple-valued current-mode logic circuit, arithmetic operation, full adder
38	Mallika De, Bhabani P. Sinha	Testing of a parallel ternary multiplier using I2L logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	integrated injection logic, parallel ternary multiplier, I/sup 2/L logic, multivalued I/sup 2/L circuits, input balanced ternary full adder, precarry generator, multivalued current inputs, multivalued current outputs, generated test sets, skew fault, fault diagnosis, logic testing, design for testability, logic design, digital arithmetic, fault location, stuck-at fault, generalized model, adders, adder, multiplying circuits, multivalued logic circuits, test sets, parallel multiplier
38	Fekri Kharbash, Ghulam M. Chaudhry	Reliable Binary Signed Digit Number Adder Design.	ISVLSI	2007	DBLP DOI BibTeX RDF
38	William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski	Quantum logic synthesis by symbolic reachability analysis.	DAC	2004	DBLP DOI BibTeX RDF	model checking, formal verification, quantum computing, satisfiability, reversible logic
38	Mahmoud A. Manzoul	A quaternary complex number CCD adder (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
35	Himanshu Thapliyal, A. Prasad Vinod 0001	Designing Efficient Online Testable Reversible Adders With New Reversible Gate.	ISCAS	2007	DBLP DOI BibTeX RDF
35	Bibhudatta Sahoo 0002, Keshab K. Parhi	A Low Power Correlator for CDMA Wireless Systems.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	low-power, correlator, CDMA, incrementer
35	Bibhudatta Sahoo 0002, Martin Kuhlmann, Keshab K. Parhi	A low-power correlator.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
33	Turgay Temel, Avni Morgül, Nizamettin Aydin	A Novel Signed Higher-Radix Full-Adder Algorithm and Implementation with Current-Mode Multi-Valued Logic Circuits.	DSD	2004	DBLP DOI BibTeX RDF
33	P. Balasubramanian 0001	Asynchronous Ripple Carry Adder based on Area Optimized Early Output Dual-Bit Full Adder.	CoRR	2018	DBLP BibTeX RDF
33	P. Balasubramanian 0001, Nikos E. Mastorakis	An Asynchronous Early Output Full Adder and a Relative-Timed Ripple Carry Adder.	CoRR	2016	DBLP BibTeX RDF
33	P. Balasubramanian 0001, K. Prasad	Early Output Hybrid Input Encoded Asynchronous Full Adder and Relative-Timed Ripple Carry Adder.	CoRR	2016	DBLP BibTeX RDF
33	Manan Mewada, Mazad Zaveri	An input test pattern for characterization of a full-adder and n-bit ripple carry adder.	ICACCI	2016	DBLP DOI BibTeX RDF
33	David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat	Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
32	Jon Alfredsson, Snorre Aunet	Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply.	PATMOS	2007	DBLP DOI BibTeX RDF
32	Luigi Dadda, Marco Macchetti, Jeff Owen	The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512).	DATE	2004	DBLP DOI BibTeX RDF
31	Ricardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro	A low power high performance CMOS voltage-mode quaternary full adder.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
31	Hafiz Md. Hasan Babu, Md. Rafiqul Islam 0001, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury	Synthesis of Full-Adder Circuit Using Reversible Logic.	VLSI Design	2004	DBLP DOI BibTeX RDF
31	Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald 0001, Russell P. Kraft, Bryan S. Goda	A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.	FPGA	2003	DBLP DOI BibTeX RDF
31	Ayman A. Fayed, Magdy A. Bayoumi	Noise-tolerant design and analysis for a low-voltage dynamic full adder cell.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
31	Satoshi Sakaidani, Naoto Miyamoto, Tadahiro Ohmi	Flexible processor based on full-adder/ d-flip-flop merged module.	ASP-DAC	2001	DBLP DOI BibTeX RDF
28	Dilip Kumar Gayen, Arunava Bhattacharyya, Chinmoy Taraphdar, Rajat Kumar Pal, Jitendra Nath Roy	All-Optical Binary-Coded Decimal Adder with a Terahertz Optical Asymmetric Demultiplexer.	Comput. Sci. Eng.	2011	DBLP DOI BibTeX RDF	Terahertz optical asymmetric demultiplexer, optical full adder, optical binary-coded decimal adder, optical switch
28	Shinji Nakamura, Kai-Yu Chu	A Single Chip Parallel Multiplier by MOS Technology.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	single chip parallel multiplier, MOS technology, five-counter cell, logic design level, full adder cell design, logic design, integrated logic circuits, multiplying circuits, design optimization, field effect integrated circuits
28	Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis	Efficient Modular Design of TSC Checkers for M-out-of-2M Codes.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	half-adder, VLSI MOS implementation, logic design, trees, codes, codes, adders, modular design, totally self-checking checkers, full-adder
28	J. A. Bate, Jon C. Muzio	Three Cell Structures for Ternary Cellular Arrays.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	combinational switching functions, ternary full adder, universal arrays, Cellular arrays, symmetric functions, ternary logic
28	John A. Gibson, R. W. Gibbard	Synthesis and Comparison of Two's Complement Parallel Multipliers.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Algorithm syntheses, full adder arrays, multiplier comparisons, parallel binary multiplication, two's complement formulation
27	R. Mahesh 0001, A. Prasad Vinod 0001	An Architecture For Integrating Low Complexity and Reconfigurability for Channel filters in Software Defined Radio Receivers.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Ismo Hänninen, Jarmo Takala	Robust Adders Based on Quantum-Dot Cellular Automata.	ASAP	2007	DBLP DOI BibTeX RDF
27	Massimo Alioto, Gaetano Palumbo	Delay uncertainty due to supply variations in static and dynamic full adders.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis	The circuit design of multiple-valued logic voltage-mode adders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
27	Christian Pacha, Uwe Auer, Christian Burwick, Peter Glösekötter, Andreas Brennemann, Werner Prost, Franz-Josef Tegude, Karl F. Goser	Threshold logic circuit design of parallel adders using resonant tunneling devices.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
27	Miriam Leeser	Reasoning about the function and timing of integrated circuits with interval temporal logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
26	Sriram Sundar S, Mahendran G	CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications.	Integr.	2024	DBLP DOI BibTeX RDF
26	Shahbaz Hussain, Mehedi Hasan, Gazal Agrawal, Mohd. Hasan	A high-performance full swing 1-bit hybrid full adder cell.	IET Circuits Devices Syst.	2022	DBLP DOI BibTeX RDF
26	Mostafa Sadeghi, Keivan Navi, Mehdi Dolatshahi	Novel efficient full adder and full subtractor designs in quantum cellular automata.	J. Supercomput.	2020	DBLP DOI BibTeX RDF
26	Mohammad-Ali Asadi, Mohammad Mosleh, Majid Haghparast	An efficient design of reversible ternary full-adder/full-subtractor with low quantum cost.	Quantum Inf. Process.	2020	DBLP DOI BibTeX RDF
26	Yanfeng Wang, Xing Li, Chun Huang, Guangzhao Cui, Junwei Sun	One-Bit Full Adder-Full Subtractor Logical Operation Based on DNA Strand Displacement.	BIC-TA (1)	2016	DBLP DOI BibTeX RDF
26	A. V. AnanthaLakshmi, G. Florence Sudha	Design of a Novel Reversible Full Adder and Reversible Full Subtractor.	ACITY (3)	2012	DBLP DOI BibTeX RDF
24	Ahmed M. Shams, Magdy A. Bayoumi	Performance evaluation of 1-bit CMOS adder cells.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
21	Hamed F. Dadgour, Muhammad Mustafa Hussain, Kaustav Banerjee	A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs.	ISLPED	2010	DBLP DOI BibTeX RDF	Boolean logic minimization, energy-efficient electronics, laterally-actuated NEMS, nanoelectromechanical switches, XOR gates
21	Faizal Karim, Marco Ottavi, Hamidreza Hashempour, Vamsi Vankamamidi, Konrad Walus, André Ivanov, Fabrizio Lombardi	Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.	J. Electron. Test.	2009	DBLP DOI BibTeX RDF	Quantum-dot cellular automata (QCA), Clocked QCA, Emerging nanotechnologies, Phase shift
21	Shai Erez, Guy Even	An improved micro-architecture for function approximation using piecewise quadratic interpolation.	ICCD	2008	DBLP DOI BibTeX RDF
21	Jon Alfredsson, Snorre Aunet, Bengt Oelmann	Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure.	VLSI Design	2007	DBLP DOI BibTeX RDF
21	Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara	Folding of logic functions and its application to look up table compaction.	ICCAD	2002	DBLP DOI BibTeX RDF
21	Kiwon Choi, Minkyu Song	Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
20	R. Nishanth, C. Helen Sulochana	A novel lightweight CNN-based error-reduced carry prediction approximate full adder design for multimedia applications.	Neural Comput. Appl.	2024	DBLP DOI BibTeX RDF
20	Samane Asgari, Mohammad Reza Reshadinezhad, Seyed Erfan Fatemieh	Energy-efficient and fast IMPLY-based approximate full adder applying NAND gates for image processing.	Comput. Electr. Eng.	2024	DBLP DOI BibTeX RDF
20	S. Lakshmanachari, Sadulla Shaik, G. S. R. Satyanarayana, Inapudi Vasavi, Vallabhuni Vijay, Chandra Shaker Pittala	1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages.	Int. J. Syst. Assur. Eng. Manag.	2024	DBLP DOI BibTeX RDF
20	Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri	High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures.	IEEE Embed. Syst. Lett.	2023	DBLP DOI BibTeX RDF
20	Jie Xu 0019, Gensheng Hu, Dingjun Qian	A quantum-based building block for designing a nanoscale full adder circuit with power analysis.	Integr.	2023	DBLP DOI BibTeX RDF
20	Sueyeon Kim, Insoo Choi, Sangki Cho, Myounggon Kang, Seungjae Baik, Changho Ra, Jongwook Jeon	Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET).	IEEE Access	2023	DBLP DOI BibTeX RDF
20	Vineet Jaiswal, Trailokya Nath Sasamal	Novel approach for the design of efficient full adder in MQCA.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
20	T. Nirmalraj, S. K. Pandiyan, Rakesh Kumar Karan, R. Sivaraman 0001, Rengarajan Amirtharajan	Design of Low-Power 10-Transistor Full Adder Using GDI Technique for Energy-Efficient Arithmetic Applications.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
20	Mina Raouf, Somayeh Timarchi	Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
20	Xing Jin, Weichong Chen, Ximing Li 0003, Ningyuan Yin, Caihua Wan, Mingkun Zhao, Xiufeng Han, Zhiyi Yu	High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
20	Forouzan Bahrami, Nabiollah Shiri, Farshad Pesaran	Imprecise Subtractor Using a New Efficient Approximate-Based Gate Diffusion Input Full Adder for Bioimages Processing.	Comput. Electr. Eng.	2023	DBLP DOI BibTeX RDF
20	A. Venkatesan, P. T. Vanathi, M. Elangovan	Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7 nm FINFET Technology for MIMO Applications.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
20	A. Venkatesan, P. T. Vanathi, M. Elangovan	Erratum: Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7nm FINFET Technology for MIMO Applications.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
20	Elham Esmaeili, Farshad Pesaran, Nabiollah Shiri	A high-efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
20	Ayush Kanojia, Sachin Agrawal, Rohit Lorenzo	Comprehensive Analysis of a Power-Efficient 1-Bit Hybrid Full Adder Cell.	Wirel. Pers. Commun.	2023	DBLP DOI BibTeX RDF
20	Seyedeh Fatemeh Deymad, Nabiollah Shiri, Farshad Pesaran	High-efficient reversible full adder realized by dynamic threshold-based gate diffusion input logics.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
20	Behrouz Safaiezadeh, Majid Haghparast, Lauri Kettunen	Novel Efficient Scalable QCA XOR and Full Adder Designs.	CoRR	2023	DBLP DOI BibTeX RDF
20	Sangyeob Kim, Hoi-Jun Yoo	C-DNN V2: Complementary Deep-Neural-Network Processor With Full-Adder/OR-Based Reduction Tree and Reconfigurable Spatial Weight Reuse.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2023	DBLP DOI BibTeX RDF
20	Farzad Mozafari, Majid Ahmadi, Arash Ahmadi	Design and Implementation of Full Adder Circuit Based on VTM-Logic Gates.	MWSCAS	2023	DBLP DOI BibTeX RDF
20	Zhouchao Gan, Dongdong Zhang, Yinghao Ma, Chenyu Zhang, Xiangshui Miao, Xingsheng Wang	Invited Paper: A Memristor-Based Stateful Majority-Inverter Graph Logic and 1-Bit Full Adder for In-Memory Computing Systems.	ICTA	2023	DBLP DOI BibTeX RDF
20	Parisa Rahimi, Myasar R. Tabany, Seyedali Pourmoafi	A Novel Low Power and High Speed 9- Transistors Dynamic Full-Adder Cell Simulation and Design.	ISCC	2023	DBLP DOI BibTeX RDF
20	B. Ravi Kumar, P. Munaswamy, B. Chandrababu Naik, K. Swetha	Implementation of Low Power and High Speed Dadda Multiplier using Xor-Xnor cell Based Hybrid Logic Full Adder.	ICCCNT	2023	DBLP DOI BibTeX RDF
20	S. Nagaleela, G. Shanthi, Boppa Manisha, Palle Bharath, Erram Praneeth	Design of DADDA Multiplier Using High Performance and Low Power Full Adder.	ICCCNT	2023	DBLP DOI BibTeX RDF
20	M. Rajmohan, N. Venkata Subbaiah, P. Sanath Kumar Reddy	Performance analysis of 8×8 Truncated Multiplier using 1-bit Hybrid Full Adder.	ICCCNT	2023	DBLP DOI BibTeX RDF
20	Naheem Olakunle Adesina, Md Azmot Ullah Khan, Jian Xu	Design of Energy Efficient Ring Oscillator and Full Adder Circuit using Compact Model of MoS2 Channel TFET.	CCWC	2023	DBLP DOI BibTeX RDF