Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
132 | Ki-Seok Chung, Taewhan Kim, C. L. Liu 0001 |
G-vector: A New Model for Glitch Analysis in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 27(3), pp. 235-251, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
synthesis, power estimation, logic circuits, glitches |
104 | Wieland Fischer, Berndt M. Gammel |
Masking at Gate Level in the Presence of Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 187-200, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
random masking, masked logic circuits, Cryptanalysis, side-channel attacks, DPA, power analysis, logic circuits, digital circuits, masking, glitches |
80 | Stefan Mangard, Kai Schramm |
Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 76-90, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Zero-Offset DPA, Zero-Input DPA, Delay Chains, AES, DPA, Masking, Glitches |
78 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Register transfer level power optimization with emphasis on glitch analysis and reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8), pp. 1114-1131, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
78 | Svetla Nikova, Vincent Rijmen, Martin Schläffer |
Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2008, 11th International Conference, Seoul, Korea, December 3-5, 2008, Revised Selected Papers, pp. 218-234, 2008, Springer, 978-3-642-00729-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
non-linear functions, Noekeon, DPA, sharing, S-box, masking, glitches |
76 | Xun Liu, Marios C. Papaefthymiou |
Incorporation of input glitches into power macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 846-849, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
63 | Quang Dinh, Deming Chen, Martin D. F. Wong |
A routing approach to reduce glitches in low power FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 99-106, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
glitch reduction, path balancing, fpgas, routing, low power |
50 | Lei Cheng 0001, Deming Chen, Martin D. F. Wong |
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 318-323, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
50 | Svetla Nikova, Christian Rechberger, Vincent Rijmen |
Threshold Implementations Against Side-Channel Attacks and Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICS ![In: Information and Communications Security, 8th International Conference, ICICS 2006, Raleigh, NC, USA, December 4-7, 2006, Proceedings, pp. 529-545, 2006, Springer, 3-540-49496-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
side-channel attacks, secret sharing, Masking |
41 | Katherine Shu-Min Li, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen |
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(4), pp. 341-355, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
oscillation ring (OR) test scheme, open faults, crosstalk glitches, IEEE P1500, wrapper cell design, stuck-at faults, delay faults, SOC testing, interconnect test |
39 | Zhimin Chen 0002, Syed Haider, Patrick Schaumont |
Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISA ![In: Advances in Information Security and Assurance, Third International Conference and Workshops, ISA 2009, Seoul, Korea, June 25-27, 2009. Proceedings, pp. 327-336, 2009, Springer, 978-3-642-02616-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton |
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(11), pp. 1521-1534, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Tomasz S. Czajkowski, Stephen Dean Brown |
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 324-329, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara |
Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 120-130, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Stefan Mangard, Thomas Popp, Berndt M. Gammel |
Side-Channel Leakage of Masked CMOS Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2005, The Cryptographers' Track at the RSA Conference 2005, San Francisco, CA, USA, February 14-18, 2005, Proceedings, pp. 351-365, 2005, Springer, 3-540-24399-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Michele Favalli |
"Victim Gate" Crosstalk Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 191-199, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
High-level macro-modeling and estimation techniques for switching activity and power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(4), pp. 538-557, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Glitch power minimization by selective gate freezing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(3), pp. 287-298, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 830-836, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Benoit Catteau, Pieter Rombouts, Ludo Weyten |
A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1477-1480, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Ricardo Ferreira, Anne-Marie Trullemans, José C. Costa, José Monteiro 0001 |
Probabilistic Bottom-Up RTL Power Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 439-, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Register Tranfers Level, Power Estimation, Glitches, ZBDD |
26 | Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di |
Glitch-free design for multi-threshold CMOS NCL circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 215-220, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
asynchronous circuit, mtcmos, glitch, threshold gate, null convention logic |
26 | Denis Réal, Cécile Canovas, Jessy Clédière, M'hamed Drissi, Frédéric Valette |
Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1274-1279, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal |
Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(11), pp. 1245-1255, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton |
GlitchLess: an active glitch minimization technique for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 156-165, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays, power minimization |
26 | Hanif Fatemi, Shahin Nazarian, Massoud Pedram |
A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 774-779, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Kathi Fisler |
Two-Dimensional Regular Expressions for Compositional Bus Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 7th International Conference, FMCAD 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings, pp. 154-157, 2007, IEEE Computer Society, 0-7695-3023-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Natasa Miskov-Zivanov, Diana Marculescu |
Circuit Reliability Analysis Using Symbolic Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2638-2649, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Fei Hu, Vishwani D. Agrawal |
Input-specific dynamic power optimization for VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 232-237, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dynamic power optimization, glitch reduction, input specific |
26 | Zhimin Chen, Yujie Zhou |
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 242-254, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA |
26 | Natasa Miskov-Zivanov, Diana Marculescu |
MARS-C: modeling and reduction of soft errors in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 767-772, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
reliability symbolic techniques, SER |
26 | Fei Hu, Vishwani D. Agrawal |
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 366-372, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Alex Gyure, Alireza Kasnavi, Sam C. Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zejda |
Noise Library Characterization for Large Capacity Static Noise Analysis Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 28-34, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald |
Successfully Attacking Masked AES Hardware Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 157-171, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis |
A Static Low-Power, High-Performance 32-bit Carry Skip Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 615-619, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Katherine Shu-Min Li, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen |
A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 145-150, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis |
A Low-Power Carry Skip Adder with Fast Saturation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 269-279, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia 0001 |
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 353-362, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Henrik Eriksson, Per Larsson-Edefors |
Impact of Voltage Scaling on Glitch Power Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 139-148, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Glitch Power Minimization by Gate Freezing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 163-167, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis |
Robust Sequential Fault Testing of Iterative Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 238-244, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays |
26 | Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya |
CMOS Stuck-open Fault Detection Using Single Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 714-717, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
24 | Bingbin Liu, Jordan T. Ash, Surbhi Goel, Akshay Krishnamurthy, Cyril Zhang |
Exposing Attention Glitches with Flip-Flop Language Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2306.00946, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Elena Simona Apostol, Ciprian-Octavian Truica |
Efficient Machine Learning Ensemble Methods for Detecting Gravitational Wave Glitches in LIGO Time Series. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2311.02106, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Tiago S. Fernandes, Samuel J. Vieira, António Onofre, Juan Calderón Bustillo, Alejandro Torres-Forné, José A. Font |
Convolutional Neural Networks for the classification of glitches in gravitational-wave data streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2303.13917, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Mohammad Reza Taesiri, Tianjun Feng, Cor-Paul Bezemer, Anh Nguyen 0002 |
GlitchBench: Can large multimodal models detect video game glitches? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2312.05291, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Ahmad Faza, John Leth, Arnfinn Aas Eielsen |
Criterion for Sufficiently Large Dither Amplitude to Mitigate Non-linear Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCTA ![In: IEEE Conference on Control Technology and Applications, CCTA 2023, Bridgetown, Barbados, August 16-18, 2023, pp. 970-977, 2023, IEEE, 979-8-3503-3544-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Ahmad Faza, John Leth, Arnfinn Aas Eielsen |
Mitigating Non-linear DAC Glitches Using Dither in Closed-loop Nano-positioning Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACC ![In: American Control Conference, ACC 2023, San Diego, CA, USA, May 31 - June 2, 2023, pp. 685-691, 2023, IEEE, 979-8-3503-2806-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Stanislav Lyakhov, Vincent Immler |
Analysis of Arbitrary Waveform Generation for Voltage Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDTC ![In: Workshop on Fault Detection and Tolerance in Cryptography, FDTC 2023, Prague, Czech Republic, September 10, 2023, pp. 36-47, 2023, IEEE, 979-8-3503-4252-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Bingbin Liu, Jordan T. Ash, Surbhi Goel, Akshay Krishnamurthy, Cyril Zhang |
Exposing Attention Glitches with Flip-Flop Language Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NeurIPS ![In: Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, NeurIPS 2023, New Orleans, LA, USA, December 10 - 16, 2023., 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
24 | Elena Simona Apostol, Ciprian-Octavian Truica |
Efficient Machine Learning Ensemble Methods for Detecting Gravitational Wave Glitches in LIGO Time Series. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCP ![In: 19th IEEE International Conference on Intelligent Computer Communication and Processing, ICCP 2023, Cluj-Napoca, Romania, October 26-28, 2023, pp. 79-86, 2023, IEEE, 979-8-3503-7035-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Sivaramakrishnan Sankarapandian, Brian Kulis |
$β$-Annealed Variational Autoencoder for glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2107.10667, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
24 | Oscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek |
A digital switching scheme to reduce DAC glitches using code-dependent randomization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NorCAS ![In: IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, Norway, October 26-27, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-0712-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Yanbin Li, Ming Tang 0002, Yuguang Li, Huanguo Zhang |
A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 70, pp. 60-69, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Shlomo Engelberg, Osnat Keren |
Constructive Bounds on the Capacity of Parallel Asynchronous Skew-Free Channels With Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 66(7), pp. 4026-4037, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Arnfinn Aas Eielsen, John Leth, Andrew J. Fleming, Adrian G. Wills, Brett Ninness |
Large-Amplitude Dithering Mitigates Glitches in Digital-to-Analogue Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 68, pp. 1950-1963, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Vittorio Zaccaria |
An F-algebra for analysing information leaks in the presence of glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2020, pp. 681, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
24 | Corey Brian Jackson, Carsten S. Østerlund, Kevin Crowston, Mahboobeh Harandi, Sarah Allen, Sara Bahaadini, Scotty Coughlin, Vicky Kalogera, Aggelos K. Katsaggelos, Shane L. Larson, Neda Rohani, Joshua R. Smith 0003, Laura Trouille, Michael Zevin |
Teaching citizen scientists to categorize glitches using machine learning guided training. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Hum. Behav. ![In: Comput. Hum. Behav. 105, pp. 106198, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Tadahiro Nishiguchi |
Transcriptional Characteristics of Quadrant Glitches on Machined Surface - Influence of Tool Diameter and Feed Rate -. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Autom. Technol. ![In: Int. J. Autom. Technol. 14(5), pp. 801-807, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Carlos García Ling, Konrad Tollmar, Linus Gisslén |
Using Deep Convolutional Neural Networks to Detect Rendered Glitches in Video Games. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AIIDE ![In: Proceedings of the Sixteenth AAAI Conference on Artificial Intelligence and Interactive Digital Entertainment, AIIDE 2020, virtual, October 19-23, 2020, pp. 66-73, 2020, AAAI Press, 978-1-57735-849-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
24 | Stefano Gualeni |
On the de-familiarizing and re-ontologizing effects of glitches and glitch-alikes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DiGRA Conference ![In: Proceedings of the 2019 DiGRA International Conference: Game, Play and the Emerging Ludo-Mix, DiGRA 2019, Kyoto, Japan, August 6-10, 2019, 2019, Digital Games Research Association. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
24 | Raphael Kim, Roland van Dierendonck, Stefan Poslad |
Moldy Ghosts and Yeasty Invasions: Glitches in Hybrid Bio-Digital Games. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI Extended Abstracts ![In: Extended Abstracts of the 2019 CHI Conference on Human Factors in Computing Systems, CHI 2019, Glasgow, Scotland, UK, May 04-09, 2019., 2019, ACM, 978-1-4503-5971-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Antti Tenhiälä, Manus Johnny Rungtusanatham, Jason W. Miller |
ERP System versus Stand-Alone Enterprise Applications in the Mitigation of Operational Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Decis. Sci. ![In: Decis. Sci. 49(3), pp. 407-444, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Rafael Nogueras, Carlos Cotta |
Analyzing Resilience to Computational Glitches in Island-Based Evolutionary Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPSN (1) ![In: Parallel Problem Solving from Nature - PPSN XV - 15th International Conference, Coimbra, Portugal, September 8-12, 2018, Proceedings, Part I, pp. 411-423, 2018, Springer, 978-3-319-99252-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Roderick Bloem, Hannes Groß, Rinat Iusupov, Bettina Könighofer, Stefan Mangard, Johannes Winter |
Formal Verification of Masked Hardware Implementations in the Presence of Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT (2) ![In: Advances in Cryptology - EUROCRYPT 2018 - 37th Annual International Conference on the Theory and Applications of Cryptographic Techniques, Tel Aviv, Israel, April 29 - May 3, 2018 Proceedings, Part II, pp. 321-353, 2018, Springer, 978-3-319-78374-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Roderick Bloem, Hannes Groß, Rinat Iusupov, Bettina Könighofer, Stefan Mangard, Johannes Winter |
Formal Verification of Masked Hardware Implementations in the Presence of Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2017, pp. 897, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
24 | Michael Meixner, Tobias G. Noll |
Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 64-II(7), pp. 787-791, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Jungwoo Joh, Yezee Seo, Hoon-Kyu Kim, Taekyoung Kwon 0002 |
Glitch Recall: A Hardware Trojan Exploiting Natural Glitches in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISA ![In: Information Security Applications - 18th International Conference, WISA 2017, Jeju Island, Korea, August 24-26, 2017, Revised Selected Papers, pp. 150-161, 2017, Springer, 978-3-319-93562-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Shlomo Engelberg, Osnat Keren |
Reliable Communication Across Parallel Asynchronous Channels with Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMCTA ![In: Coding Theory and Applications - 5th International Castle Meeting, ICMCTA 2017, Vihula, Estonia, August 28-31, 2017, Proceedings, pp. 93-106, 2017, Springer, 978-3-319-66277-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Ciro D'Urso |
EXPERIENCE: Glitches in Databases, How to Ensure Data Quality by Outlier Detection Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Data Inf. Qual. ![In: ACM J. Data Inf. Qual. 7(3), pp. 14:1-14:22, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Herwig Wendt, Nicolas Dobigeon, Jean-Yves Tourneret, Mathieu Albinet, Christophe Goldstein, Nadia Karouche |
Detection and Correction of Glitches in a Multiplexed Multichannel Data Stream - Application to the MADRAS Instrument. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Geosci. Remote. Sens. ![In: IEEE Trans. Geosci. Remote. Sens. 54(5), pp. 2803-2811, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath |
Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 13(10), pp. 20160328, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Charlotte A. L. Haley |
Mathematical physics: Glitches in time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nat. ![In: Nat. 532(7600), pp. 450-451, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Yan Peng, Ian W. Jones, Mark R. Greenstreet |
Finding Glitches Using Formal Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016, Porto Alegre, Brazil, May 8-11, 2016, pp. 45-46, 2016, IEEE Computer Society, 978-1-4673-9007-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Laure Berti-Équille, Ji Meng Loh, Tamraparni Dasu |
A masking index for quantifying hidden glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Knowl. Inf. Syst. ![In: Knowl. Inf. Syst. 44(2), pp. 253-277, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Honorio Martín, Thomas Korak, Enrique San Millán, Michael Hutter |
Fault Attacks on STRNGs: Impact of Glitches, Temperature, and Underpowering on Randomness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Forensics Secur. ![In: IEEE Trans. Inf. Forensics Secur. 10(2), pp. 266-277, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Stephen Longfield Jr., Brittany Nkounkou, Rajit Manohar, Ross Tate |
Preventing glitches and short circuits in high-level self-timed chip specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation, Portland, OR, USA, June 15-17, 2015, pp. 270-279, 2015, ACM, 978-1-4503-3468-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Bruno Robisson |
Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2014, Arlington, VA, USA, May 6-7, 2014, pp. 130-135, 2014, IEEE Computer Society, 978-1-4799-4114-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Michael Meixner, Tobias G. Noll |
Limits of gate-level power estimation considering real delay effects and glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSoC ![In: 2014 International Symposium on System-on-Chip, SoC 2014, Tampere, Finland, October 28-29, 2014, pp. 1-7, 2014, IEEE, 978-1-4799-6890-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Ji Meng Loh, Tamraparni Dasu |
Auditing data streams for correlated glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Inf. Qual. ![In: Int. J. Inf. Qual. 3(2), pp. 85-106, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Tamraparni Dasu |
Data Glitches: Monsters in Your Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Handbook of Data Quality ![In: Handbook of Data Quality, Research and Practice., pp. 163-178, 2013, Springer, 978-3-642-36256-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Laure Berti-Équille, Ji Meng Loh, Tamraparni Dasu |
A Masking Index for Quantifying Hidden Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDM ![In: 2013 IEEE 13th International Conference on Data Mining, Dallas, TX, USA, December 7-10, 2013, pp. 21-30, 2013, IEEE Computer Society, 978-0-7695-5108-1. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Koichi Shimizu, Daisuke Suzuki, Tomomi Kasuya |
Glitch PUF: Extracting Information from Usually Unwanted Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(1), pp. 223-233, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Ryuta Sato |
Generation Mechanism of Quadrant Glitches and Compensation for it in Feed Drive Systems of NC Machine Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Autom. Technol. ![In: Int. J. Autom. Technol. 6(2), pp. 154-162, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Svetla Nikova, Vincent Rijmen, Martin Schläffer |
Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Cryptol. ![In: J. Cryptol. 24(2), pp. 292-321, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Emmanuel Prouff, Thomas Roche |
Higher-Order Glitches Free Implementation of the AES using Secure Multi-Party Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2011, pp. 413, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
24 | Ji Meng Loh, Tamraparni Dasu |
Auditing data streams for correlated glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIQ ![In: Proceedings of the 16th International Conference on Information Quality, ICIQ 2011, Adelaide, Australia, November 18-20, 2011., 2011, MIT Information Quality Program, 978-1-61839-337-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
24 | Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede |
An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDTC ![In: 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2011, Tokyo, Japan, September 29, 2011, pp. 105-114, 2011, IEEE Computer Society, 978-1-4577-1463-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Emmanuel Prouff, Thomas Roche |
Higher-Order Glitches Free Implementation of the AES Using Secure Multi-party Computation Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28 - October 1, 2011. Proceedings, pp. 63-78, 2011, Springer, 978-3-642-23950-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Da-Cheng Juan, Yu-Ting Chen, Ming-Chao Lee, Shih-Chieh Chang |
An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(2), pp. 246-255, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Quang Dinh, Deming Chen, Martin D. F. Wong |
A Routing Approach to Reduce Glitches in Low Power FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2), pp. 235-240, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Xenophon Koufteros, Greg Rawski, Rupak Rauniar |
Organizational Integration for Product Development: The Effects on Glitches, On-Time Execution of Engineering Change Orders, and Market Success. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Decis. Sci. ![In: Decis. Sci. 41(1), pp. 49-80, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier |
Fault diagnosis of crosstalk induced glitches and delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010, pp. 358-363, 2010, IEEE Computer Society, 978-1-4244-6612-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier |
Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 345-350, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Switching Windows, Test Set Compaction, Automatic Test Pattern Generation, Crosstalk Faults |
24 | Monjur Alam, Santosh Ghosh, M. J. Mohan, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta 0001 |
Effect of glitches against masked AES S-box implementation and countermeasure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Inf. Secur. ![In: IET Inf. Secur. 3(1), pp. 34-44, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Jins D. Alexander, Vishwani D. Agrawal |
Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 13-15 May 2009, Tampa, Florida, USA, pp. 127-132, 2009, IEEE Computer Society, 978-0-7695-3684-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad Taghi Manzuri Shalmani |
On the Importance of the Number of Fanouts to Prevent the Glitches in DPA-Resistant Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSICC ![In: Advances in Computer Science and Engineering - 13th International CSI Computer Conference, CSICC 2008, Kish Island, Iran, March 9-11, 2008 Revised Selected Papers, pp. 661-670, 2008, 978-3-540-89984-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Cheng Chia Lo |
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1265-1270, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Minjin Zhang, Xiaowei Li 0001 |
Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 16th Asian Test Symposium, ATS 2007, Beijing, China, October 8-11, 2007, pp. 259-264, 2007, IEEE, 0-7695-2890-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang |
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 779-782, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|