Search results for "iDDT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
248	Abhishek Singh 0001, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel	Defect Simulation Methodology for iDDT Testing.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	iDDT, transient current testing, device testing, ATPG, fault simulation, IDDQ, defect simulation, defect-based test
136	Ali Chehab, Saurabh Patel, Rafic Z. Makki	Scaling of iDDT Test Methods for Random Logic Circuits.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	dynamic power supply current, design for current testability, resistive opens, resistive bridges, very deep sub-micron technologies, VDSM, fault simulation
121	Yinghua Min, Zhongcheng Li	IDDT Testing versus IDDQ Testing.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	IDDT test, IDDQ test, stuck-open fault, Boolean process
121	Yinghua Min, Zhuxing Zhao, Zhongcheng Li	IDDT Testing.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	IDDT test, IDDQ test, stuck-open fault, Boolean process
115	Ali Chehab, Rafic Z. Makki, Michael Spica, David Wu	IDDT Test Methodologies for Very Deep Sub-micron CMOS Circuits.	DELTA	2002	DBLP DOI BibTeX RDF
100	Chuen-Song Chen, Jien-Chung Lo, Tian Xia	An indirect current sensing technique for IDDQ and IDDT tests.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	IDDT, IDDQ, current testing, BICS
100	Jishun Kuang, Yu Wang, Xiaofen Wei, Changnian Zhang	IDDT ATPG Based on Ambiguous Delay Assignments.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	IDDT testing, delay Assignments, stuck-open fault
64	Manoj Sachdev, Peter Janssen, Victor Zieren	Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs.	ITC	1998	DBLP DOI BibTeX RDF
52	Josep Rius 0001, Joan Figueras	Exploring the Combination of IDDQ and iDDt Testing: Energy Testing.	DATE	1999	DBLP DOI BibTeX RDF
49	Sagar S. Sabade, D. M. H. Walker	IDDX-based test methods: A survey.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	IDDT test, test, VLSI testing, IDDQ
42	Scott Thomas, Rafic Z. Makki, Sai Kishore Vavilala	Measurement and Analysis of Physical Defects for Dynamic Supply Current Testing.	DELTA	2004	DBLP DOI BibTeX RDF
30	Hanaa ZainEldin, Mahmoud Badawy 0001, Mostafa A. El-Hosseini, Hesham Arafat, Ajith Abraham	An improved dynamic deployment technique based-on genetic algorithm (IDDT-GA) for maximizing coverage in wireless sensor networks.	J. Ambient Intell. Humaniz. Comput.	2020	DBLP DOI BibTeX RDF
30	Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu	Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs.	ATS	2017	DBLP DOI BibTeX RDF
30	Radi Husin Bin Ramlee, Mark Zwolinski	Using Iddt current degradation to monitor ageing in CMOS circuits.	PATMOS	2016	DBLP DOI BibTeX RDF
30	Yong Zhao, Hans G. Kerkhoff	Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor.	DSD	2015	DBLP DOI BibTeX RDF
30	Gábor Gyepes, Viera Stopjaková, Daniel Arbet, Libor Majer, Juraj Brenkus	A new IDDT test approach and its efficiency in covering resistive opens in SRAM arrays.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
30	Gábor Gyepes, Daniel Arbet, Juraj Brenkus, Viera Stopjaková	Application of IDDT test towards increasing SRAM reliability in nanometer technologies.	DDECS	2012	DBLP DOI BibTeX RDF
30	Gábor Gyepes, Juraj Brenkus, Daniel Arbet, Viera Stopjaková	Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies.	DDECS	2011	DBLP DOI BibTeX RDF
30	Layla Hamieh, Nader Mehdi, Ghazalah Omeirat, Ali Chehab, Ayman I. Kayssi	The effectiveness of delay and IDDT tests in detecting resistive open defects for nanometer CMOS adder circuits.	IDT	2011	DBLP DOI BibTeX RDF
30	Jishun Kuang, Zhiqiang Yang, Qijian Zhu, Yinghua Min	IDDT: Fundamentals and Test Generation.	J. Comput. Sci. Technol.	2003	DBLP DOI BibTeX RDF
30	Suriya Ashok Kumar, Rafic Z. Makki, David M. Binkley	IDDT Testing of Embedded CMOS SRAMs.	DATE	2002	DBLP DOI BibTeX RDF
30	Shih-Yu Yang, Christos A. Papachristou, Massood Tabib-Azar	Improving Bus Test Via IDDT and Boundary Scan.	DAC	2001	DBLP DOI BibTeX RDF
30	Javier Argüelles, María José López, J. Blanco, Mar Martínez, Salvador Bracho	Iddt testing of continuous-time filters.	VTS	1995	DBLP DOI BibTeX RDF	continuous time filters, continuous-time filters, design-for-test methodology, dynamic supply current consumption, dynamic current, partitioning methodology, test reliability, built-in self test, integrated circuit testing, design for testability, automatic testing, CMOS, automatic test equipment, built-in current sensor, CMOS analogue integrated circuits
21	Yolanda Lechuga, Román Mozuelos, Mar Martínez, Salvador Bracho	Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics.	DATE	2002	DBLP DOI BibTeX RDF
21	Abhishek Singh 0001, Jim Plusquellic, Anne E. Gattiker	Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models.	VTS	2002	DBLP DOI BibTeX RDF
21	Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos	A Versatile Built-In Self-Test Scheme for Delay Fault Testing.	DATE	2000	DBLP DOI BibTeX RDF