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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 65 occurrences of 52 keywords
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Results
Found 308 publication records. Showing 308 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
83 | Hyun Woo Choi, Abhijit Chatterjee |
Digital bit stream jitter testing using jitter expansion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1468-1473, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
76 | Isaac Keslassy, Murali S. Kodialam, T. V. Lakshman, Dimitrios Stiliadis |
On guaranteed smooth scheduling for input-queued switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 13(6), pp. 1364-1375, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, router, switch, jitter |
68 | T. H. Szymanski |
A Conflict-Free Low-Jitter Guaranteed-Rate MAC Protocol for Base-Station Communications in Wireless Mesh Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AccessNets ![In: AccessNets, Third International Conference on Access Networks, AccessNets 2008, Las Vegas, NV, USA, October 15-17, 2008. Revised Papers, pp. 118-137, 2008, Springer, 978-3-642-04647-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low jitter, scheduling, quality of service, networks, mesh, multihop |
60 | Shalabh Goyal, Abhijit Chatterjee, Mike Atia |
Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 165-172, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
57 | David Hay, Gabriel Scalosub |
Jitter Regulation for Multiple Streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Algorithms - ESA 2005, 13th Annual European Symposium, Palma de Mallorca, Spain, October 3-6, 2005, Proceedings, pp. 496-507, 2005, Springer, 3-540-29118-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | David C. Keezer, Dany Minier, Patrice Ducharme |
Method for reducing jitter in multi-gigahertz ATE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 701-706, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Takashi Kawamoto, Masaru Kokubo |
A low-jitter 1.5-GHz and large-EMI reduction 10-dBm spread-spectrum clock generator for Serial-ATA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 696-701, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
45 | Tony Pialis, Eric W. Hu, Khoman Phang |
A 1.8V low-jitter CMOS ring oscillator with supply regulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2791-2794, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu |
34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1255-1262, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Adrian Maxim, Baker Scott, Ed Schneider, Melvin Hagge, Steve Chacko, Dan Stiurca |
Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 766-769, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
36 | Zvika Brakerski, Boaz Patt-Shamir |
Jitter-approximation tradeoff for periodic scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Networks ![In: Wirel. Networks 12(6), pp. 723-731, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Jitter minimization, Perfect periodicity, Asymmetric communication, Periodic scheduling |
36 | Zvika Brakerski, Boaz Patt-Shamir |
Jitter-Approximation Tradeoff for Periodic Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Alfio Zanchi, Ioannis Papantonopoulos, Frank (Ching-Yuh) Tsay |
Measurement and SPICE prediction of sub-picosecond clock jitter in A/D converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 557-560, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Tingzhou Yang, Zhao Chen, Dimitrios Makrakis, Abdelhakim Hafid |
A Study of AF and EF Services Interaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICOIN ![In: The 15th International Conference on Information Networking, ICOIN 2001, Beppu City, Oita, Japan, January 31 - February 2, 2001, pp. 495-502, 2001, IEEE Computer Society, 0-7695-0951-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Abdelohahab Djemouai, Mohamad Sawan |
Fast-locking low-jitter integrated CMOS phase-locked loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 264-267, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Yu Duan, Chi-Hang Chan, Yan Zhu 0001, Rui Paulo Martins |
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(12), pp. 4799-4809, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
28 | Dongjun Park, Jongsun Kim |
A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 17(19), pp. 20200296, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Haw-Yun Shin, Jean-Lien C. Wu, Yi-Hsien Wu |
A Packet Scheduling Scheme for Broadband Wireless Networks with Heterogeneous Services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA (2) ![In: 18th International Conference on Advanced Information Networking and Applications (AINA 2004), 29-31 March 2004, Fukuoka, Japan, pp. 355-359, 2004, IEEE Computer Society, 0-7695-2051-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Frame-Based, Quality-of-Service, Packet Scheduling, Round-robin, Weighted-round-robin, Slot-reuse |
24 | Kazuhiko Miki, David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill, Yuichi Goto |
A new test and characterization scheme for 10+ GHz low jitter wide band PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 856-859, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Sitt Tontisirin, Reinhard Tielert |
A Gb/s one-fourth-rate CMOS CDR circuit without external reference clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Shun Nagata, Ewout Martens, Adam Cooman, Jan Craninckx |
A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 66th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2023, Tempe, AZ, USA, August 6-9, 2023, pp. 895-899, 2023, IEEE, 979-8-3503-0210-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | N. K. Anushkannan, H. Mangalam |
Design of an ultra-low power, low complexity and low jitter PLL with digitally controlled oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Adv. Intell. Paradigms ![In: Int. J. Adv. Intell. Paradigms 15(1), pp. 98-107, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Kuo-Hsing Cheng, Yu-Lung Lo |
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 178-182, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Chien-Hung Kuo, Yi-Shun Shih |
A frequency synthesizer using two different delay feedbacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2799-2802, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | S. Nagavarapu, J. Yan, Edward K. F. Lee, Randall L. Geiger |
An asynchronous data recovery/retransmission technique with foreground DLL calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 354-357, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | T. H. Szymanski |
Scheduling and Channel Assignment of Backhaul Traffic in Infrastructure Wireless Mesh Networks with Near-Minimal Delay and Jitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDS ![In: The Fourth International Conference on Digital Society, ICDS 2010, 10.16 February 2010, St. Maarten, Netherlands Antilles, pp. 78-85, 2010, IEEE Computer Society, 978-0-7695-3953-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
backhaul, low-jitter, scheduling, quality of service, wireless mesh network, TDMA, OFDMA, crossbar, relay network, input-queue |
22 | T. H. Szymanski |
Throughput and QoS optimization in nonuniform multichannel wireless mesh networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Q2SWinet ![In: Q2SWinet'08 - Proceedings of the 4th ACM Workshop on Q2S and Security for Wireless and Mobile Networks, Vancouver, British Columbia, Canada, October 27-28, 2008, pp. 9-19, 2008, ACM, 978-1-60558-237-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low-jitter, scheduling, QoS, network, wireless, mesh, multihop |
19 | Hamed Khanmirza, Sajjad Zarifzadeh, Nasser Yazdani |
ADPQ: An Adaptive Approach for Expedited Forwarding Traffic Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the 10th IEEE Symposium on Computers and Communications (ISCC 2005), 27-30 June 2005, Murcia, Cartagena, Spain, pp. 801-806, 2005, IEEE Computer Society, 0-7695-2373-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Saurabh Kumar, Yatendra Kumar Singh |
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 94, pp. 102108, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Jianguo Hu, Renfei Zou, Yao Yao, Jiajun He, Deming Wang |
A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 143, pp. 106061, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino |
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(12), pp. 3320-3337, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Suneui Park, Seojin Choi, Seyeon Yoo, Yoonseo Cho, Jaehyouk Choi |
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(9), pp. 2829-2840, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi |
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(9), pp. 2841-2855, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Jaehyouk Choi |
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(2), pp. 480-491, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie |
A Low-Jitter and Low-Spur Charge-Sampling PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(2), pp. 492-504, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Mohammad Bagheri, Xun Li |
An ultra-low power and low jitter frequency synthesizer for 5G wireless communication and IoE applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 50(3), pp. 1021-1047, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi |
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 56(1), pp. 298-309, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Charalampos Stylianopoulos, Magnus Almgren, Olaf Landsiedel, Marina Papatriantafilou, Trevor Neish, Linus Gillander, Bengt Johansson, Staffan Bonnier |
On the performance of commodity hardware for low latency and low jitter packet processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DEBS ![In: 14th ACM International Conference on Distributed and Event-based Systems, DEBS 2020, Montreal, Quebec, Canada, July 13-17, 2020, pp. 177-182, 2020, ACM, 978-1-4503-8028-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
19 | Mario Mercandelli |
Techniques for low-jitter and low-area occupation fractional-N Frequency synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2020 |
RDF |
|
19 | Yongping Fan, Bo Xiang, Dan Zhang, James S. Ayers, Kuan-Yueh James Shen, Andrey Mezhiba |
Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019, pp. 320-322, 2019, IEEE, 978-1-5386-8531-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Xiang Gao |
Low Jitter and Low Power PLL:Towards The Utopia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 2019 International SoC Design Conference, ISOCC 2019, Jeju, Korea (South), October 6-9, 2019, pp. 38-39, 2019, IEEE, 978-1-7281-2478-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi |
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(4), pp. 1192-1202, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Motahhareh Estebsari, Mohammad Gholami, Mohammad Javad Ghahramanpour |
A wide range delay locked loop for low power and low jitter applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 46(3), pp. 401-414, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Faeze Noruzpur, Sina Mahdavi, Maryam Poreh, Shima Tayyeb Ghasemi |
A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18μm Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: 25th International Conference `Mixed Design of Integrated Circuits and System`, MIXDES 2018, Gdynia, Poland, June 21-23, 2018, pp. 109-115, 2018, IEEE, 978-83-63578-14-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Ahmed Musa, Wei Deng 0001, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa |
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 49(1), pp. 50-60, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt |
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 48(12), pp. 3134-3145, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Davide Tasca |
Low-power low-jitter fractional-N frequency synthesizer using bang bang phase detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2012 |
RDF |
|
19 | Yingmei Chen, Zhigong Wang, Li Zhang |
A low-jitter low-power monolithically integrated optical receiver for SDH STM-16. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 54(6), pp. 1293-1299, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Ulrich L. Rohde, Ajay K. Poddar |
Digital frequency synthesizer using adaptive mode-coupled resonator mechanism for low phase noise and low jitter applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 414-417, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Fu Luo, Godi Fischer |
Low jitter audio range PLL with ultra low power dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011, pp. 241-246, 2011, ACM, 978-1-4503-0667-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | David E. Duarte, Suching Hsu, Keng L. Wong, Mingwei Huang, Greg Taylor |
Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings, pp. 1-4, 2010, IEEE, 978-1-4244-5758-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Régis Roubadia, Sami Ajram, Guy Cathébras |
Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 458-467, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Amr M. Fahim |
A compact, low-power low-jitter digital PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2003 - 29th European Solid-State Circuits Conference, Estoril, Portugal, September 16-18, 2003, pp. 101-104, 2003, IEEE, 0-7803-7995-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton |
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(12), pp. 1804-1812, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Kuo-Hsing Chen, Huan-Sen Liao, Lin-Jiunn Tzou |
A low-jitter and low-power phase-locked loop design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 257-260, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Jun Zhao 0002, Yong-Bin Kim |
A low power 32 nanometer CMOS digitally controlled oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 183-186, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Jaehong Ko, Wookwan Lee, Soo-Won Kim |
2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 122-125, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
jitter, PLL, output buffer, charge-pump |
17 | Wen-Chi Wu, Chih-Chien Huang, Chih-Hsiung Chang, Nai-Heng Tseng |
Low-power CMOS PLL for clock generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 633-636, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Juyeop Kim, Yongwoo Jo, Hangi Park, Taeho Seong, Younghyun Lim, Jaehyouk Choi |
A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(2), pp. 424-434, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Min-Ji Kim, Won-Young Lee |
Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEIC ![In: International Conference on Electronics, Information, and Communication, ICEIC 2024, Taipei, Taiwan, January 28-31, 2024, pp. 1-3, 2024, IEEE, 979-8-3503-7188-8. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi |
10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 190-192, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Xiangyu Meng 0003, Wang Xie, Jiaqi Zhang, Zhao Zhang 0004 |
A 0.2-7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 72, pp. 1-8, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Dengyu Ran, Xiao Chen, Lei Song |
Agile: A high-scalable and low-jitter flow tables lifecycle management framework for multi-core programmable data plane. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Commun. ![In: Comput. Commun. 207, pp. 56-65, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Zhen Li 0037, Zhenrong Li, Xudong Wang, Zeyuan Wang, Yiqi Zhuang |
A low jitter sub-sampling phase-locked loop with sampling thermal noise cancellation technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 51(1), pp. 67-79, January 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Jin Wu, Minwei Hu, Xudong Wu, Yang Zuo, Chenggong Wan, Lixia Zheng, Weifeng Sun |
A low jitter fractional PLL with offset current charge pump. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 138, pp. 105833, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Shaorong Lu, Sheng Xie, Luhong Mao, Ruiliang Song, Naibo Zhang |
A low jitter 50 Gb/s PAM4 optical receiver in 130 nm SiGe BiCMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 136, pp. 105803, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Qing Liu, Heming Wang, Fangxu Lv, Geng Zhang 0001, Dongbin Lv |
Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCEIC ![In: 4th International Conference on Computer Engineering and Intelligent Control, ICCEIC 2023, Guangzhou, China, October 20-22, 2023, pp. 216-220, 2023, IEEE, 979-8-3503-0887-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Tianshu Xu, Wen Gu, Koichi Ota, Shinobu Hasegawa |
A Low-Jitter Hand Tracking System for Improving Typing Efficiency in Virtual Reality Workspace. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TENCON ![In: IEEE Region 10 Conference, TENCON 2023, Chiang Mai, Thailand, October 31 - Nov. 3, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-0219-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Andreas Depold, Christian Dorn, Robert Weigel, Fabian Lurz |
A Simple Low Jitter Wireless Triggering and Unidirectional Communication System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WiSNeT ![In: 2023 IEEE Topical Conference on Wireless Sensors and Sensor Networks, Las Vegas, NV, USA, January 22-25, 2023, pp. 32-35, 2023, IEEE, 978-1-6654-9321-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Hsi-Hao Huang, Chun-Hsien Liu, Tzu-Yun Huang, Sheng-Di Lin, Chen-Yi Lee |
Self-Restoring and Low-Jitter Circuits for High Timing-Resolution SPAD Sensing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Jin Sun, Jiahao Hu, Ziqi Song, Qing Li, Dian He, Hujun Jia |
A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 15th IEEE International Conference on ASIC, ASICON 2023, Nanjing, China, October 24-27, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-1298-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Simone Mattia Dartizio |
Design of small-footprint, high-spectral purity and low-jitter digitally-intensive frequency synthetizers ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2023 |
RDF |
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16 | Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong |
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(6), pp. 1712-1722, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Hangi Park, Chanwoong Hwang, Taeho Seong, Jaehyouk Choi |
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(12), pp. 3527-3537, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Woorham Bae |
Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 80680-80694, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu |
A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(2), pp. 269-273, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Shuxiang Song, Zefa Liu, Mingcan Cen, Chaobo Cai |
A 9.8-12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(11), pp. 2250190:1-2250190:14, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal |
A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 50(8), pp. 2900-2912, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Tianxiang Wu, Xi Wang, Yong Chen 0005, Junyan Ren, Shunli Ma |
A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 50(2), pp. 367-381, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Jiyun Tong, Sha Wang, Shuang Zhang, Mengdi Zhang, Ye Zhao, Fazhan Zhao |
A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 22(1), pp. 284, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Chengxian Pan, Chunqi Shi, Guoliang Zhao, Boxiao Liu, Leilei Huang, Runxi Zhang |
A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 19(24), pp. 20220432, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Sheng Xie, Chengkui Jia, Luhong Mao, Gaolei Zhou, Naibo Zhang, Ruiliang Song |
Low jitter design for quarter-rate CDR of 100Gb/s PAM4 optical receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 19(15), pp. 20220281, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Jiahao Hu, Zhongxian Huang, Baoxing Duan, Qing Li, Ziqi Song, Dian He |
A Multiplying Delay-Locked Loop design with low jitter and high linearity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTA ![In: 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2022, Xi'an, China, October 28-30, 2022, pp. 38-39, 2022, IEEE, 978-1-6654-9269-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang Won Son, Thomas Byunghak Cho |
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 56(12), pp. 3756-3767, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Shahram Modanlou, Gholamreza Ardeshir, Mohammad Gholami |
Analysis and design of a low jitter delay-locked loop using lock state detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 49(5), pp. 1410-1419, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Chia-Chen Chang, Yu-Tung Chin, Hossameldin A. Ibrahim, Kang-Yu Chang, Shyh-Jye Jou |
A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Woorham Bae |
State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Junghoon Jin, Seungjun Kim, Sunguk Choi, Pil-Ho Lee, Sang-jae Rhee, Ki-hwan Choi, Jongsun Kim |
A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021, pp. 311-312, 2021, IEEE, 978-1-6654-0174-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Souradip Sen, Utkarsh Upadhyaya, Krishna Reddy Kondreddy, Arun Goyal, Sandeep Goyal, Shalabh Gupta |
A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, VLSID 2021, Guwahati, India, February 20-24, 2021, pp. 216-221, 2021, IEEE, 978-1-6654-4087-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Sarang Kazeminia, Arefeh Soltani |
A low-jitter leakage-free digitally calibrated phase locked loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 88, pp. 106865, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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16 | Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal |
A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 29(9), pp. 2050142:1-2050142:22, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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16 | Jin Wu, Shuang Chen, Kang Hu, Lixia Zheng, Weifeng Sun |
A low jitter multiplying delay-locked loop with static phase offset elimination applied to time-to-digital converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 106, pp. 104926, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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16 | Youngbog Yoon, Hyunsu Park, Chulwoo Kim |
A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. ![In: IEEE Trans. Circuits Syst. 67-II(11), pp. 2342-2346, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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16 | Wei Zou, Daming Ren, Xuecheng Zou |
A wideband low-jitter PLL with an optimized Ring-VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 17(3), pp. 20190703, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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16 | Pierre Bisiaux, Elena Blokhina, Eugene Koskin, Teerachot Siriburanon, Dimitri Galayko |
Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: European Conference on Circuit Theory and Design, ECCTD 2020, Sofia, Bulgaria, September 7-10, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-7183-8. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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16 | Zeeshan Ali, Makwana Harshit R, Shalabh Gupta |
A Low Jitter Double-Tailed Strong-Arm Latch Based Digital-to-Time Converter (DTC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020, Glasgow, Scotland, UK, November 23-25, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-6044-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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16 | Mengshuai Wang, Yingmei Chen, Jinlei Yuan |
A low jitter 50Gb/s PAM4 CDR of Receiver in 40nm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCSP ![In: 2020 International Conference on Wireless Communications and Signal Processing (WCSP), Nanjing, China, October 21-23, 2020, pp. 349-352, 2020, IEEE, 978-1-7281-7236-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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16 | Juyeop Kim, Younghyun Lim, Heein Yoon, Yongsun Lee, Hangi Park, Yoonseo Cho, Taeho Seong, Jaehyouk Choi |
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(12), pp. 3466-3477, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Heein Yoon, Suneui Park, Jaehyouk Choi |
A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(6), pp. 1564-1574, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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16 | Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi |
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(4), pp. 927-936, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
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