Search results for "n-flop"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Kuo-Hsing Cheng, Yung-Hsiang Lin	A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
91	Saihua Lin, Huazhong Yang, Rong Luo	High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit.	ISVLSI	2007	DBLP DOI BibTeX RDF
86	Pramod Kumar Meher	Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
82	Liam P. Maguire, T. Martin McGinnity, L. J. McDaid	From a Fuzzy Flip-Flop to a MVL Flip-Flop.	ISMVL	1999	DBLP DOI BibTeX RDF	MVL flip-flop, MOS implementation, fuzzy reasoning
80	Amit Jain, David T. Blaauw	Slack borrowing in flip-flop based sequential circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	timing analysis
77	Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri	A robust, fast pulsed flip-flop design.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flip-flop, latch
69	Fatemeh Aezinia, Ali Afzali-Kusha, Caro Lucas	Optimizing High Speed Flip-Flop Using Genetic Algorithm.	APCCAS	2006	DBLP DOI BibTeX RDF
69	Tolga Yalçin, Neslin Ismailoglu	Design of a fully-static differential low-power CMOS flip-flop.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
69	Kwang-Ting Cheng	Partial scan designs without using a separate scan clock.	VTS	1995	DBLP DOI BibTeX RDF	flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock
67	Motoi Inaba, Koichi Tanno, Okihiko Ishizuka	Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits.	ISMVL	2002	DBLP DOI BibTeX RDF	Multi-valued flip-flop, Down literal circuit, Analog inverter, Voltage comparator, NMIN circuit
64	Saihua Lin, Huazhong Yang, Rong Luo	A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
59	A. S. Seyedi, S. H. Rasouli, Amir Amirabadi, Ali Afzali-Kusha	Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology.	ISVLSI	2006	DBLP DOI BibTeX RDF
59	A. S. Seyedi, S. H. Rasouli, Amir Amirabadi, Ali Afzali-Kusha	Low power low leakage clock gated static pulsed flip-flop.	ISCAS	2006	DBLP DOI BibTeX RDF
59	Marius Padure, Sorin Cotofana, Stamatis Vassiliadis	Design and experimental results of a CMOS flip-flop featuring embedded threshold logic.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
59	Bill Pontikakis, Mohamed Nekili	A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
54	Bo Fu, Paul Ampadu	Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency.	ISCAS	2007	DBLP DOI BibTeX RDF
54	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto	Single-Event Upset Analysis and Protection in High Speed Circuits.	ETS	2006	DBLP DOI BibTeX RDF
54	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Pre-capturing static pulsed flip-flops.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
54	Jack J. Dongarra	High Performance Computing Trends and Self Adapting Numerical Software.	ISHPC	2003	DBLP DOI BibTeX RDF
53	Gerard Elineau, Werner Wiesbeck	An New J-K Flip-Flop for Synchronizers.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Arbiter circuit, data intersection, tunnel diode flip-flop, flip-flop, synchronizer circuit
53	Leo Sintonen	A Clocked Multivalued Flip-Flop.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	N-valued logic design, N-valued logic devices, N-state flip-flop, multivalued flip-flop, multivalued sequential circuits
51	Mohamed A. Elgamel, Tarek Darwish, Magdy A. Bayoumi	Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops.	ISVLSI	2002	DBLP DOI BibTeX RDF	noise, power, flip-flop, deep submicron
51	Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija	Conditional pre-charge techniques for power-efficient dual-edge clocking.	ISLPED	2002	DBLP DOI BibTeX RDF	clocked storage elements, dual edge-triggered flip-flop, power consumption, clocking, clock distribution
48	Chul Soo Kim, Joo-Seong Kim, Bai-Sun Kong, Yongsam Moon, Young-Hyun Jun	Presetting pulse-based flip-flop.	ISCAS	2008	DBLP DOI BibTeX RDF
48	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
48	Yinshui Xia, Lun-Yao Wang, A. E. A. Almaini	A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	multiple-valued clock, CMOS, flip-flops, multiple-valued logic
48	Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra	A novel high-speed sense-amplifier-based flip-flop.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
48	Zhong-Ching Lu, Ting-Chi Wang	Concurrent flip-flop and buffer insertion with adaptive blockage avoidance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
48	Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao	Flip-Flop and Repeater Insertion for Early Interconnect Planning.	DATE	2002	DBLP DOI BibTeX RDF
48	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	ARVLSI	2001	DBLP DOI BibTeX RDF
48	Mark Vesterbacka	A robust differential scan flip-flop.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
45	Kee Sup Kim, Charles R. Kime	Partial scan flip-flop selection by use of empirical testability.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	scan flip-flop selection, serial scan, design for testability, testability, partial scan
45	Jason P. Hurst, Nick Kanopoulos	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing
43	Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu	Fault modeling and testing of retention flip-flops in low power designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
43	Omid Sarbishei, Mohammad Maymandi-Nejad	Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops.	ISCAS	2007	DBLP DOI BibTeX RDF
43	Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty	A TMR Scheme for SEU Mitigation in Scan Flip-Flops.	ISQED	2007	DBLP DOI BibTeX RDF
40	Jing Wang 0001, Gianluca Meloni, Gianluca Berrettini, Luca Potì, Antonella Bogoni	All-Optical Clocked Flip-Flops Exploiting SOA-Based SR Latches and Logic Gates.	OSC	2009	DBLP DOI BibTeX RDF	optical flip-flop, optical logic gate, optical signal processing, semiconductor optical amplifier (SOA)
40	Gustavo Neuberger, Gilson I. Wirth, Ricardo Reis 0001	Protecting digital circuits against hold time violation due to process variability.	SBCCI	2009	DBLP DOI BibTeX RDF	flip-flop characterization, hold time violations, race immunity, clock skew, process variability
40	Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic	Level conversion for dual-supply systems.	ISLPED	2003	DBLP DOI BibTeX RDF	level conversion, flip-flop, dual-supply voltage
37	Jun Seomun, Jae-Hyun Kim, Youngsoo Shin	Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
37	Håvard Pedersen Alstad, Snorre Aunet	Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology.	DDECS	2008	DBLP DOI BibTeX RDF
37	Dong-Shong Liang, Kwang-Jow Gan	New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits.	DELTA	2008	DBLP DOI BibTeX RDF	negative differential resistance(NDR), monostable-bistable transition logic elements(MOBILE)
37	Rubil Ahmadi	A Hold Friendly Flip-Flop For Area Recovery.	ISCAS	2007	DBLP DOI BibTeX RDF
37	Jun Seomun, Jaehyun Kim, Youngsoo Shin	Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits.	DAC	2007	DBLP DOI BibTeX RDF
37	S. H. Rasouli, Amir Amirabadi, A. Seyedi, Ali Afzali-Kusha	Double edge triggered Feedback Flip-Flop in sub 100NM technology.	ASP-DAC	2006	DBLP DOI BibTeX RDF
37	Saihua Lin, Rong Luo, Huazhong Yang, Hui Wang 0004	A 0.9V 10GHz 71µW Static D Flip-flop by using FinFET Devices.	APCCAS	2006	DBLP DOI BibTeX RDF
37	Myint Wai Phyu, Wang Ling Goh, Kiat Seng Yeo	A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
37	Hui Zhang, Pinaki Mazumder	Design of a new sense amplifier flip-flop with improved power-delay-product.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
37	Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel	Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.	PATMOS	2004	DBLP DOI BibTeX RDF
37	Jacek Kluska, Zbigniew Hajduk	Digital Implementation of Fuzzy Petri Net Based on Asynchronous Fuzzy RS Flip-Flop.	ICAISC	2004	DBLP DOI BibTeX RDF
37	Sang-Dae Shin, Hun Choi, Bai-Sun Kong	Variable sampling window flip-flop for low-power application.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
37	Satoshi Sakaidani, Naoto Miyamoto, Tadahiro Ohmi	Flexible processor based on full-adder/ d-flip-flop merged module.	ASP-DAC	2001	DBLP DOI BibTeX RDF
37	Chulwoo Kim, Sung-Mo Kang	A low-power reduced swing single clock flip-flop.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
37	Nikola Nedovic, Vojin G. Oklobdzija	Dynamic Flip-Flop with Improved Power.	ICCD	2000	DBLP DOI BibTeX RDF
37	Richard F. Hobson, Allan R. Dyck	A Multiple-Input Single-Phase Clock Flip-Flop Family.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
37	Hideaki Matsuzaki, Toshihiro Itoh, Masafumi Yamamoto	A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
37	Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante	Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection.	DATE	1998	DBLP DOI BibTeX RDF
37	G. Lacroix, Philippe Marchegay, G. Piel	Comments on "The Anomalous Behavior of Flip-Flops in Synchronizer Circuits".	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	uncertainty interval, Anomalous response of flip-flop, flip-flop metastable state, asynchronous interactions, synchronizer failures
37	Nikolaos Gaitanis, Constantine Halatsis	A New Double-Rank Realization of Sequential Machines.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	Boolean memory, cyclic Boolean memory, double-rank circuits, excitation function, excitation matrix, flip-flop memory, n-flop, sequential machines, state assignment
34	Uthman Alsaiari, Resve A. Saleh	Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits.	ISQED	2008	DBLP DOI BibTeX RDF	Partitioning, Redundancy, Yield, Flip-Flop
34	Frank Rubin	Decrypting a Stream Cipher Based on J-K Flop-Flops.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	J?K flip-flop, linear shift register, cryptography, stream cipher, Boolean equations, code breaking
32	Pei-Hsin Ho	Industrial clock design.	ISPD	2009	DBLP DOI BibTeX RDF	low power, variability, physical design, clock tree synthesis
32	Eric L. Hill, Mikko H. Lipasti	Transparent mode flip-flops for collapsible pipelines.	ICCD	2007	DBLP DOI BibTeX RDF
32	Ben Choi 0002, Kunal Tipnis	New Components for Building Fuzzy Logic Circuits.	FSKD (2)	2007	DBLP DOI BibTeX RDF
32	Chao Yan 0001, Mark R. Greenstreet	Circuit Level Verification of a High-Speed Toggle.	FMCAD	2007	DBLP DOI BibTeX RDF
32	Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta 0001	Optimization of Master-Slave Flip-Flops for High-Performance Applications.	PATMOS	2006	DBLP DOI BibTeX RDF
32	Fatemeh Aezinia, S. Najafzadeh, Ali Afzali-Kusha	Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops.	APCCAS	2006	DBLP DOI BibTeX RDF
32	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Dual-Edge Triggered Static Pulsed Flip-Flops.	VLSI Design	2005	DBLP DOI BibTeX RDF
32	Robert J. Drost, Craig Forrest, Bruce Guenin, Ron Ho, Ashok V. Krishnamoorthy, Danny Cohen, John E. Cunningham, Bernard Tourancheau, Arthur Zingher, Alex Chow, Gary Lauterbach, Ivan E. Sutherland	Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication.	Hot Interconnects	2005	DBLP DOI BibTeX RDF
32	Clint Morgan, Darko Stefanovic, Cristopher Moore, Milan N. Stojanovic	Building the Components for a Biomolecular Computer.	DNA	2004	DBLP DOI BibTeX RDF
32	Ran Ginosar	Fourteen Ways to Fool Your Synchronizer.	ASYNC	2003	DBLP DOI BibTeX RDF
32	Dong Xiang, Yi Xu	Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals.	VTS	2001	DBLP DOI BibTeX RDF
32	Parag K. Lala, Anup Singh, Alvernon Walker	A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs.	DFT	1999	DBLP DOI BibTeX RDF	DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing
32	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell	On variable clock methods for path delay testing of sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
31	Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi	Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process.	IOLTS	2019	DBLP DOI BibTeX RDF
31	Motoki Tokumasu, Hiroshige Fujii, Masako Ohta, Tsunealu Fuse, Atsushi Kameyama	A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF).	CICC	2002	DBLP DOI BibTeX RDF
29	Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Energy recovery clocking scheme and flip-flops for ultra low-energy applications.	ISLPED	2003	DBLP DOI BibTeX RDF	flip-flop, clock, clock tree, energy recovery, adiabatic
29	Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe 0001, Marios C. Papaefthymiou	A 225 MHz resonant clocked ASIC chip.	ISLPED	2003	DBLP DOI BibTeX RDF	adiabatic logic, resonant LC tank, single phase, VLSI, CMOS, flip-flop, low energy, clock generator
29	Jongsun Park 0001, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy 0001	High performance and low power FIR filter design based on sharing multiplication.	ISLPED	2002	DBLP DOI BibTeX RDF	FIR filter design, computation sharing, conditional capture flip-flop, high performance and low power carry select adder
29	Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa	A unified approach in the analysis of latches and flip-flops for low-power systems.	ISLPED	1998	DBLP DOI BibTeX RDF	master-slave latch, optimization, timing, flip-flop, power measurement
29	Branka Medved Rogina, Bozidar Vojnovic	Metastability evaluation method by propagation delay distribution measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
26	Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, Weidong Kuang	Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Chuan Lin 0002, Hai Zhou 0001	Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
26	Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis 0001, Gilson I. Wirth, Ralf Brederlow, Christian Pacha	Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
26	Hoa Le Minh, Fary Ghassemlooy, Wai Pang Ng	An Ultrafast with High Contrast Ratio 12 All-optical Switch based on Tri-arm Mach-Zehnder employing All-optical Flip-flop.	ICC	2007	DBLP DOI BibTeX RDF
26	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Power Consumption Analysis of Flip-flop Based Interconnect Pipelining.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Lih-Yih Chiou, Shien-Chun Luo	An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Gefu Xu, Adit D. Singh	Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing.	VLSI Design	2007	DBLP DOI BibTeX RDF
26	Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang	Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar	Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic.	ISQED	2006	DBLP DOI BibTeX RDF
26	Peiyi Zhao, Pradeep Kumar Golconda, C. Archana, Magdy A. Bayoumi	A Double-Edge Implicit-Pulsed Level Convert Flip-Flop.	ISVLSI	2004	DBLP DOI BibTeX RDF
26	Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He 0001	Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction.	ISQED	2004	DBLP DOI BibTeX RDF
26	Pradeep Varma, Ashutosh Chakraborty	Low-Voltage, Double-Edge-Triggered Flip Flop.	PATMOS	2003	DBLP DOI BibTeX RDF
26	Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou	A high-performance low-power static differential double edge-triggered flip-flop.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
26	Tetsuya Uemura, Toshio Baba	Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop.	ISMVL	2000	DBLP DOI BibTeX RDF	tunnel transistor, multiple-valued T-gate, D-FF, NDR
26	Rafael Vargas-Bernal, Arturo Sarmiento-Reyes	A topology-based method for identifying flip-flop graphs in BJT circuits.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
26	Vincent Schmitt	Flip-Flop Nets.	STACS	1996	DBLP DOI BibTeX RDF
21	Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky	Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	CMOS logic devices, reliability, Markov process, monte carlo method, poisson distribution, laplace transform
21	Douglas S. Greer	Images as Symbols: An Associative Neurotransmitter-Field Model of the Brodmann Areas.	Trans. Comput. Sci.	2009	DBLP DOI BibTeX RDF	Natural intelligence, cognitive signal processing, neurotransmitter fields, pattern recognition, memory, computational neuroscience
21	Jackey Z. Yan, Natarajan Viswanathan, Chris Chu	Handling complexities in modern large-scale mixed-size placement.	DAC	2009	DBLP DOI BibTeX RDF	incremental placement, mixed-size design, floorplanning