Search results for "netlist"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
128	Andrew B. Kahng, Sherief Reda	Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
99	Scott W. Hadley, Brian L. Mark, Anthony Vannelli	An efficient eigenvector approach for finding netlist partitions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
82	P. S. Nagendra Rao, C. S. Jayathirtha, C. S. Raghavendra Prasad	New Net Models for Spectral Netlist Partitioning.	VLSI Design	1998	DBLP DOI BibTeX RDF	Netlist Partitioning, Spectral Partitioning Net Models, Clique Models, Star Models, Graph Partitioning
79	Guenter Stenz, Bernhard M. Riess, Bernhard Rohfleisch, Frank M. Johannes	Performance optimization by interacting netlist transformations andplacement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
75	Steven D. Corey, Andrew T. Yang	Automatic netlist extraction for measurement-based characterization of off-chip interconnect.	ICCAD	1996	DBLP DOI BibTeX RDF	MCM substrate-level interconnect circuitry, SPICE netlist, automatic netlist extraction, linear circuits, measured time domain refectometry data, measurement-based characterization, microstrip circuits, multiport system, off-chip interconnect, reflection transmission, time-domain scattering parameters, user-specified cutoff frequency, delay, crosstalk, circuit simulator, multichip modules, nonlinear circuits
69	Larry G. Jones	Fast batch incremental netlist compilation hierarchical schematics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
62	Qinghua Liu, Malgorzata Marek-Sadowska	A study of netlist structure and placement efficiency.	ISPD	2004	DBLP DOI BibTeX RDF	netlist structure, efficiency, placement
60	Andrew B. Kahng, Sherief Reda	Evaluation of placer suboptimality via zero-change netlist transformations.	ISPD	2005	DBLP DOI BibTeX RDF	placer suboptimality, benchmarking, wirelength
60	Pierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa	Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components.	DATE	2004	DBLP DOI BibTeX RDF
60	J. H. Jiang, Wen-Ben Jone, Shih-Chieh Chang, Swaroop Ghosh	Embedded core test generation using broadcast test architecture and netlist scrambling.	IEEE Trans. Reliab.	2003	DBLP DOI BibTeX RDF
53	Jeehong Yang, Serap A. Savari, Oskar Mencer	An Approach to Graph and Netlist Compression.	DCC	2008	DBLP DOI BibTeX RDF	Graph Compression, Netlist Compression, EDIF Compression, CEDIF, SUBDUE, GRAPHITOUR
51	Jin-Tai Yan, Pei-Yung Hsiao	A new fuzzy-clustering-based approach for two-way circuit partitioning.	VLSI Design	1995	DBLP DOI BibTeX RDF	fuzzy-clustering-based approach, two-way circuit partitioning, circuit netlist, undirected edge-weighted graph, tree net model, clustering distance, area information, area-balanced constraints, circuit benchmarks, VLSI, simulated annealing, network topology, trees (mathematics), fuzzy set theory, logic partitioning, fuzzy c-means clustering, fuzzy memberships
50	Jean-Baptiste Note, Éric Rannaud	From the bitstream to the netlist.	FPGA	2008	DBLP DOI BibTeX RDF	bitstream format, FPGA, reverse-engineering
48	Cheng Xie, Wenzhi Chen, Jiaoying Shi, Lü Ye	Hierarchical Integration of Runtime Models.	ICESS	2004	DBLP DOI BibTeX RDF
48	Charles J. Alpert, Andrew B. Kahng	Multiway partitioning via geometric embeddings, orderings, and dynamic programming.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
42	Reilly McKendrick, Keenan Faulkner, Jeffrey Goeders	Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison.	ICFPT	2023	DBLP DOI BibTeX RDF
41	Kaushik De	Test methodology for embedded cores which protects intellectual property.	VTS	1997	DBLP DOI BibTeX RDF	core I/Os, ASIC I/O inaccessibility, partial netlist generation, ASIC level test generation, gate testing, core scan chain, selective boundary scan, coreware design paradigm, logic testing, heuristic algorithm, structural analysis, intellectual property protection, embedded cores, test methodology
40	Jason Baumgartner, Hari Mony, Adnan Aziz	Optimal Constraint-Preserving Netlist Simplification.	FMCAD	2008	DBLP DOI BibTeX RDF
39	Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Augusto da Luz Reis	An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
39	Pranav Anbalagan, Jeffrey A. Davis	A priori prediction of tightly clustered connections based on heuristic classification trees.	SLIP	2006	DBLP DOI BibTeX RDF	wire length prediction
32	Bita Gorjiara, Daniel Gajski	Automatic architecture refinement techniques for customizing processing elements.	DAC	2008	DBLP DOI BibTeX RDF	GNR, nanocoded architectures, no-instruction-set computer (NISC), refinement, high-level synthesis, power, ASIP, datapath, netlist
32	Robert F. Lembach, Rafael A. Arce-Nazario, Donald Eisenmenger, Cory Wood	A diagnostic method for detecting and assessing the impact of physical design optimizations on routing.	ISPD	2005	DBLP DOI BibTeX RDF	routing, efficiency, timing, placement, physical synthesis, netlist
32	Peter J. Osler	Placement driven synthesis case studies on two sets of two chips: hierarchical and flat.	ISPD	2004	DBLP DOI BibTeX RDF	synthesis, placement, application specific integrated circuit (ASIC), register transfer level (RTL), static timing analysis (STA), netlist
32	Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
32	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	A genetic algorithm-based system for generating test programs for microprocessor IP cores.	ICTAI	2000	DBLP DOI BibTeX RDF	industrial property, genetic algorithm based system, test program generation, microprocessor IP cores, digital systems design trend, design-and-reuse paradigm, intellectual property cores, encrypted gate-level netlist, testability problems, automatic approach, processor cores, fault coverage figures, random approach, genetic algorithms, genetic algorithms, microprocessor chips, automatic test software, test program, electronic engineering computing
32	Emmanuel Simeu, Arno W. Peters, Iyad Rayane	Automatic Design of Optimal Concurrent Fault Detector for Linear Analog Systems.	FTCS	1999	DBLP DOI BibTeX RDF	concurrent, detection, state space, residual, netlist
32	Fumio Suzuki, Hisao Koizumi, M. Hiramine, K. Yamamoto, Hiroto Yasuura, K. Okino	A HW/SW co-design environment for multi-media equipments development using inverse problem.	CODES	1997	DBLP DOI BibTeX RDF	audio circuitry, conceptual stage, development cycle reduction, hardware/software codesign environment, human recognition characteristics, human sensibilities, multimedia equipment development, netlist generation, repeated results comparison, semiconductor circuits, semiconductor production, signal reproduction, system response, television receiver, evaluation, perception, multimedia communication, inverse problem, cost estimates, performance estimates, optimization method, filter design, numerical models, susceptibility, playback
32	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev	Decomposition and technology mapping of speed-independent circuits using Boolean relations.	ICCAD	1997	DBLP DOI BibTeX RDF	Boolean decomposition, decomposed logic sharing, design library, library matching, logic decomposition, logic resynthesis, signal insertion, two-input combinational gate, two-input sequential gate, optimization, technology mapping, circuit CAD, speed-independent circuits, netlist, complex gates, Boolean relations
32	Paul Tafertshofer, Andreas Ganz, Manfred Henftling	A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists.	ICCAD	1997	DBLP DOI BibTeX RDF	SAT-based implication engine, circuit clause description, efficient ATPG, implication evaluation, indirect implications, netlist optimization, structure based methods, graph algorithms, automatic testing, logic circuits, graph model, equivalence checking, implication graph
32	H. Fatih Ugurdag, Thomas E. Fuhrman	Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath.	ICCD	1996	DBLP DOI BibTeX RDF	Autocircuit, clock edge general behavioral synthesis system, physical datapaths, next-generation synthesis tool, behavioral HDL input descriptions, data-flow representations, use-trees, raw-states, word-oriented synthesis, unique parameterized netlist representation, high level synthesis, high-level design
32	Louis Monier, Ramsey W. Haddad, Jeremy Dion	Recursive layout generation.	ARVLSI	1995	DBLP DOI BibTeX RDF	BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration
32	C. P. Ravikumar, Hemant Joshi	HISCOAP: a hierarchical testability analysis tool.	VLSI Design	1995	DBLP DOI BibTeX RDF	HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model
32	Yuhong Yu, Ashok Samal, Sharad C. Seth	A system for recognizing a large class of engineering drawings.	ICDAR	1995	DBLP DOI BibTeX RDF	engineering drawings recognition, symbolic engineering drawings, chemical plant diagrams, automatic recognition, domain-independent rules segment symbols, understanding subsystem, domain-specific matchers, printed images, graphical user interface, design verification, large database, flowcharting, flowcharts, netlist, residual errors
31	Rajat Subhra Chakraborty, Swarup Bhunia	Hardware protection and authentication through netlist level obfuscation.	ICCAD	2008	DBLP DOI BibTeX RDF	IP piracy, design for security, hardware authentication, hardware obfuscation, hardware protection
31	Aaron P. Hurst	Automatic synthesis of clock gating logic with controlled netlist perturbation.	DAC	2008	DBLP DOI BibTeX RDF	low power, clock gating, logic optimization, dynamic power
31	Qinghua Liu, Malgorzata Marek-Sadowska	A study of netlist structure and placement efficiency.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
31	Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji	Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
31	Hendrik Hartje, Ingmar Neumann, Dominik Stoffel, Wolfgang Kunz	Cycle time optimization by timing driven placement with simultaneous netlist transformations.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
31	Charles J. Alpert, Andrew B. Kahng	A general framework for vertex orderings, with applications to netlist clustering.	ICCAD	1994	DBLP DOI BibTeX RDF
29	Suresh Raman, Mike Lubyanitsky	Cone Resynthesis ECO Methodology for Multi-Million Gate Designs.	VLSI Design	2009	DBLP DOI BibTeX RDF
29	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
29	Lijun Li, Carl Tropper	A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation.	PADS	2007	DBLP DOI BibTeX RDF
29	Ning Lu, Judy H. McCullen	Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance.	ISQED	2007	DBLP DOI BibTeX RDF
29	Jindrich Zejda, Li Ding 0002	TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks.	ISQED	2006	DBLP DOI BibTeX RDF
29	Jason Baumgartner, Hari Mony	Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies.	CHARME	2005	DBLP DOI BibTeX RDF
29	Prabhakar Kudva, Andrew Sullivan, William E. Dougherty	Measurements for structural logic synthesis optimizations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
29	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver	A Fine-Grain Phased Logic CPU.	ISVLSI	2003	DBLP DOI BibTeX RDF
29	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver	A Coarse-Grain Phased Logic CPU.	ASYNC	2003	DBLP DOI BibTeX RDF
29	Prabhakar Kudva, Andrew Sullivan, William E. Dougherty	Metrics for structural logic synthesis.	ICCAD	2002	DBLP DOI BibTeX RDF
29	Phillip Christie	Rent exponent prediction methods.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
29	Jennifer L. White, Anthony S. Wojcik, Moon-Jung Chung, Travis E. Doom	Candidate subcircuits for functional module identification in logic circuits.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
29	Chia-Pin R. Liu, Jacob A. Abraham	Transistor Level Synthesis for Static CMOS Combinational Circuits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
29	Norio Kuji	Guided-Probe Diagnosis of Macro-Cell-Designed LSI Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Electron beam testers, Guided-probe diagnosis, Memory-macro cells, Logic-behavior models, Logic simulation
29	Jason Cong, Wilburt Labio, Narayanan Shivakumar	Multiway VLSI circuit partitioning based on dual net representation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
29	Jason Cong, Wilburt Labio, Narayanan Shivakumar	Multi-way VLSI circuit partitioning based on dual net representation.	ICCAD	1994	DBLP DOI BibTeX RDF
29	Lars W. Hagen, Andrew B. Kahng	New spectral methods for ratio cut partitioning and clustering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
22	Ajay Kumar Verma, Paolo Ienne	Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.	ASP-DAC	2007	DBLP DOI BibTeX RDF	multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers
21	Inseong Jeon, Hyunho Park, Taehwan Yoon, Hanwool Jeong	High Efficiency Variation-Aware SRAM Timing Characterization via Machine-Learning-Assisted Netlist Extraction.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
21	Zhishang Luo, Truong Son Hy, Puoya Tabaghi, Donghyeon Koh, Michaël Defferrard, Elahe Rezaei, Ryan Carey, W. Rhett Davis, Rajeev Jain, Yusu Wang 0001	DE-HNN: An effective neural model for Circuit Netlist representation.	CoRR	2024	DBLP DOI BibTeX RDF
21	Gus Henry Smith, Zachary D. Sisco, Thanawat Techaumnuaiwit, Jingtao Xia, Vishal Canumalla, Andrew Cheung, Zachary Tatlock, Chandrakana Nandi, Jonathan Balkind	There and Back Again: A Netlist's Tale with Much Egraphin'.	CoRR	2024	DBLP DOI BibTeX RDF
21	Zhishang Luo, Truong Son Hy, Puoya Tabaghi, Michaël Defferrard, Elahe Rezaei, Ryan Carey, W. Rhett Davis, Rajeev Jain, Yusu Wang 0001	DE-HNN: An effective neural model for Circuit Netlist representation.	AISTATS	2024	DBLP BibTeX RDF
21	Yiding Wei, Jun Liu, Dengbao Sun, Guodong Su, Junchao Wang	From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits.	Symmetry	2023	DBLP DOI BibTeX RDF
21	Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor	FSMx-Ultra: Finite State Machine Extraction From Gate-Level Netlist for Security Assessment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
21	Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu	TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection.	CoRR	2023	DBLP DOI BibTeX RDF
21	Ann Jelyn Tiempo, Yong-Jin Jeong	Implementing Region-Based Segmentation for Hardware Trojan Detection in FPGAs Cell-Level Netlist.	IEICE Trans. Inf. Syst.	2023	DBLP DOI BibTeX RDF
21	Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor	ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
21	Xuenong Hong, Tong Lin 0001, Yiqiong Shi, Bah-Hwee Gwee	GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning.	IEEE Trans. Artif. Intell.	2023	DBLP DOI BibTeX RDF
21	Madhav Nair, Rajat Sadhukhan, Hammond Pearce, Debdeep Mukhopadhyay, Ramesh Karri	Netlist Whisperer: AI and NLP Fight Circuit Leakage!	ASHES@CCS	2023	DBLP DOI BibTeX RDF
21	Helmut Graeb, Markus Leibl	Learning from the Implicit Functional Hierarchy in an Analog Netlist.	ISPD	2023	DBLP DOI BibTeX RDF
21	Manuel Jirsak, Henning Siemen, Jonas Lienke, Martin Grabmann, Eric Schäfer, Georg Gläser	Under Cover: On-FPGA Coverage Monitoring by Netlist Instrumentation.	SMACD	2023	DBLP DOI BibTeX RDF
21	Kyungjun Min, Seongbin Kwon, Sung-Yun Lee, Dohun Kim, Sunghye Park, Seokhyeong Kang	ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks.	ICCAD	2023	DBLP DOI BibTeX RDF
21	Su Zheng, Lancheng Zou, Peng Xu, Siting Liu 0002, Bei Yu 0001, Martin D. F. Wong	Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction.	ICCAD	2023	DBLP DOI BibTeX RDF
21	Animesh Basak Chowdhury, Jitendra Bhandari, Luca Collini, Ramesh Karri, Benjamin Tan 0001, Siddharth Garg	ConVERTS: Contrastively Learning Structurally InVariant Netlist Representations.	MLCAD	2023	DBLP DOI BibTeX RDF
21	Julien Rodriguez, François Galea, François Pellegrini, Lilia Zaourar	A Hypergraph Model and Associated Optimization Strategies for Path Length-Driven Netlist Partitioning.	ICCS (3)	2023	DBLP DOI BibTeX RDF
21	Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu	TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection.	ISCAS	2023	DBLP DOI BibTeX RDF
21	Liang Hong, Ge Zhu, Jing Zhou, Xuefei Li, Ziyi Chen, Wei Hu 0008	Hunting for Hardware Trojan in Gate Netlist: A Stacking Ensemble Learning Perspective.	ITC-Asia	2023	DBLP DOI BibTeX RDF
21	James Geist, Travis Meade, Shaojie Zhang, Yier Jin	NetViz: A Tool for Netlist Security Visualization.	ISQED	2023	DBLP DOI BibTeX RDF
21	Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor	ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction.	ITC	2023	DBLP DOI BibTeX RDF
21	Waqas Uzair, Douglas Chai, Alexander Rassau	Automated Netlist Generation from Offline Hand-Drawn Circuit Diagrams.	DICTA	2023	DBLP DOI BibTeX RDF
21	Hassan Salmani	Gradual-N-Justification (GNJ) to Reduce False-Positive Hardware Trojan Detection in Gate-Level Netlist.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
21	Shichao Yu, Chongyan Gu, Weiqiang Liu 0001, Máire O'Neill	Deep Learning-Based Hardware Trojan Detection With Block-Based Netlist Information Extraction.	IEEE Trans. Emerg. Top. Comput.	2022	DBLP DOI BibTeX RDF
21	Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor	FSMx-Ultra: Finite State Machine Extraction from Gate-Level Netlist for Security Assessment.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
21	Chi-Wei Chen, Pei-Yu Lo, Wei-Ting Hsu, Chih-Wei Chen, Chin-Wei Tien, Sy-Yen Kuo	A Hardware Trojan Insertion Framework against Gate-Level Netlist Structural Feature-based and SCOAP-based Detection.	MWSCAS	2022	DBLP DOI BibTeX RDF
21	Erwei Wang, James J. Davis 0001, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah	Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference.	FPGA	2022	DBLP DOI BibTeX RDF
21	Alexander Hepp, Johanna Baehr, Georg Sigl	Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs.	DATE	2022	DBLP DOI BibTeX RDF
21	Jeffrey Todd McDonald, Jennifer Parnell, Todd R. Andel, Samuel H. Russ	Effectiveness of Adversarial Component Recovery in Protected Netlist Circuit Designs.	SECRYPT	2022	DBLP DOI BibTeX RDF
21	Marie Auffret, Erwei Wang, James J. Davis 0001	FPL Demo: Logic Shrinkage: A Neural Architecture Search-Based Approach to FPGA Netlist Generation.	FPL	2022	DBLP DOI BibTeX RDF
21	Brunno A. Abreu, Guilherme Paim, Jorge Castro-Godínez, Mateus Grellert, Sergio Bampi	On the Netlist Gate-level Pruning for Tree-based Machine Learning Accelerators.	LASCAS	2022	DBLP DOI BibTeX RDF
21	Ahmet Emre Sertdemir, Mehmet Besenk, Tugba Dalyan, Y. Daghan Gokdel, Engin Afacan	From Image to Simulation: An ANN-based Automatic Circuit Netlist Generator (Img2Sim).	SMACD	2022	DBLP DOI BibTeX RDF
21	Reilly McKendrick, Corey Simpson, Brent Nelson, Jeffrey Goeders	Leveraging FPGA Primitives to Improve Word Reconstruction during Netlist Reverse Engineering.	FPT	2022	DBLP DOI BibTeX RDF
21	Raveena Raikar, Dirk Stroobandt	Multi-Die Heterogeneous FPGAs: How Balanced Should Netlist Partitioning be?	SLIP	2022	DBLP DOI BibTeX RDF
21	Guangwei Zhao, Kaveh Shamsi	Graph Neural Network based Netlist Operator Detection under Circuit Rewriting.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
21	Hassan Salmani	The Improved COTD Technique for Hardware Trojan Detection in Gate-level Netlist.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
21	Rasheed Kibria, Nusrat Farzana, Farimah Farahmandi, Mark M. Tehranipoor	FSMx: Finite State Machine Extraction from Flattened Netlist With Application to Security.	VTS	2022	DBLP DOI BibTeX RDF
21	Shamminuj Aktar, Abdel-Hameed A. Badawy, Nandakishore Santhi	Quantum Netlist Compiler (QNC).	HPEC	2022	DBLP DOI BibTeX RDF
21	Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu 0001, Tsung-Yi Ho, Bei Yu 0001, Yu Huang	Functionality matters in netlist representation learning.	DAC	2022	DBLP DOI BibTeX RDF
21	Da Meng, Yali Zheng	Circuit Partitioning for PCB Netlist Based on Net Attributes.	ICMLC	2022	DBLP DOI BibTeX RDF
21	Jorge Castro-Godínez, Humberto Barrantes-García, Muhammad Shafique 0001, Jörg Henkel	AxLS: A Framework for Approximate Logic Synthesis Based on Netlist Transformations.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
21	Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos	Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2021	DBLP DOI BibTeX RDF
21	Anindan Mondal, Rajesh Kumar Biswal, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen	Hardware Trojan Free Netlist Identification: A Clustering Approach.	J. Electron. Test.	2021	DBLP DOI BibTeX RDF