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Publication years (Num. hits)
1964-1975 (17) 1976-1979 (19) 1980-1981 (20) 1982 (32) 1983-1984 (52) 1985 (44) 1986 (53) 1987 (37) 1988 (84) 1989 (74) 1990 (79) 1991 (89) 1992 (105) 1993 (125) 1994 (151) 1995 (196) 1996 (207) 1997 (253) 1998 (312) 1999 (563) 2000 (546) 2001 (619) 2002 (886) 2003 (1286) 2004 (1325) 2005 (1712) 2006 (2055) 2007 (1970) 2008 (1863) 2009 (1404) 2010 (1146) 2011 (1135) 2012 (1092) 2013 (1002) 2014 (1092) 2015 (1090) 2016 (1004) 2017 (1032) 2018 (988) 2019 (1039) 2020 (742) 2021 (835) 2022 (785) 2023 (848) 2024 (131)
Publication types (Num. hits)
article(8668) book(35) data(6) incollection(102) inproceedings(20838) phdthesis(381) proceedings(109)
Venues (Conferences, Journals, ...)
ISCAS(889) SoCC(852) DATE(679) DAC(647) IEEE Trans. Very Large Scale I...(612) VLSI-SOC(601) IEEE Trans. Comput. Aided Des....(573) IEEE J. Solid State Circuits(503) ASP-DAC(423) MCSoC(421) CoRR(413) ReCoSoC(411) NOCS(397) SoC(360) ISQED(354) VLSI Design(324) More (+10 of total 2176)
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Results
Found 30195 publication records. Showing 30139 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
76H. Bernhard Pogge The next chip challenge: effective methods for viable mixed technology SoCs. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF SoCs (System on a Chip), chip fabrication methods, chip subsector concepts, chip/packing integration
65Guy Even, Ami Litman Overcoming chip-to-chip delays and clock skews. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews
54Noel Eisley, Li-Shiuan Peh, Li Shang Leveraging on-chip networks for data cache migration in chip multiprocessors. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF network-driven computing, interconnection network, CMP, chip-multiprocessor, migration
51Jaime H. Moreno Chip-level integration: the new frontier for microprocessor architecture. Search on Bibsonomy SPAA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF chip-level integration, microprocessor architecture
50Partha Kundu, Li-Shiuan Peh Guest Editors' Introduction: On-Chip Interconnects for Multicores. Search on Bibsonomy IEEE Micro The full citation details ... 2007 DBLP  DOI  BibTeX  RDF embedded systems, system on chip, network on chip, multicore architectures, on-chip interconnection networks
48Shirish Bahirat, Sudeep Pasricha Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. Search on Bibsonomy CODES+ISSS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF photonic interconnect, network-on-chip, chip multiprocessor
47Rob Aitken, Krisztián Flautner, John Goodacre High-Performance Multiprocessor System on Chip: Trends in Chip Architecture for the Mass Market. Search on Bibsonomy Multiprocessor System-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
47Suboh A. Suboh, Mohamed Bakhouya, Tarek A. El-Ghazawi Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network. Search on Bibsonomy NOCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF System on Chip, Network on Chip, Modeling and simulation, On Chip Interconnects
46Tobias Bjerregaard, Shankar Mahadevan A survey of research and practices of Network-on-chip. Search on Bibsonomy ACM Comput. Surv. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions
45Luciano Lavagno, Sujit Dey, Rajesh K. Gupta 0001 Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
45T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael Faulty chip identification in a multi chip module system. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF faulty chip identification, multi chip module, linear space compressor, field programmable gate array, fault diagnosis, data compression, data compression, built-in self test, built-in self test, integrated circuit testing, fault detection, comparator, multichip modules
45Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese Impact of Chip-Level Integration on Performance of OLTP Workloads. Search on Bibsonomy HPCA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF chip-level integration, database workloads, multiprocessors, memory system performance
44Roman L. Lysecky, Frank Vahid On-chip logic minimization. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF on-chip logic minimization, on-chip synthesis, embedded systems, dynamic optimization, system-on-a-chip, logic minimization
43Michael Ferdman, Babak Falsafi Last-Touch Correlated Data Streaming. Search on Bibsonomy ISPASS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF predictor lookahead, last-touch correlated data streaming, address-correlating predictor, cache block address identification, correlation data storage, program active memory footprint, prediction lookahead, off-chip correlation data lookup, scalable on-chip table, low-latency lookup, on-chip storage, last-touch predictor, prefetch, superscalar processor, cycle-accurate simulation
42Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan Compiler directed network-on-chip reliability enhancement for chip multiprocessors. Search on Bibsonomy LCTES The full citation details ... 2010 DBLP  DOI  BibTeX  RDF reliability, compiler, noc, chip multiprocessors
42Daniel Wiklund, Dake Liu Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip. Search on Bibsonomy IWSOC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF basestation, scheduling, Network on chip, 3G, WCDMA
42Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF power distribution grids, power noise, decoupling capacitors, power distribution systems
42Hyung Gyu Lee, Naehyuck Chang, Ümit Y. Ogras, Radu Marculescu On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF MPEG-2 encoder, system-on-chip, Networks-on-chip, FPGA prototype, point-to-point
42John Kim Low-cost router microarchitecture for on-chip networks. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF router microarchitecture, complexity, on-chip network
42Louis Scheffer An overview of on-chip interconnect variation. Search on Bibsonomy SLIP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF causes of variability, on-chip variation, design rules
42Mohamed Shalan, Vincent John Mooney III Hardware support for real-time embedded multiprocessor system-on-a-chip memory management. Search on Bibsonomy CODES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Atalanta, SoCDMMU, real-time operating systems., two-level memory management, real-time systems, embedded systems, System-on-a-Chip, dynamic memory management
41Andreas Hansson 0001, Kees Goossens An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. Search on Bibsonomy CODES+ISSS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF system on chip, network on chip, programming model, protocol stack
41Ricardo Reis 0001 Design Tools and Methods for Chip Physical Design. Search on Bibsonomy Multiprocessor System-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
41Lionel Torres, Pascal Benoit, Gilles Sassatelli, Michel Robert, Fabien Clermidy, Diego Puschini An Introduction to Multi-Core System on Chip - Trends and Challenges. Search on Bibsonomy Multiprocessor System-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
41Diana Göhringer, Michael Hübner 0001, Jürgen Becker 0001 Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support. Search on Bibsonomy Multiprocessor System-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
41Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. Search on Bibsonomy Low Power Networks-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
41Sai-Wang Tam, Eran Socher, Mau-Chung Frank Chang, Jason Cong, Glenn D. Reinman RF-Interconnect for Future Network-On-Chip. Search on Bibsonomy Low Power Networks-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
41Yuho Jin, Ki Hwan Yum, Eun Jung Kim 0001 Adaptive Data Compression for Low-Power On-Chip Networks. Search on Bibsonomy Low Power Networks-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
41Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania Application-Specific Routing Algorithms for Low Power Network on Chip Design. Search on Bibsonomy Low Power Networks-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
41Mark A. Anders 0001, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar Y. Borkar Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections. Search on Bibsonomy Low Power Networks-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
41Miltos D. Grammatikakis, Marcello Coppola, Fabrizio Sensini Software for Multiprocessor Networks on Chip. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Shashi Kumar On Packet Switched Networks for On-Chip Communication. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Axel Jantsch, Hannu Tenhunen Will Networks on Chip Close the Productivity Gap? Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Kees Goossens, John Dielissen, Jef L. van Meerbergen, Peter Poplavko, Andrei Radulescu, Edwin Rijpkema, Erwin Waterlander, Paul Wielage Guaranteeing the Quality of Services in Networks on Chip. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Raimund Ubar, Jaan Raik Testing Strategies for Networks on Chip. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Ilkka Saastamoinen, David A. Sigüenza-Tortosa, Jari Nurmi An IP-Based On-Chip Packet-Switched Network. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Johnny Öberg Clocking Strategies for Networks-on-Chip. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos A buffered crossbar-based chip interconnection framework supporting quality of service. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF chip interconnect, quality of service, system on chip, network on chip, multi-processor, buffered crossbar
41Roman L. Lysecky, Frank Vahid A codesigned on-chip logic minimizer. Search on Bibsonomy CODES+ISSS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF embedded CAD, on-chip logic minimization, on-chip synthesis, embedded systems, dynamic optimization, system-on-a-chip, hardware/software codesign, logic minimization
41Mario Kovac, N. Ranganathan JAGUAR: a high speed VLSI chip for JPEG image compression standard. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF JAGUAR, high speed VLSI chip, JPEG image compression standard, pipelined single chip VLSI architecture, entropy encoder, clock rate, input rate, CMOS VLSI chip, Huffman entropy coding, 1024 pixel, 1048576 pixel, VLSI, parallel architectures, data compression, image coding, discrete cosine transforms, discrete cosine transform, pipeline processing, color images, image colour analysis, digital signal processing chips, Huffman codes, high throughput, CMOS digital integrated circuits, entropy codes, 100 MHz
41Chen Wang 0001, Jianhua Xuan, Li Chen 0018, Po Zhao, Yue Joseph Wang, Robert Clarke, Eric P. Hoffman Integrative Network Component Analysis for Regulatory Network Reconstruction. Search on Bibsonomy ISBRA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Network component analysis, ChIP-on-chip, muscle regeneration, gene regulatory networks, microarray data analysis
39Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF system design, data cache, data partitioning, system synthesis, scratch-pad memory, on-chip memory, memory synthesis
39Li Shang, Li-Shiuan Peh, Amit Kumar 0002, Niraj K. Jha Thermal Modeling, Characterization and Management of On-Chip Networks. Search on Bibsonomy MICRO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Björn Osterloh, Harald Michalik, Björn Fiethe SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs. Search on Bibsonomy ARCS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF SoCWire, dynamic reconfigurable system, Sytem-on-Chip, Network-on-Chip, SRAM-based FPGA, VMC
39Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar A design methodology for application-specific networks-on-chip. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF regular topology, architecture, methodology, networks-on-chip, Application-specific
39Sung-Hsien Sun, Shie-Jue Lee A JPEG Chip for Image Compression and Decompression. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF image compression/decompression, standard cell design, FPGA, VHDL, CAD tools, VLSI chip
39Xiaohong Jiang 0001, Susumu Horiguchi, Yue Hao Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core. Search on Bibsonomy DFT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
38Antonio Flores, Juan L. Aragón, Manuel E. Acacio An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. Search on Bibsonomy J. Supercomput. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Power dissipation model, Microarchitectural level simulator, Heterogeneus on-chip interconnection network, Chip-multiprocessor, Parallel scientific applications
38Hyunmin Kim, Katherina J. Kechris, Lawrence Hunter Mining Discriminative Distance Context of Transcription Factor Binding Sites on ChIP Enriched Regions. Search on Bibsonomy ISBRA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF ChIP-chip data analysis, ensemble learning, transcription factor
38Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter Combined DRAM and logic chip for massively parallel systems. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits
38Thomas William Ainsworth, Timothy Mark Pinkston On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus. Search on Bibsonomy NOCS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Element Interconnect Bus, heterogeneous multicore, network characterization, interconnection networks, network-on-chip, Cell Broadband Engine, on-chip network, performance bottleneck
37Xudong Shi 0003, Feiqi Su, Jih-Kwon Peir, Ye Xia 0001, Zhen Yang Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility. Search on Bibsonomy ISPASS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF multiple cache organization, single-pass simulation, on-chip storage space, on-chip cache capacity, single-pass stack simulation, global stack, shared stack, per-core private stack, single simulation pass, average memory access time, chip-multiprocessor, data replication, data accessibility, abstract model, reuse distances
37Federico Rota, Shantanu Dutt, Sahithi Krishna Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Woo Hyung Lee, Sanjay Pant, David T. Blaauw Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
36Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF voltage/frequency scaling, embedded systems, design space, power-performance trade-offs
36Yuan Cao 0003, Wanyi Liu, Yue Zheng, Shuai Chen, Jing Ye 0001, Lei Qian, Chip-Hong Chang A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
36Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC)
36Marcelo Daniel Berejuck, César Albenes Zeferino Adding mechanisms for QoS to a network-on-chip. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF FPGA, systems-on-chip, networks-on-chip
36Donald J. Dent Project Management for System-on-Chip Using Multi-Chip Modules. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Multi-Chip Modules, System-on Chip, Project Management
36Charles M. Higgins, Christof Koch Multi-Chip Neuromorphic Motion Processing. Search on Bibsonomy ARVLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF vision chip, AER, motion, disparity, neuromorphic
35Suboh A. Suboh, Mohamed Bakhouya, Jaafar Gaber, Tarek A. El-Ghazawi An interconnection architecture for network-on-chip systems. Search on Bibsonomy Telecommun. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Switching and routing, Network on chip, Network analysis, Modeling and simulation, On-chip interconnects
35Xinping Zhu, Sharad Malik A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF on-chip communication architecture, network-on-chip, multiprocessor system, object-oriented modeling, packet-switching network, design exploration, bus, Retargetable simulation
35Baojun Qiao, Feng Shi 0009, Weixing Ji THIN: A New Hierarchical Interconnection Network-on-Chip for SOC. Search on Bibsonomy ICA3PP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF multicast, System-on-Chip, Network-on-Chip, network topology
35Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF architecture, Systems-on-chip, mapping, networks on chip, synthesis
35Kanishka Lahiri, Anand Raghunathan Power analysis of system-level on-chip communication architectures. Search on Bibsonomy CODES+ISSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF system-on-chip, network-on-chip, low-power design, power analysis, communication architectures
35John D. Owens, William J. Dally, Ron Ho, Doddaballapur Narasimha-Murthy Jayasimha, Stephen W. Keckler, Li-Shiuan Peh Research Challenges for On-Chip Interconnection Networks. Search on Bibsonomy IEEE Micro The full citation details ... 2007 DBLP  DOI  BibTeX  RDF embedded systems, system on chip, network on chip, multicore architectures, on-chip interconnection networks
35Noel Eisley, Vassos Soteriou, Li-Shiuan Peh High-level power analysis for multi-core chips. Search on Bibsonomy CASES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF simulation, chip multiprocessor (CMP), multi-core, power analysis, system-on-a-chip (SoC)
35Abderrahim Doumar, Hideo Ito Testing approach within FPGA-based fault tolerant systems. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
34Roman Obermaisser, Hubert Kraut, Christian El Salloum A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR. Search on Bibsonomy EDCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Paul Ampadu, Bo Fu, David Wolpert 0001, Qiaoyan Yu Adaptive Voltage Control for Energy-Efficient NoC Links. Search on Bibsonomy Low Power Networks-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Stanislavs Golubcovs, Alex Yakovlev Asynchronous Communications for NoCs. Search on Bibsonomy Low Power Networks-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli Design and Analysis of NoCs for Low-Power 2D and 3D SoCs. Search on Bibsonomy Low Power Networks-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study. Search on Bibsonomy Low Power Networks-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Jung Ho Ahn, Raymond G. Beausoleil, Nathan L. Binkert, Al Davis, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, Matteo Monchiero, Naveen Muralimanohar, Robert Schreiber, Dana Vantrease CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study. Search on Bibsonomy Low Power Networks-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Michael J. Anderson, Bryan Catanzaro, Jike Chong, Ekaterina Gonina, Kurt Keutzer, Chao-Yue Lai, Mark Murphy, Bor-Yiing Su, Narayanan Sundaram PALLAS: Mapping Applications onto Manycore. Search on Bibsonomy Multiprocessor System-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Jürgen Teich, Jörg Henkel, Andreas Herkersdorf, Doris Schmitt-Landsiedel, Wolfgang Schröder-Preikschat, Gregor Snelting Invasive Computing: An Overview. Search on Bibsonomy Multiprocessor System-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Benny Akesson, Anca Mariana Molnos, Andreas Hansson 0001, Jude Angelo Ambrose, Kees Goossens Composability and Predictability for Independent Application Development, Verification, and Execution. Search on Bibsonomy Multiprocessor System-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Dac Pham, Jim Holt, Sanjay Deshpande Embedded Multicore Systems: Design Challenges and Opportunities. Search on Bibsonomy Multiprocessor System-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Miltos D. Grammatikakis, George Kornaros, Marcello Coppola Power-Aware Multicore SoC and NoC Design. Search on Bibsonomy Multiprocessor System-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Rakesh Kumar 0002, Timothy G. Mattson, Gilles Pokam, Rob F. Van der Wijngaart The Case for Message Passing on Many-Core Chips. Search on Bibsonomy Multiprocessor System-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Andreas Herkersdorf, Andreas Lankes, Michael Meitinger, Rainer Ohlendorf, Stefan Wallentowitz, Thomas Wild, Johannes Zeppenfeld Hardware Support for Efficient Resource Utilization in Manycore Processor Systems. Search on Bibsonomy Multiprocessor System-on-Chip The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Juha-Pekka Soininen, Hannu Heusala A Design Methodology for NOC-Based Systems. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Eric Verhulst Beyond the Von Neumann Machine. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Martti Forsell A Parallel Computer as a NOC Region. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Andrew Mihal, Kurt Keutzer Mapping Concurrent Applications onto Architectural Platforms. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Davide Bertozzi, Luca Benini, Giovanni De Micheli Energy-Reliability trade-Off for NoCs. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Sungjoo Yoo, Gabriela Nicolescu, Iuliana Bacivarov, Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya Multi-Level Software Validation for NoC. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Zhonghai Lu, Raimo Haukilahti NoC Application Programming Interfaces. Search on Bibsonomy Networks on Chip The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
33Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger On-Chip Interconnection Networks of the TRIPS Chip. Search on Bibsonomy IEEE Micro The full citation details ... 2007 DBLP  DOI  BibTeX  RDF communication, networking, distributed architectures, packet-switching networks, multicore architectures, on-chip interconnection networks
33Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF data compression, chip multiprocessors, optimizing compiler
33Mahmut T. Kandemir, Ozcan Ozturk 0001, Mustafa Karaköy Dynamic on-chip memory management for chip multiprocessors. Search on Bibsonomy CASES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF chip multiprocessors, optimizing compiler, memory bank
33Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos Practical off-chip meta-data for temporal memory streaming. Search on Bibsonomy HPCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
33Xu Wang, Ge Gan, Joseph B. Manzano, Dongrui Fan, Shuxu Guo A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor. Search on Bibsonomy ICPADS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo Low-power network-on-chip for high-performance SoC design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Zhao Zhang 0010, Zhichun Zhu, Xiaodong Zhang 0001 Design and Optimization of Large Size and Low Overhead Off-Chip Caches. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
33Jörg Henkel, Wayne H. Wolf, Srimat T. Chakradhar On-chip networks: A scalable, communication-centric embedded system design paradigm. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
33Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Andreas G. Andreou Programmable Kernel Analog VLSI Convolution Chip for Real Time Vision Processing. Search on Bibsonomy IJCNN (4) The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
33Duo Ding, David Z. Pan OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture. Search on Bibsonomy SLIP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF photonic networks-on-chip, low power, computer aided design, high performance
33James M. Baker Jr., Brian T. Gold, Mark Bucciero, Sidney Bennett, Rajneesh Mahajan, Priyadarshini Ramachandran, Jignesh Shah SCMP: A Single-Chip Message-Passing Parallel Computer. Search on Bibsonomy J. Supercomput. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF single-chip parallel computers, parallel architecture, high-performance computing, computer architecture, embedded computing
33Sudarshan Banerjee, Nikil D. Dutt FIFO power optimization for on-chip networks. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF wide flits, low power design, shared memory, switches, FIFO, on-chip networks
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