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Found 531 publication records. Showing 531 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
66 | Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes 0001, Everton Carara |
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. |
SBCCI |
2003 |
DBLP DOI BibTeX RDF |
transaction level, VHDL, SystemC, System modeling, register transfer level |
62 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Register-transfer level estimation techniques for switching activity and power consumption. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs |
61 | Ramesh Karri, Balakrishnan Iyer |
Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
Concurrent error detection, register transfer level, on line testing |
60 | Rajesh Gupta 0003, Melvin A. Breuer |
Partial scan design of register-transfer level circuits. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
serial scan design, I-paths, design for testability, register-transfer level designs, balanced structures, partial scan design |
59 | Ramesh Karri, Balakrishnan Iyer, Israel Koren |
Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
59 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
A design-for-testability technique for register-transfer level circuits using control/data flow extraction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
59 | Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy |
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
MUSTC-testing, multi-stage-combinational test, control paths, signal types, module level pre-computed test sets, scheduling, logic testing, integrated circuit testing, combinational circuits, automatic testing, automatic test, register-transfer level, test scheduling, data-paths |
56 | Han Liang, Piyush Mishra, Kaijie Wu 0001 |
Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Concurrent error detection, register-transfer level, single-event upsets, hardware redundancy |
49 | Jason Cong, Yiping Fan, Junjuan Xu |
Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
distributed register file, Behavioral synthesis, resource binding |
46 | Matthias Mutz |
Register Transfer Level VHDL Models without Clocks. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
VHDL RT subset, register transfer level models |
46 | Vijay Pitchumani, Edward P. Stabler |
Verification of Register Transfer Level Parallel Control Sequences. |
IEEE Trans. Computers |
1985 |
DBLP DOI BibTeX RDF |
critical region, parallel control sequence, Assertion, register transfer level, shared resource, clock cycle, auxiliary variable, verification condition |
46 | Vijay Pitchumani, Edward P. Stabler |
An Inductive Assertion Method for Register Transfer Level Design Verification. |
IEEE Trans. Computers |
1983 |
DBLP DOI BibTeX RDF |
inductive assertion method, synchronous logic, theorem proving, Assertions, predicate calculus, register transfer level design, verification condition |
45 | Jay K. Adams, John Alan Miller, Donald E. Thomas |
Execution-time profiling for multiple-process behavioral synthesis. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model |
44 | Jason Cong, Yiping Fan, Wei Jiang |
Platform-based resource binding using a distributed register-file microarchitecture. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
distributed register file, behavior synthesis, resource binding |
42 | Joan Carletta, Christos A. Papachristou |
Structural constraints for circular self-test paths. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits |
41 | Xiaowei Li 0001, Toshimitsu Masuzawa, Hideo Fujiwara |
Strong self-testability for data paths high-level synthesis. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
self-testability, testability constraints, interconnection assignment, test resources reusability, high level synthesis, high-level synthesis, design for testability, register transfer level, data flow graphs, data paths, register assignment |
40 | Li Shen 0002 |
VFSim: Concurrent Fault Simulation at Register Transfer Level. |
J. Comput. Sci. Technol. |
2005 |
DBLP DOI BibTeX RDF |
concurrent fault simulation, fault model, RTL, Verilog, high-level testing, circuit modeling |
40 | Zebo Peng, Krzysztof Kuchcinski |
Automated transformation of algorithms into register-transfer level implementations. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
40 | Frank Mayer, Albrecht P. Stroele |
A Versatile BIST Technique Combining Test Registers and Accumulators. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
test register, built-in self-test, register-transfer level, accumulator |
39 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits |
38 | Thomas Bräunl |
Register-Transfer Level Simulation. |
MASCOTS |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Jaan Raik, Raimund Ubar |
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
hierarchical test pattern generation, sequential circuits, register-transfer level, decision diagrams |
37 | Min Xu, Fadi J. Kurdahi |
Layout-Driven RTL Binding Techniques for High-Level Synthesis. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
layout-driven register-transfer-level, binding techniques, chip level implementation, high level synthesis, high-level synthesis, design process |
36 | Yu Huang 0005, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy |
Synthesis of Scan Chains for Netlist Descriptions at RT-Level. |
J. Electron. Test. |
2002 |
DBLP DOI BibTeX RDF |
scan synthesis, design for testability (DFT), register transfer level (RTL) |
36 | Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri |
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Amin Asghari, Seied Ahmad Motamedi, Sepehr Attarchi |
Effective RTL Method to Develop On-Line Self-Test Routine for the Processors Using the Wavelet Transform. |
ACIS-ICIS |
2008 |
DBLP DOI BibTeX RDF |
On-line low-cost testing, Spectral test pattern generating, Software-based self-testing (SBST), Register transfer level (RTL), Processor testing |
35 | Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham |
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Register Transfer Level implementation, Verification, Hardware Description Languages, arithmetic logic unit |
35 | Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan |
Power emulation: a new paradigm for power estimation. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels |
35 | Zhigang Yin, Yinghua Min, Xiaowei Li 0001 |
An Approach to RTL Fault Extraction and Test Generation. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
ATPG (Automatic Test Pattern Generation), RTL (Register Transfer Level), Fault |
35 | Zdenek Kotásek, F. Zboril |
RT level testability analysis to reduce test application time. |
EUROMICRO |
1997 |
DBLP DOI BibTeX RDF |
register transfer level testability analysis, RTL element classification, RTL circuit transformation, labelled directed graph, PROLOG environment, implementation principles, logic testing, test application time reduction |
35 | Zijian Zhou 0001, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin |
Partitioning transition relations efficiently and automatically. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
automatic partitioning, state transition relations, abstract implicit state enumeration procedure, automatic verification method, graph theory, finite state machines, logic CAD, state estimation, logic partitioning, extended finite state machines, register transfer level designs, multiway decision graphs |
35 | Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
A test evaluation technique for VLSI circuits using register-transfer level fault modeling. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Ramesh Karri, Kaijie Wu 0001 |
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Matthias Müller 0002, Andreas Wortmann 0002, Dominik Mader, Sven Simon 0001 |
Register Isolation for Synthesizable Register Files. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Chun-hong Chen, Chi-Ying Tsui |
Towards the capability of providing power-area-delay trade-off at the register transfer level. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Kai Hylla |
Bridging the gap between precise RT-level power/timing estimation and fast high-level simulation: a method for automatically identifying and characterising combinational macros in synchronous sequential systems at register-transfer level and subsequent executable high-level model generation with respect to non-functional properties. |
|
2014 |
RDF |
|
32 | Loganathan Lingappan, Niraj K. Jha |
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Bruce S. Greene, Samiha Mourad |
Partial Scan Testing on the Register-Transfer Level. |
J. Electron. Test. |
2002 |
DBLP DOI BibTeX RDF |
RT-level, fault coverage, partial scan, scan design, graph reduction |
32 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO: regular expression-based register-transfer level testability analysis and optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi |
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Loganathan Lingappan, Niraj K. Jha |
Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri |
Delay Constrained Register Transfer Level Dynamic Power Estimation. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Ho Fai Ko, Qiang Xu 0001, Nicola Nicolici |
Register-transfer level functional scan for hierarchical designs. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Register transfer level power optimization with emphasis on glitch analysis and reduction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Jiong Luo, Lin Zhong 0001, Yunsi Fei, Niraj K. Jha |
Register binding-based RTL power management for control-flow intensive designs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik |
A BIST scheme for RTL circuits based on symbolic testabilityanalysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Héctor Navarro, Saeid Nooshabadi, Juan A. Montiel-Nelson, Victor Navarro-Botello, Javier Sosa, José C. García 0001 |
A geometric approach to register transfer level satisfiability. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Felipe Machado, Teresa Riesgo, Yago Torroja |
Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
activity estimation, CAD, VHDL, BDD, power estimation, RTL, Switching activity, circuit partition, digital circuit design |
30 | Anish Muttreja, Srivaths Ravi 0001, Niraj K. Jha |
Variability-Tolerant Register-Transfer Level Synthesis. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Richard Stern, Nikhil Joshi, Kaijie Wu 0001, Ramesh Karri |
Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations. |
FDTC |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara |
A DFT Method for Time Expansion Model at Register Transfer Level. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Kaijie Wu 0001, Ramesh Karri |
Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Indradeep Ghosh, Krishna Sekar, Vamsi Boppana |
Design for Verification at the Register Transfer Level. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Jens Schönherr, Bernd Straube |
Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Laurence Tianruo Yang, Zebo Peng |
An Improved Register-Transfer Level Functional Partitioning Approach for Testability. |
EUROMICRO |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Johannes Steensma, Francky Catthoor, Hugo De Man |
Partial scan and symbolic test at the register-transfer level. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
data path test, partial scan selection, symbolic test pattern generation, partial scan application schemes |
30 | Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka |
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. |
CAV |
1990 |
DBLP DOI BibTeX RDF |
|
30 | Rolf Ernst, S. Sutarwala, J.-Y. Jou, M. Tong |
Simulation based verification of register-transfer level behavioral synthesis tools. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
26 | Rami Beidas, Jianwen Zhu |
Scalable interprocedural register allocation for high level synthesis. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Yoshichika Fujioka, Michitaka Kameyama |
Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme. |
ISOCC |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken |
The challenges of implementing fine-grained power gating. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating |
26 | K. M. Deliparaschos, F. I. Nenedakis, Spyros G. Tzafestas |
Design and Implementation of a Fast Digital Fuzzy Logic Controller Using FPGA Technology. |
J. Intell. Robotic Syst. |
2006 |
DBLP DOI BibTeX RDF |
digital fuzzy logic controller, odd-even method, very high-speed hardware description language, synthesis, register transfer level, place and route |
26 | Maciej J. Ciesielski, Priyank Kalla, Serkan Askar |
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
Register transfer level—design aids, arithmetic and logic structures—verification, symbolic and algebraic manipulation, verification |
26 | Guy Dupenloup, Thierry Lemeunier, Roland Mayr |
Transistor abstraction for the functional verification of FPGAs. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
cone model, logic equivalence checking, transistor abstraction, FPGA, register transfer level, multiplexer, functional verification |
26 | Jaan Raik, Tanel Nõmmeots, Raimund Ubar |
A New Testability Calculation Method to Guide RTL Test Generation. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
test pattern generation, register-transfer level, decision diagrams, testability measures |
26 | Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi |
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. |
J. Electron. Test. |
2004 |
DBLP DOI BibTeX RDF |
hierarchical fault simulation, mixed level, delta times, VHDL, register transfer level |
26 | Peter J. Osler |
Placement driven synthesis case studies on two sets of two chips: hierarchical and flat. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
synthesis, placement, application specific integrated circuit (ASIC), register transfer level (RTL), static timing analysis (STA), netlist |
26 | Mohamed Kawokgy, C. André T. Salama |
Low-power asynchronous viterbi decoder for wireless applications. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
bundled-data, four-phase, low-power, synchronous, wireless, VHDL, digital signal processing, asynchronous, register transfer level, viterbi algorithm, speed-independent, handshaking protocol |
26 | Zaher S. Andraus, Karem A. Sakallah |
Automatic abstraction and verification of verilog models. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
UCLID, logic of counter arithmetic with lambda expressions and uninter-preted functions (CLU), abstraction, register transfer level (RTL), verilog |
26 | Tomokazu Yoneda, Hideo Fujiwara |
Design for Consecutive Transparency of Cores in System-on-a-Chip. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
consecutive transparency, design for testability, system-on a chip, register transfer level, test access mechanism, consecutive testability |
26 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
Integrated test of interacting controllers and datapaths. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
built-in self-test, register transfer level, synthesis-for-testability |
26 | Huawei Li 0001, Yinghua Min, Zhongcheng Li |
An RT-Level ATPG Based on Clustering of Circuit States. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
cluster of states, automatic test pattern generation, register-transfer level, behavioral descriptions |
26 | Kavel M. Büyüksahin, Farid N. Najm |
High-level power estimation with interconnect effects. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
high-level power estimation, interconnect capacitance estimation, register transfer level (RTL) power estimation |
26 | Laurence Tianruo Yang, Zebo Peng |
Incremental Testability Analysis for Partial Scan Selection and Design Transformations. |
J. Electron. Test. |
1999 |
DBLP DOI BibTeX RDF |
incremental testability analysis, partial scan selection, design transformation, register transfer level, high-level test synthesis |
26 | Chuck Monahan, Forrest Brewer |
Scheduling and binding bounds for RT-level symbolic execution. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
ALAP bounds, as-late-as-possible bounds, binding bounds, efficient operand mapping bound, exact scheduling problem, minimal schedule length, operand recomputation, point-to-point delays, pre-defined data path, register transfer level symbolic execution, time improvement factors, transitive memory units, processor scheduling |
26 | Joan Carletta, Christos A. Papachristou |
Testability analysis and insertion for RTL circuits based on pseudorandom BIST. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
pseudorandom BIST, indirect feedback, preprocessing transformation, word-level correlation, modeling, logic testing, probability, built-in self test, built-in self-test, integrated circuit testing, Markov processes, automatic testing, Markov model, insertion, testability analysis, test point insertion, iterative technique, RTL circuits, register transfer level circuits |
26 | Masaru Takesue |
Cache Memories for Data Flow Machines. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
data flow machines, dataflow caches, cache block replacement, cache memories, memory architecture, buffer storage, register transfer level simulator |
26 | Louis J. Hafer, Alice C. Parker |
Automated Synthesis of Digital Hardware. |
IEEE Trans. Computers |
1982 |
DBLP DOI BibTeX RDF |
hardware specification, computer-aided design, logic design, design automation, register-transfer level, hardware-descriptive language, ISP, Automated synthesis |
26 | Mario Barbacci |
A Comparison of Register Transfer Languages for Describing Computers and Digital Systems. |
IEEE Trans. Computers |
1975 |
DBLP DOI BibTeX RDF |
language properties, design automation, register transfer level, design languages, structural description, behavioral description, Asynchronous control |
25 | Lin Zhong 0001, Jiong Luo, Yunsi Fei, Niraj K. Jha |
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Matthias Müller 0002, Andreas Wortmann 0002, Sven Simon 0001, S. Wolter, Steffen Buch, Marek Wróblewski, Josef A. Nossek |
Low power register file architecture for application specific DSPs. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Nazanin Mansouri, Ranga Vemuri |
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok, Fawnizu Azmadi Hussin |
Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level. |
ATS |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Farnoud Farahmand, Duc Tri Nguyen, Viet Ba Dang, Ahmed Ferozpuri, Kris Gaj |
Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies. |
FPL |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Pradeep Kumar Biswal, Santosh Biswas |
On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams. |
Microelectron. J. |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Kaijie Wu 0001, Ramesh Karri |
Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Kaijie Wu 0001, Ramesh Karri |
Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. |
ICCAD |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Kaijie Wu 0001, Ramesh Karri |
Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. |
ITC |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Ramesh Karri, Kaijie Wu 0001 |
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. |
ITC |
2000 |
DBLP DOI BibTeX RDF |
|
24 | J. Bhasker |
Synthesis at the Register Transfer Level and the Behavioral Level. |
The VLSI Handbook |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Adam Postula, David Abramson 0001, Ziping Fang, Paul Logothetis |
A Comparison of High Level Synthesis and Register Transfer Level Design Techniques for Custom Computing Machines. |
HICSS (7) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Anand Raghunathan, Niraj K. Jha |
SCALP: an iterative-improvement-based low-power data path synthesis system. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Xin Wang, Tapani Ahonen, Jari Nurmi |
Applying CDMA Technique to Network-on-Chip. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Kamal S. Khouri, Niraj K. Jha |
Leakage Power Analysis and Reduction during Behavioral Synthesis. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
22 | K. J. Singh, P. A. Subrahmanyam |
Extracting RTL models from transistor netlists. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
Switch-level simulation, Formal verification, Extraction, RTL model |
21 | Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara |
Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Masayoshi Yoshimura, Atsuya Tsujikawa, Toshinori Hosokawa |
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha, Chandan Karfa |
SRIL: Securing Registers from Information Leakage at Register Transfer Level. |
VLSID |
2024 |
DBLP DOI BibTeX RDF |
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21 | Sarwono Sutikno, Septafiansyah Dwi Putra, Fajar Wijitrisnanto, Muhamad Erza Aminanto |
Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Dang Van Pham, Phan Cong Vinh, Bao Khang Nguyen |
Algebraic Semantics of Register Transfer Level in Synthesis of Stream Calculus-Based Computing Big Data in Livestream. |
ICTCC |
2023 |
DBLP DOI BibTeX RDF |
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