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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 531 publication records. Showing 531 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
66 | Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes 0001, Everton Carara |
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 355-, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
transaction level, VHDL, SystemC, System modeling, register transfer level |
62 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Register-transfer level estimation techniques for switching activity and power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 158-165, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs |
61 | Ramesh Karri, Balakrishnan Iyer |
Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(4), pp. 505-515, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Concurrent error detection, register transfer level, on line testing |
60 | Rajesh Gupta 0003, Melvin A. Breuer |
Partial scan design of register-transfer level circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 25-46, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
serial scan design, I-paths, design for testability, register-transfer level designs, balanced structures, partial scan design |
59 | Ramesh Karri, Balakrishnan Iyer, Israel Koren |
Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8), pp. 877-888, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
59 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
A design-for-testability technique for register-transfer level circuits using control/data flow extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8), pp. 706-723, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
59 | Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy |
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 110-115, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
MUSTC-testing, multi-stage-combinational test, control paths, signal types, module level pre-computed test sets, scheduling, logic testing, integrated circuit testing, combinational circuits, automatic testing, automatic test, register-transfer level, test scheduling, data-paths |
56 | Han Liang, Piyush Mishra, Kaijie Wu 0001 |
Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(2), pp. 243-252, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Concurrent error detection, register-transfer level, single-event upsets, hardware redundancy |
49 | Jason Cong, Yiping Fan, Junjuan Xu |
Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(3), pp. 35:1-35:31, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
distributed register file, Behavioral synthesis, resource binding |
46 | Matthias Mutz |
Register Transfer Level VHDL Models without Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 153-158, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
VHDL RT subset, register transfer level models |
46 | Vijay Pitchumani, Edward P. Stabler |
Verification of Register Transfer Level Parallel Control Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(8), pp. 761-765, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
critical region, parallel control sequence, Assertion, register transfer level, shared resource, clock cycle, auxiliary variable, verification condition |
46 | Vijay Pitchumani, Edward P. Stabler |
An Inductive Assertion Method for Register Transfer Level Design Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(12), pp. 1073-1080, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
inductive assertion method, synchronous logic, theorem proving, Assertions, predicate calculus, register transfer level design, verification condition |
45 | Jay K. Adams, John Alan Miller, Donald E. Thomas |
Execution-time profiling for multiple-process behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 144-149, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model |
44 | Jason Cong, Yiping Fan, Wei Jiang |
Platform-based resource binding using a distributed register-file microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 709-715, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
distributed register file, behavior synthesis, resource binding |
42 | Joan Carletta, Christos A. Papachristou |
Structural constraints for circular self-test paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 486-491, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits |
41 | Xiaowei Li 0001, Toshimitsu Masuzawa, Hideo Fujiwara |
Strong self-testability for data paths high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 229-234, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
self-testability, testability constraints, interconnection assignment, test resources reusability, high level synthesis, high-level synthesis, design for testability, register transfer level, data flow graphs, data paths, register assignment |
40 | Li Shen 0002 |
VFSim: Concurrent Fault Simulation at Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(2), pp. 175-186, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
concurrent fault simulation, fault model, RTL, Verilog, high-level testing, circuit modeling |
40 | Zebo Peng, Krzysztof Kuchcinski |
Automated transformation of algorithms into register-transfer level implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2), pp. 150-166, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
40 | Frank Mayer, Albrecht P. Stroele |
A Versatile BIST Technique Combining Test Registers and Accumulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 412-, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
test register, built-in self-test, register-transfer level, accumulator |
39 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 173-179, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits |
38 | Thomas Bräunl |
Register-Transfer Level Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 2000, Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 29 August - 1 September 2000, San Francisco, California, USA, pp. 392-396, 2000, IEEE Computer Society, 0-7695-0728-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Jaan Raik, Raimund Ubar |
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 213-226, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
hierarchical test pattern generation, sequential circuits, register-transfer level, decision diagrams |
37 | Min Xu, Fadi J. Kurdahi |
Layout-Driven RTL Binding Techniques for High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 9th International Symposium on System Synthesis, ISSS '96, San Diego, CA, USA, November 6-8, 1996., pp. 33-38, 1996, ACM / IEEE Computer Society, 0-8186-7563-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
layout-driven register-transfer-level, binding techniques, chip level implementation, high level synthesis, high-level synthesis, design process |
36 | Yu Huang 0005, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy |
Synthesis of Scan Chains for Netlist Descriptions at RT-Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(2), pp. 189-201, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
scan synthesis, design for testability (DFT), register transfer level (RTL) |
36 | Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri |
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 521-526, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Amin Asghari, Seied Ahmad Motamedi, Sepehr Attarchi |
Effective RTL Method to Develop On-Line Self-Test Routine for the Processors Using the Wavelet Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIS-ICIS ![In: 7th IEEE/ACIS International Conference on Computer and Information Science, IEEE/ACIS ICIS 2008, 14-16 May 2008, Portland, Oregon, USA, pp. 33-38, 2008, IEEE Computer Society, 978-0-7695-3131-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
On-line low-cost testing, Spectral test pattern generating, Software-based self-testing (SBST), Register transfer level (RTL), Processor testing |
35 | Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham |
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(10), pp. 1401-1414, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Register Transfer Level implementation, Verification, Hardware Description Languages, arithmetic logic unit |
35 | Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan |
Power emulation: a new paradigm for power estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 700-705, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels |
35 | Zhigang Yin, Yinghua Min, Xiaowei Li 0001 |
An Approach to RTL Fault Extraction and Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 219-224, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
ATPG (Automatic Test Pattern Generation), RTL (Register Transfer Level), Fault |
35 | Zdenek Kotásek, F. Zboril |
RT level testability analysis to reduce test application time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 104-, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
register transfer level testability analysis, RTL element classification, RTL circuit transformation, labelled directed graph, PROLOG environment, implementation principles, logic testing, test application time reduction |
35 | Zijian Zhou 0001, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin |
Partitioning transition relations efficiently and automatically. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 106-111, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
automatic partitioning, state transition relations, abstract implicit state enumeration procedure, automatic verification method, graph theory, finite state machines, logic CAD, state estimation, logic partitioning, extended finite state machines, register transfer level designs, multiway decision graphs |
35 | Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
A test evaluation technique for VLSI circuits using register-transfer level fault modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8), pp. 1104-1113, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Ramesh Karri, Kaijie Wu 0001 |
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(6), pp. 864-875, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Matthias Müller 0002, Andreas Wortmann 0002, Dominik Mader, Sven Simon 0001 |
Register Isolation for Synthesizable Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 228-237, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Chun-hong Chen, Chi-Ying Tsui |
Towards the capability of providing power-area-delay trade-off at the register transfer level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 24-29, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Kai Hylla |
Bridging the gap between precise RT-level power/timing estimation and fast high-level simulation: a method for automatically identifying and characterising combinational macros in synchronous sequential systems at register-transfer level and subsequent executable high-level model generation with respect to non-functional properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2014 |
RDF |
|
32 | Loganathan Lingappan, Niraj K. Jha |
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 418-423, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Bruce S. Greene, Samiha Mourad |
Partial Scan Testing on the Register-Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(6), pp. 613-626, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
RT-level, fault coverage, partial scan, scan design, graph reduction |
32 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO: regular expression-based register-transfer level testability analysis and optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 824-832, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi |
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1535-1544, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Loganathan Lingappan, Niraj K. Jha |
Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1339-1345, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri |
Delay Constrained Register Transfer Level Dynamic Power Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 36-46, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Ho Fai Ko, Qiang Xu 0001, Nicola Nicolici |
Register-transfer level functional scan for hierarchical designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1172-1175, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Register transfer level power optimization with emphasis on glitch analysis and reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8), pp. 1114-1131, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Jiong Luo, Lin Zhong 0001, Yunsi Fei, Niraj K. Jha |
Register binding-based RTL power management for control-flow intensive designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8), pp. 1175-1183, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik |
A BIST scheme for RTL circuits based on symbolic testabilityanalysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1), pp. 111-128, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Héctor Navarro, Saeid Nooshabadi, Juan A. Montiel-Nelson, Victor Navarro-Botello, Javier Sosa, José C. García 0001 |
A geometric approach to register transfer level satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 272-275, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Felipe Machado, Teresa Riesgo, Yago Torroja |
Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 399-408, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
activity estimation, CAD, VHDL, BDD, power estimation, RTL, Switching activity, circuit partition, digital circuit design |
30 | Anish Muttreja, Srivaths Ravi 0001, Niraj K. Jha |
Variability-Tolerant Register-Transfer Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 621-628, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Richard Stern, Nikhil Joshi, Kaijie Wu 0001, Ramesh Karri |
Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDTC ![In: Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007, FDTC 2007: Vienna, Austria, 10 September 2007, pp. 112-119, 2007, IEEE Computer Society, 0-7695-2982-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara |
A DFT Method for Time Expansion Model at Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 682-687, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Kaijie Wu 0001, Ramesh Karri |
Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 902-911, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Indradeep Ghosh, Krishna Sekar, Vamsi Boppana |
Design for Verification at the Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 420-425, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Jens Schönherr, Bernd Straube |
Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 759, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Laurence Tianruo Yang, Zebo Peng |
An Improved Register-Transfer Level Functional Partitioning Approach for Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10107-, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Johannes Steensma, Francky Catthoor, Hugo De Man |
Partial scan and symbolic test at the register-transfer level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 7-23, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
data path test, partial scan selection, symbolic test pattern generation, partial scan application schemes |
30 | Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka |
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 2nd International Workshop, CAV '90, New Brunswick, NJ, USA, June 18-21, 1990, Proceedings, pp. 76-85, 1990, Springer, 3-540-54477-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
30 | Rolf Ernst, S. Sutarwala, J.-Y. Jou, M. Tong |
Simulation based verification of register-transfer level behavioral synthesis tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 396-400, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
26 | Rami Beidas, Jianwen Zhu |
Scalable interprocedural register allocation for high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 511-516, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Yoshichika Fujioka, Michitaka Kameyama |
Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012, pp. 235-238, 2012, IEEE, 978-1-4673-2989-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken |
The challenges of implementing fine-grained power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 361-364, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating |
26 | K. M. Deliparaschos, F. I. Nenedakis, Spyros G. Tzafestas |
Design and Implementation of a Fast Digital Fuzzy Logic Controller Using FPGA Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 45(1), pp. 77-96, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
digital fuzzy logic controller, odd-even method, very high-speed hardware description language, synthesis, register transfer level, place and route |
26 | Maciej J. Ciesielski, Priyank Kalla, Serkan Askar |
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(9), pp. 1188-1201, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Register transfer level—design aids, arithmetic and logic structures—verification, symbolic and algebraic manipulation, verification |
26 | Guy Dupenloup, Thierry Lemeunier, Roland Mayr |
Transistor abstraction for the functional verification of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1069-1072, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cone model, logic equivalence checking, transistor abstraction, FPGA, register transfer level, multiplexer, functional verification |
26 | Jaan Raik, Tanel Nõmmeots, Raimund Ubar |
A New Testability Calculation Method to Guide RTL Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(1), pp. 71-82, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
test pattern generation, register-transfer level, decision diagrams, testability measures |
26 | Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi |
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(6), pp. 575-589, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hierarchical fault simulation, mixed level, delta times, VHDL, register transfer level |
26 | Peter J. Osler |
Placement driven synthesis case studies on two sets of two chips: hierarchical and flat. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 190-197, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
synthesis, placement, application specific integrated circuit (ASIC), register transfer level (RTL), static timing analysis (STA), netlist |
26 | Mohamed Kawokgy, C. André T. Salama |
Low-power asynchronous viterbi decoder for wireless applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 286-289, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
bundled-data, four-phase, low-power, synchronous, wireless, VHDL, digital signal processing, asynchronous, register transfer level, viterbi algorithm, speed-independent, handshaking protocol |
26 | Zaher S. Andraus, Karem A. Sakallah |
Automatic abstraction and verification of verilog models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 218-223, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
UCLID, logic of counter arithmetic with lambda expressions and uninter-preted functions (CLU), abstraction, register transfer level (RTL), verilog |
26 | Tomokazu Yoneda, Hideo Fujiwara |
Design for Consecutive Transparency of Cores in System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 287-292, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
consecutive transparency, design for testability, system-on a chip, register transfer level, test access mechanism, consecutive testability |
26 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
Integrated test of interacting controllers and datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(3), pp. 401-422, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
built-in self-test, register transfer level, synthesis-for-testability |
26 | Huawei Li 0001, Yinghua Min, Zhongcheng Li |
An RT-Level ATPG Based on Clustering of Circuit States. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 213-218, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
cluster of states, automatic test pattern generation, register-transfer level, behavioral descriptions |
26 | Kavel M. Büyüksahin, Farid N. Najm |
High-level power estimation with interconnect effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 197-202, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
high-level power estimation, interconnect capacitance estimation, register transfer level (RTL) power estimation |
26 | Laurence Tianruo Yang, Zebo Peng |
Incremental Testability Analysis for Partial Scan Selection and Design Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 103-113, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
incremental testability analysis, partial scan selection, design transformation, register transfer level, high-level test synthesis |
26 | Chuck Monahan, Forrest Brewer |
Scheduling and binding bounds for RT-level symbolic execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 230-235, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
ALAP bounds, as-late-as-possible bounds, binding bounds, efficient operand mapping bound, exact scheduling problem, minimal schedule length, operand recomputation, point-to-point delays, pre-defined data path, register transfer level symbolic execution, time improvement factors, transitive memory units, processor scheduling |
26 | Joan Carletta, Christos A. Papachristou |
Testability analysis and insertion for RTL circuits based on pseudorandom BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 162-167, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pseudorandom BIST, indirect feedback, preprocessing transformation, word-level correlation, modeling, logic testing, probability, built-in self test, built-in self-test, integrated circuit testing, Markov processes, automatic testing, Markov model, insertion, testability analysis, test point insertion, iterative technique, RTL circuits, register transfer level circuits |
26 | Masaru Takesue |
Cache Memories for Data Flow Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(6), pp. 677-687, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
data flow machines, dataflow caches, cache block replacement, cache memories, memory architecture, buffer storage, register transfer level simulator |
26 | Louis J. Hafer, Alice C. Parker |
Automated Synthesis of Digital Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(2), pp. 93-109, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
hardware specification, computer-aided design, logic design, design automation, register-transfer level, hardware-descriptive language, ISP, Automated synthesis |
26 | Mario Barbacci |
A Comparison of Register Transfer Languages for Describing Computers and Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(2), pp. 137-150, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
language properties, design automation, register transfer level, design languages, structural description, behavioral description, Asynchronous control |
25 | Lin Zhong 0001, Jiong Luo, Yunsi Fei, Niraj K. Jha |
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 391-394, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Matthias Müller 0002, Andreas Wortmann 0002, Sven Simon 0001, S. Wolter, Steffen Buch, Marek Wróblewski, Josef A. Nossek |
Low power register file architecture for application specific DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 89-92, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Nazanin Mansouri, Ranga Vemuri |
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 223-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok, Fawnizu Azmadi Hussin |
Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 28th IEEE Asian Test Symposium, ATS 2019, Kolkata, India, December 10-13, 2019, pp. 98, 2019, IEEE, 978-1-7281-2695-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Farnoud Farahmand, Duc Tri Nguyen, Viet Ba Dang, Ahmed Ferozpuri, Kris Gaj |
Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 29th International Conference on Field Programmable Logic and Applications, FPL 2019, Barcelona, Spain, September 8-12, 2019, pp. 225-231, 2019, IEEE, 978-1-7281-4884-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Pradeep Kumar Biswal, Santosh Biswas |
On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 67, pp. 88-100, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Kaijie Wu 0001, Ramesh Karri |
Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3), pp. 413-422, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Kaijie Wu 0001, Ramesh Karri |
Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2001, San Jose, CA, USA, November 4-8, 2001, pp. 537-, 2001, IEEE Computer Society, 0-7803-7249-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Kaijie Wu 0001, Ramesh Karri |
Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001, pp. 221-229, 2001, IEEE Computer Society, 0-7803-7169-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Ramesh Karri, Kaijie Wu 0001 |
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000, pp. 971-978, 2000, IEEE Computer Society, 0-7803-6546-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | J. Bhasker |
Synthesis at the Register Transfer Level and the Behavioral Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
The VLSI Handbook ![In: The VLSI Handbook., 1999, CRC Press, 978-0-8493-8593-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Adam Postula, David Abramson 0001, Ziping Fang, Paul Logothetis |
A Comparison of High Level Synthesis and Register Transfer Level Design Techniques for Custom Computing Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (7) ![In: Thirty-First Annual Hawaii International Conference on System Sciences, Kohala Coast, Hawaii, USA, January 6-9, 1998, pp. 207-215, 1998, IEEE Computer Society, 0-8186-8255-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Anand Raghunathan, Niraj K. Jha |
SCALP: an iterative-improvement-based low-power data path synthesis system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11), pp. 1260-1277, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Xin Wang, Tapani Ahonen, Jari Nurmi |
Applying CDMA Technique to Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(10), pp. 1091-1100, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Kamal S. Khouri, Niraj K. Jha |
Leakage Power Analysis and Reduction during Behavioral Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 561-564, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | K. J. Singh, P. A. Subrahmanyam |
Extracting RTL models from transistor netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 11-17, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Switch-level simulation, Formal verification, Extraction, RTL model |
21 | Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara |
Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, Third International Conference, FMCAD 2000, Austin, Texas, USA, November 1-3, 2000, Proceedings, pp. 455-469, 2000, Springer, 3-540-41219-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Masayoshi Yoshimura, Atsuya Tsujikawa, Toshinori Hosokawa |
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3), pp. 583-591, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha, Chandan Karfa |
SRIL: Securing Registers from Information Leakage at Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, VLSID 2024, Kolkata, India, January 6-10, 2024, pp. 492-498, 2024, IEEE, 979-8-3503-8440-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Sarwono Sutikno, Septafiansyah Dwi Putra, Fajar Wijitrisnanto, Muhamad Erza Aminanto |
Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 46073-46083, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Dang Van Pham, Phan Cong Vinh, Bao Khang Nguyen |
Algebraic Semantics of Register Transfer Level in Synthesis of Stream Calculus-Based Computing Big Data in Livestream. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTCC ![In: Nature of Computation and Communication - 9th EAI International Conference, ICTCC 2023, Ho Chi Minh City, Vietnam, October 26-27, 2023, Proceedings, pp. 19-35, 2023, Springer, 978-3-031-59461-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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