Search results for "reset"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
147	Irith Pomeranz, Sudhakar M. Reddy	On the Detection of Reset Faults in Synchronous Sequential Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF
140	Gun Seo, Sun-Moo Kang, Dae Young Kim 0001, Hong-Bum Jeon	A distributed cycle reset protocol for the high-speed LAN/MAN.	LCN	1995	DBLP DOI BibTeX RDF	shared medium access protocol, distributed cycle reset protocol, high-speed LAN/MAN, distributed cycle reset function, token reset, distributed cycle reset, access control, local area networks, access protocols, metropolitan area networks
132	Dong Xiang, Yi Xu	Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals.	VTS	2001	DBLP DOI BibTeX RDF
112	Vigyan Singhal, Sharad Malik, Robert K. Brayton	The case for retiming with explicit reset circuitry.	ICCAD	1996	DBLP DOI BibTeX RDF	reset state, synchronous reset, asynchronous reset, Retiming, initial state
91	Roy Armoni, Doron Bustan, Orna Kupferman, Moshe Y. Vardi	Resets vs. Aborts in Linear Temporal Logic.	TACAS	2003	DBLP DOI BibTeX RDF
85	Huy Nguyen 0001, Rabindra K. Roy, Abhijit Chatterjee	Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	sequential circuit BIST, built0in self-test, fault propagation analysis, BIST, partial reset
73	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita	Test sequence compaction for sequential circuits with reset states.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
71	Kohzoh Yoshino, Kentaro Takagi, Taishin Nomura, Shunsuke Sato, Mitsuo Tonoike	MEG responses during rhythmic finger tapping in humans to phasic stimulation and their interpretation based on neural mechanisms.	Biol. Cybern.	2002	DBLP DOI BibTeX RDF
66	Anish Arora, Mohamed G. Gouda	Distributed Reset (Extended Abstract).	FSTTCS	1990	DBLP DOI BibTeX RDF	Additional Key Words and Phrases Self-stabilization, spanning trees, diffusing computations
61	Yukiyoshi Kameyama	Axioms for control operators in the CPS hierarchy.	High. Order Symb. Comput.	2007	DBLP DOI BibTeX RDF	Type system, Axiomatization, Delimited continuation, CPS translation, Control operator
61	Yukiyoshi Kameyama	Axioms for Delimited Continuations in the CPS Hierarchy.	CSL	2004	DBLP DOI BibTeX RDF
56	Stefano Battilotti	State estimation of nonlinear systems with Markov state reset.	CDC	2008	DBLP DOI BibTeX RDF
56	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
56	Martin F. Arlitt, Carey L. Williamson	An analysis of TCP reset behaviour on the internet.	Comput. Commun. Rev.	2004	DBLP DOI BibTeX RDF	web, TCP, workload characterization, network traffic measurement
56	Irith Pomeranz, Sudhakar M. Reddy	On Full Reset as a Design-For-Testability Technique.	VLSI Design	1997	DBLP DOI BibTeX RDF
56	David Eppstein	Reset Sequences for Finite Automata with Application to Design of Parts Orienters.	ICALP	1988	DBLP DOI BibTeX RDF
54	Wil M. P. van der Aalst, Kees M. van Hee, Arthur H. M. ter Hofstede, Natalia Sidorova, H. M. W. Verbeek, Marc Voorhoeve, Moe Thandar Wynn	Soundness of Workflow Nets with Reset Arcs.	Trans. Petri Nets Other Model. Concurr.	2009	DBLP DOI BibTeX RDF	Workflow Nets, Reset Nets, Verification, Petri Nets, Decidability, Soundness
54	Moe Thandar Wynn, Wil M. P. van der Aalst, Arthur H. M. ter Hofstede, David Edmond	Verifying Workflows with Cancellation Regions and OR-Joins: An Approach Based on Reset Nets and Reachability Analysis.	Business Process Management	2006	DBLP DOI BibTeX RDF	Workflow verification, Cancellation, OR-joins, Reset nets, YAWL
54	Moe Thandar Wynn, David Edmond, Wil M. P. van der Aalst, Arthur H. M. ter Hofstede	Achieving a General, Formal and Decidable Approach to the OR-Join in Workflow Using Reset Nets.	ICATPN	2005	DBLP DOI BibTeX RDF	OR-join, synchronizing merge, Reset nets, Petri nets, Workflow patterns, YAWL
54	Shaz Qadeer, Robert K. Brayton, Vigyan Singhal	Latch Redundancy Removal Without Global Reset.	ICCD	1996	DBLP DOI BibTeX RDF	global reset assumption, latch redundancy, safe replacement, delayed replacement, Finite state machine, core, strongly connected components
51	William Leal, Anish Arora	Scalable Self-Stabilization via Composition.	ICDCS	2004	DBLP DOI BibTeX RDF
51	Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel	Exact calculation of synchronizing sequences based on binary decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
46	In-Ho Moon, Per Bjesse, Carl Pixley	A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states.	DATE	2007	DBLP DOI BibTeX RDF
46	Subrangshu Das, Subash Chandar G., Ashutosh Tiwari	Reset Careabouts in a SoC Design.	VLSI Design	2004	DBLP DOI BibTeX RDF
46	Hsing-Chung Liang, Chung-Len Lee	An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
46	Huy Nguyen 0001, Abhijit Chatterjee, Rabindra K. Roy	Impact of Partial Reset on Fault Independent Testing and BIST.	VLSI Design	1997	DBLP DOI BibTeX RDF
44	Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton	Sequential optimization in the absence of global reset.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Sequential logic synthesis, no-reset latches, safe replaceability
44	Yuan Lu, Irith Pomeranz	Synchronization of large sequential circuits by partial reset.	VTS	1996	DBLP DOI BibTeX RDF	large synchronous sequential circuits, synchronization, sequential circuits, synchronisation, feedback loops, synchronizing sequence, partial reset
41	Vipul Goyal, Amit Sahai	Resettably Secure Computation.	EUROCRYPT	2009	DBLP DOI BibTeX RDF
41	Kazuki Nakada, Keiji Miura, Hatsuo Hayashi	Theoretical Analysis of Synchronization Phenomena in Two Pulse-Coupled Resonate-and-Fire Neurons.	IJCNN	2007	DBLP DOI BibTeX RDF
41	Abdel Ejnioui, Abdelhalim Alsharqawi	Self-resetting stage logic pipelines.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	clockless, self-resetting, pipeline, asynchronous
41	Yukiyoshi Kameyama, Masahito Hasegawa	A sound and complete axiomatization of delimited continuations.	ICFP	2003	DBLP DOI BibTeX RDF	continuation, axiomatization, CPS-translation
41	Chin-Tser Huang, Mohamed G. Gouda, E. N. Elnozahy	Convergence of IPsec in Presence of Resets.	ICDCS Workshops	2003	DBLP DOI BibTeX RDF
41	Peter A. Tass	Desynchronization of brain rhythms with soft phase-resetting techniques.	Biol. Cybern.	2002	DBLP DOI BibTeX RDF
39	Chris Barker	Wild control operators.	POPL	2009	DBLP DOI BibTeX RDF	fcontrol, same, natural language, continuations, focus, shift, control operators, reset
39	Stephan Roch, Karsten Schmidt 0004	On the Step Explosion Problem.	ICATPN	2006	DBLP DOI BibTeX RDF	step semantics, inhibitory, signal arcs, priorities, read, partial order reduction, State space exploration, reset
39	Jeff Siebert, Jamie Collier, Rajeevan Amirtharajah	Self-timed circuits for energy harvesting AC power supplies.	ISLPED	2005	DBLP DOI BibTeX RDF	AC power supplies, power-on-reset, energy harvesting, self-timed circuits, dynamic memory
39	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	A Unified DFT Approach for BIST and External Test.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	BIST, DFT, test point insertion, partial reset
39	Po-Chi Hu, Leonard Kleinrock	A queueing model for wormhole routing with timeout.	ICCCN	1995	DBLP DOI BibTeX RDF	timeout reset mechanism, M/G/1 queueing system, approximations, feedback, analytical model, wormhole routing, telecommunication network routing, queueing model, performance characteristics, impatient customers
37	Mohamed Soufi, Yvon Savaria, F. Darlay, Bozena Kaminska	Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	full reset, initialization of sequential circuits, modelization of sequential circuits, Markov chain processes, Built-in self-testing, pseudorandom testing, testability measures, partial reset
36	Masao Nakanishi, Taishin Nomura, Shunsuke Sato	Stumbling with optimal phase reset during gait can prevent a humanoid from falling.	Biol. Cybern.	2006	DBLP DOI BibTeX RDF
36	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
36	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
36	Kenichi Asai	Offline partial evaluation for shift and reset.	PEPM	2004	DBLP DOI BibTeX RDF	CPS transformation, binding-time analysis (BTA), offline partial evaluation, continuation-passing style (CPS), logical relations, delimited continuations
36	Dongkyun Kim, Hanseok Bae	Trial-Number Reset Mechanism at MAC Layer for Mobile Ad Hoc Networks.	ECUMN	2004	DBLP DOI BibTeX RDF
36	Peter A. Tass	A model of desynchronizing deep brain stimulation with a demand-controlled coordinated reset of neural subpopulations.	Biol. Cybern.	2003	DBLP DOI BibTeX RDF
36	Kenichi Asai	Online partial evaluation for shift and reset.	PEPM	2002	DBLP DOI BibTeX RDF	CPS transformation, direct style (DS), online partial evaluations, continuation-passing style (CPS), Delimited continuations
36	Martin Gasbichler, Michael Sperber	Final shift for call/cc: : direct implementation of shift and reset.	ICFP	2002	DBLP DOI BibTeX RDF	implementation, scheme, continuations
36	João Carlos Cunha, António Correia, Jorge Henriques, Mário Zenha Rela, João Gabriel Silva	Reset-Driven Fault Tolerance.	EDCC	2002	DBLP DOI BibTeX RDF
36	Alain Finkel, Grégoire Sutre	An Algorithm Constructing the Semilinear Post* for 2-Dim Reset/Transfer VASS.	MFCS	2000	DBLP DOI BibTeX RDF
36	Michael Leuschel, Helko Lehmann	Coverability of Reset Petri Nets and Other Well-Structured Transition Systems by Partial Deduction.	Computational Logic	2000	DBLP DOI BibTeX RDF
36	Wendy Belluomini, Chris J. Myers, H. Peter Hofstee	Verification of Delayed-Reset Domino Circuits Using ATACS.	ASYNC	1999	DBLP DOI BibTeX RDF
36	Catherine Dufourd, Alain Finkel, Philippe Schnoebelen	Reset Nets Between Decidability and Undecidability.	ICALP	1998	DBLP DOI BibTeX RDF
36	Irith Pomeranz, Sudhakar M. Reddy	On the use of reset to increase the testability of interconnected finite-state machines.	ED&TC	1997	DBLP DOI BibTeX RDF
36	Baruch Awerbuch, Boaz Patt-Shamir, George Varghese, Shlomi Dolev	Self-Stabilization by Local Checking and Global Reset (Extended Abstract).	WDAG	1994	DBLP DOI BibTeX RDF
34	Erik Zenner	Nonce Generators and the Nonce Reset Problem.	ISC	2009	DBLP DOI BibTeX RDF	Nonce Reset, Nonce Generator, Cryptography, Security Engineering, Nonce
34	Irith Pomeranz, Sudhakar M. Reddy	On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	hardware reset, synchronous sequential circuit test generation, state variables, test generation procedure, logic testing, sequential circuits, test sequence
31	Andrei A. Antonov, Maksim S. Karpovich, Vladislav Yu. Vasilyev	Power-On Reset Circuit in 180-nm CMOS With Brownout Detection, Stable Switching Points, Long Reset Pulse Duration, and Resilience to Switching Noise.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
31	Tommaso Innocenti, Seyed Ali Mirheidari, Amin Kharraz, Bruno Crispo, Engin Kirda	You've Got (a Reset) Mail: A Security Analysis of Email-Based Password Reset Procedures.	DIMVA	2021	DBLP DOI BibTeX RDF
31	Farzaneh Zokaee, Lei Jiang 0001	Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET.	HPCA	2020	DBLP DOI BibTeX RDF
31	Jun Ho Huh, Hyoungshick Kim, Swathi S. V. P. Rayala, Rakesh B. Bobba, Konstantin Beznosov	I'm too Busy to Reset my LinkedIn Password: On the Effectiveness of Password Reset Emails.	CHI	2017	DBLP DOI BibTeX RDF
31	Xiaoqian Li, Moshe Zukerman, Huachun Zhou, Hongbin Luo, Feng Qiu, Hongke Zhang	Time to live of identifier-to-locator mappings: with-reset or no-reset.	Int. J. Commun. Syst.	2014	DBLP DOI BibTeX RDF
31	Antonio Barreiro, Alfonso Baños, Sebastián Dormido 0001, José Antonio González-Prieto	Reset control systems with reset band: Well-posedness, limit cycles and stability analysis.	Syst. Control. Lett.	2014	DBLP DOI BibTeX RDF
31	Pedro Mercader, Joaquín Carrasco, Alfonso Baños	IQC analysis for time-delay reset control systems with first order reset elements.	CDC	2013	DBLP DOI BibTeX RDF
31	Irith Pomeranz, Sudhakar M. Reddy	Reset and partial-reset-based functional broadside tests.	IET Comput. Digit. Tech.	2012	DBLP DOI BibTeX RDF
31	José Antonio Prieto, Antonio Barreiro, Sebastián Dormido 0001, Sophie Tarbouriech	Delay-Dependent Stability of Reset Control Systems with Anticipative Reset Conditions.	ROCOND	2012	DBLP DOI BibTeX RDF
31	Alfonso Baños, Joaquín Carrasco, Antonio Barreiro	Reset Times-Dependent Stability of Reset Control Systems.	IEEE Trans. Autom. Control.	2011	DBLP DOI BibTeX RDF
31	Fulvio Forni, Dragan Nesic, Luca Zaccarian	Reset passivation of nonlinear controllers via a suitable time-regular reset map.	Autom.	2011	DBLP DOI BibTeX RDF
31	Massimo Costabile, Ivar Massabò, Emilio Russo	On pricing arithmetic average reset options with multiple reset dates in a lattice framework.	J. Comput. Appl. Math.	2011	DBLP DOI BibTeX RDF
31	Huy-Binh Le, Xuan-Dien Do, Sang-Gug Lee 0001, Seung-Tak Ryu	A Long Reset-Time Power-On Reset Circuit With Brown-Out Detection Capability.	IEEE Trans. Circuits Syst. II Express Briefs	2011	DBLP DOI BibTeX RDF
31	Angel Vidal Sanchez, Alfonso Baños	Stablity of reset control systems with variable reset: Application to PI+CI compensation.	ECC	2009	DBLP DOI BibTeX RDF
31	Angel Vidal Sanchez, Alfonso Baños	Stability of reset control systems with variable reset: Application to PI+CI compensation.	ECC	2009	DBLP DOI BibTeX RDF
31	Yuqian Guo, Youyi Wang, Lihua Xie, Hui Li, Weihua Gui 0001	Optimal reset law design of reset control systems with application to HDD systems.	CDC	2009	DBLP DOI BibTeX RDF
31	Alfonso Baños, Sebastián Dormido 0001, Antonio Barreiro	Stability Analysis of reset control systems with reset band.	ADHS	2009	DBLP DOI BibTeX RDF
30	Axel Schild, Magnus Egerstedt, Jan Lunze	Orbital Control for a Class of Planar Impulsive Hybrid Systems with Controllable Resets.	HSCC	2009	DBLP DOI BibTeX RDF
30	Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili	Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification.	FMCAD	2007	DBLP DOI BibTeX RDF
30	Xuandong Li, Jianhua Zhao, Tao Zheng, Yong Li 0005, Guoliang Zheng	Duration-constrained regular expressions.	Formal Aspects Comput.	2004	DBLP DOI BibTeX RDF	Regular expressions, Hybrid automata, Duration Calculus
30	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline-Level Control of Self-Resetting Pipelines.	DSD	2004	DBLP DOI BibTeX RDF
30	Hubert Garavel, Wendelin Serwe	State Space Reduction for Process Algebra Specifications.	AMAST	2004	DBLP DOI BibTeX RDF
30	Ranko Lazic 0001, Thomas Christopher Newcomb, A. W. Roscoe 0001	On Model Checking Data-Independent Systems with Arrays with Whole-Array Operations.	25 Years Communicating Sequential Processes	2004	DBLP DOI BibTeX RDF
30	Amine Bermak, Farid Boussaïd, Abdesselam Bouzerdoum	A New read-out circuit for low power current and voltage mediated integrating CMOS imager.	DELTA	2004	DBLP DOI BibTeX RDF
30	Chi-Yi Lin, Sy-Yen Kuo, Yennun Huang	A Checkpointing Tool for Palm Operating System.	DSN	2001	DBLP DOI BibTeX RDF
30	Alain Finkel, Grégoire Sutre	Decidability of Reachability Problems for Classes of Two Counters Automata.	STACS	2000	DBLP DOI BibTeX RDF
30	Ben Mathew, Daniel G. Saab	Combining multiple DFT schemes with test generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
30	Klaus Eckl, Christian Legl	Retiming Sequential Circuits with Multiple Register Classes.	DATE	1999	DBLP DOI BibTeX RDF
29	Markus Jakobsson, Liu Yang, Susanne Wetzel	Quantifying the security of preference-based authentication.	Digital Identity Management	2008	DBLP DOI BibTeX RDF	password reset, preference-based authentication, security question, simulation
29	Carlo Blundo, Giuseppe Persiano, Ahmad-Reza Sadeghi, Ivan Visconti	Improved Security Notions and Protocols for Non-transferable Identification.	ESORICS	2008	DBLP DOI BibTeX RDF	Non-transferability, reset attacks, e-passports
29	Wil M. P. van der Aalst	Discovery, Verification and Conformance of Workflows with Cancellation.	ICGT	2008	DBLP DOI BibTeX RDF	Reset Nets, Verification, Petri Nets, Soundness, Process Mining
29	Rajeevan Amirtharajah, Justin Wenck, Jamie Collier, Jeff Siebert, Bicky Zhou	Circuits for energy harvesting sensor signal processing.	DAC	2006	DBLP DOI BibTeX RDF	AC power supplies, power-on-reset, energy harvesting, self-timed circuits, dynamic memory
29	Shinya Aoi, Kazuo Tsuchiya	Locomotion Control of a Biped Robot Using Nonlinear Oscillators.	Auton. Robots	2005	DBLP DOI BibTeX RDF	nonlinear oscillators, phase reset, touch sensor signal, biped robot, limit cycle, locomotion control
29	Beichuan Zhang 0001, Vamsi Kambhampati, Mohit Lad, Daniel Massey, Lixia Zhang 0001	Identifying BGP routing table transfers.	MineNet	2005	DBLP DOI BibTeX RDF	collection time, routing table transfer, session reset, BGP
29	Lélia Blin, Alain Cournier, Vincent Villain	An Improved Snap-Stabilizing PIF Algorithm.	Self-Stabilizing Systems	2003	DBLP DOI BibTeX RDF	propagation of information with feedback, reset protocols, wave algorithms, Fault-tolerance, self-stabilization, snap-stabilization
29	Alain Cournier, Ajoy Kumar Datta, Franck Petit, Vincent Villain	Enabling Snap-Stabilizatio.	ICDCS	2003	DBLP DOI BibTeX RDF	propagation of information with feedback, reset protocols, Fault-tolerance, self-stabilization, leader election, snapshot, snap-stabilization
29	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	Design for sequential testability: an internal state reseeding approach for 100 % fault coverage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset
29	Susumu Fujiwara, Gregor von Bochmann, Ferhat Khendek, Mokhtar Amalou, Abderrazak Ghedamsi	Test Selection Based on Finite State Models.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	partial W-method, full fault-detection power, interaction parameters, reset function, software engineering, protocols, program testing, conformance testing, conformance testing, determinism, test suites, protocol implementations, protocol testing, test architectures, finite state models
29	Yves Bekkers, Lucien Ungaro	Real-Time Memory Management for Prolog.	RCLP	1991	DBLP DOI BibTeX RDF	early reset, variable shunting, attributed variable, virtual backtracking, Prolog, implementation, abstract machine, realtime, garbage collector
25	Thomas Loquen, Sophie Tarbouriech, Christophe Prieur 0001	Stability of reset control systems with nonzero reference.	CDC	2008	DBLP DOI BibTeX RDF
25	Ichiro Maruta, Toshiharu Sugie	Reset-free iterative identification based on the finite-dimensional signal subspace.	CDC	2008	DBLP DOI BibTeX RDF
25	Kaijian Shi	Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities.	ICCD	2008	DBLP DOI BibTeX RDF
25	Toru Tanzawa	A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage.	ISCAS	2008	DBLP DOI BibTeX RDF