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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 84 occurrences of 66 keywords
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Found 196 publication records. Showing 196 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 68 | David Sheldon, Rakesh Kumar 0002, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen |
Application-specific customization of parameterized FPGA soft-core processors.  |
ICCAD  |
2006 |
DBLP DOI BibTeX RDF |
|
| 62 | David Sheldon, Rakesh Kumar 0002, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky |
Conjoining soft-core FPGA processors. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning |
| 58 | Roman L. Lysecky, Frank Vahid |
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 42 | Omar A. Al Rayahi, Mohammed A. S. Khalid |
UWindsor Nios II: A soft-core processor for design space exploration. |
EIT |
2009 |
DBLP DOI BibTeX RDF |
|
| 42 | David Sheldon, Frank Vahid, Stefano Lonardi |
Interactive presentation: Soft-core processor customization using the design of experiments paradigm. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 35 | Milos Drutarovský, Michal Varchola |
Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
| 32 | Oleg Maslennikow, Juri Shevtshenko, Anatoli Sergyienko |
Configurable Microprocessor Array for DSP Applications. |
PPAM |
2003 |
DBLP DOI BibTeX RDF |
|
| 30 | José A. M. de Holanda, Jecel Assumpcao, Denis F. Wolf, Eduardo Marques, João M. P. Cardoso |
On Adapting Power Estimation Models for Embedded Soft-Core Processors. |
SIES |
2007 |
DBLP DOI BibTeX RDF |
|
| 29 | Ozgur Sinanoglu, Tsvetomir Petrov |
Isolation Techniques for Soft Cores. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 27 | Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown |
Experiences with Soft-Core Processor Design. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
| 27 | Kaharudin Dimyati, M. F. Ismail |
Implementing a reconfigurable MAP decoder on a soft core processor system. |
APCCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
| 26 | Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang 0032, Yuan Xie 0001, Frank Mueller 0001 |
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. |
CASES |
2009 |
DBLP DOI BibTeX RDF |
LEON3, checkercore, shadow pipeline, FPGA, embedded system, real-time, WCET, worst-case-execution-time, SPARC |
| 26 | David Castells-Rufas, Eduard Fernandez-Alonso, Jordi Carrabina |
Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems. |
Int. J. Reconfigurable Comput. |
2012 |
DBLP DOI BibTeX RDF |
|
| 23 | Rainer Scholz, Klaus Buchenrieder |
Self Reconfiguring EPIC Soft Core Processors. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
|
| 23 | Sujit Dey, Debashis Panigrahi, Li Chen, Clark N. Taylor, Krishna Sekar, Pablo Sanchez |
Using a Soft Core in a SoC Design: Experiences with picoJava. |
IEEE Des. Test Comput. |
2000 |
DBLP DOI BibTeX RDF |
|
| 22 | J. Manikandan, B. Venkataramani, V. Avanthi |
FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 20 | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante |
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 20 | Willian dos Santos Lima, Renata Spolon Lobato, Aleardo Manacero, Roberta Spolon Ulson |
Towards a Java bytecodes compiler for Nios II soft-core processor. |
ISCC |
2009 |
DBLP DOI BibTeX RDF |
|
| 20 | Coral Gonzalez-Concejero, V. Rodellar, Agustín Álvarez Marquina, Elvira Martínez de Icaya, Pedro Gómez Vilda |
A Soft-Core for Pattern Recognition. |
AINA Workshops (1) |
2007 |
DBLP DOI BibTeX RDF |
|
| 20 | Roger D. Chamberlain, John W. Lockwood, Saurabh Gayen, Richard Hough, Phillip H. Jones |
Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory. |
MSE |
2005 |
DBLP DOI BibTeX RDF |
|
| 20 | César Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin |
RASoC: A Router Soft-Core for Networks-on-Chip. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
FPGA, Systems-on-Chip, On-Chip Networks |
| 20 | Lotfi Guedria, Damien Hubaux, Mathieu Ocaña, Jean-Didier Legat |
Flexible embedded system for sensor integration and custom data processing in an automotive application. |
IWCMC |
2009 |
DBLP DOI BibTeX RDF |
driver coaching, soft-core, vehicle monitoring, FPGA, GPS, flexibility, automotive system, FMS, CAN bus |
| 20 | Olivier Hébert, Ivan C. Kraljic, Yvon Savaria |
A method to derive application-specific embedded processing cores. |
CODES |
2000 |
DBLP DOI BibTeX RDF |
custom core, soft core, system-on-a-chip, embedded core, configurable processor |
| 19 | Liang-Teh Lee, Shin-Tsung Lee, Ching-Wei Chen |
Parallel Programming on a Soft-Core Based Multi-core System. |
ICA3PP (2) |
2010 |
DBLP DOI BibTeX RDF |
|
| 19 | Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi |
Improving the Soft-error Tolerability of a Soft-core Processor on. |
J. Next Gener. Inf. Technol. |
2011 |
DBLP DOI BibTeX RDF |
|
| 19 | Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante |
Automatic Generation of Validation Stimuli for Application-Specific Processors. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 19 | Colin J. Ihrig, Rami G. Melhem, Alex K. Jones |
Automated modeling and emulation of interconnect designs for many-core chip multiprocessors. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
simulation, interconnection network, emulation, multi-core, many-core |
| 19 | Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton |
Architectures and algorithms for synthesizable embedded programmable logic cores. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
programmable logic cores, FPGA, standard cells, system-on-chip design |
| 19 | Tomokazu Yoneda, Hideo Fujiwara |
Design for Consecutive Transparency of Cores in System-on-a-Chip. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
consecutive transparency, design for testability, system-on a chip, register transfer level, test access mechanism, consecutive testability |
| 17 | Parimal Patel |
Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 16 | Flavius Gruian, Per Andersson, Krzysztof Kuchcinski, Martin Schoeberl |
Automatic generation of application-specific systems based on a micro-programmed Java core. |
SAC |
2005 |
DBLP DOI BibTeX RDF |
Java, FPGA, system-on-chip, co-design |
| 14 | |
Efficient implementation of QRD-RLS algorithm using hardware-software co-design. |
IPDPS |
2009 |
DBLP DOI BibTeX RDF |
|
| 14 | Tomas Dedek, Tomas Marek, Tomás Martínek |
High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
| 13 | Yuhao Zhao, Fanhao Guo, Deshui Xu |
Vibration energy characters study of a soft-core beam system coupled through nonlinear coupling layers. |
Commun. Nonlinear Sci. Numer. Simul. |
2024 |
DBLP DOI BibTeX RDF |
|
| 13 | Ionel Zagan, Vasile Gheorghita Gaitan |
Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
| 13 | Prashant S. Titare, D. G. Khairnar |
MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application. |
Int. J. High Perform. Syst. Archit. |
2023 |
DBLP DOI BibTeX RDF |
|
| 13 | Ognjen Glamocanin, Shashwat Shrivastava, Jinwei Yao, Nour Ardo, Mathias Payer, Mirjana Stojilovic |
Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs. |
J. Hardw. Syst. Secur. |
2023 |
DBLP DOI BibTeX RDF |
|
| 13 | Ionel Zagan, Vasile Gheorghita Gaitan |
Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation. |
PeerJ Comput. Sci. |
2023 |
DBLP DOI BibTeX RDF |
|
| 13 | Bruno E. Forlin, Wouter van Huffelen, Carlo Cazzaniga, Paolo Rech, Nikolaos Alachiotis 0001, Marco Ottavi |
An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds? |
ETS |
2023 |
DBLP DOI BibTeX RDF |
|
| 13 | Farshid Samsami Khodadad, Hamid Noori |
Characterizing energy and performance of soft-core-based homogeneous multiprocessor systems. |
J. Supercomput. |
2022 |
DBLP DOI BibTeX RDF |
|
| 13 | Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro |
Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors. |
Comput. Electr. Eng. |
2022 |
DBLP DOI BibTeX RDF |
|
| 13 | Vilabha Patil, Shraddha Deshpande |
Design of FPGA Soft Core Based WSN Node Using Customization Paradigm. |
Wirel. Pers. Commun. |
2022 |
DBLP DOI BibTeX RDF |
|
| 13 | Hailong Wu, Jindong Li, Xiang Chen |
Implementation of CNN Heterogeneous Scheme Based on Domestic FPGA with RISC-V Soft Core CPU. |
ICTA |
2022 |
DBLP DOI BibTeX RDF |
|
| 13 | Zhong-xun Wang, Kai-yue Sha, Xinglong Gao |
Digital Image Encryption Test System Based on FPGA and Nios II Soft Core. |
Autom. Control. Comput. Sci. |
2021 |
DBLP DOI BibTeX RDF |
|
| 13 | Yoshiki Kimura, Kanemitsu Ootsu, Tatsuya Tsuchiya, Takashi Yokota |
Development of RISC-V Based Soft-core Processor with Scalable Vector Extension for Embedded System. |
ACIT |
2021 |
DBLP DOI BibTeX RDF |
|
| 13 | Hector Gerardo Muñoz Hernandez, Mitko Veleski, Marcelo Brandalero, Michael Hübner 0001 |
Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPU. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 13 | Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri |
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. |
DFT |
2021 |
DBLP DOI BibTeX RDF |
|
| 13 | John A. Kalomiros, John V. Vourvoulakis |
The Robin Soft-Core: A Paradigm for Studying VHDL and Computer Architecture. |
IDAACS |
2021 |
DBLP DOI BibTeX RDF |
|
| 13 | Yongtao Liu, Ruizhi Sun, Tianyi Zhang, Xiangnan Zhang, Li Li, Guoqing Shi |
Fast Fire Identification Soft-Core Package Design Based on FPGA. |
iThings/GreenCom/CPSCom/SmartData/Cybermatics |
2020 |
DBLP DOI BibTeX RDF |
|
| 13 | Kati Tervo, Samawat Malik, Topi Leppänen, Pekka Jääskeläinen |
TTA-SIMD Soft Core Processors. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 13 | Marcelo Brandalero, Hector Gerardo Muñoz Hernandez, Mitko Veleski, Muhammed Al Kadi, Paolo Rech, Michael Hübner 0001 |
(Special Topic Submission) Enabling Domain-Specific Architectures with an Open-Source Soft-Core GPGPU. |
IPDPS Workshops |
2020 |
DBLP DOI BibTeX RDF |
|
| 13 | Tomoya Kikuchi, Yoshiki Kimura, Kanemitsu Ootsu, Takashi Yokota |
Development of Soft-Core Processor with Efficient Array Data Transfer Mechanism. |
CANDAR (Workshops) |
2020 |
DBLP DOI BibTeX RDF |
|
| 13 | Michael Kirchhoff, Philipp Kerling, Detlef Streitferdt, Wolfgang Fengler 0001 |
A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor. |
Int. J. Reconfigurable Comput. |
2019 |
DBLP DOI BibTeX RDF |
|
| 13 | Abdolsamad Hamidi, Arash Ahmadi, Shahram Karimi, Majid Ahmadi |
Implementation of application specific soft-core architecture for switching converters. |
Comput. Electr. Eng. |
2019 |
DBLP DOI BibTeX RDF |
|
| 13 | Stephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume, Sebastian Niemann, Christian Müller-Schloer |
Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture. |
J. Parallel Distributed Comput. |
2019 |
DBLP DOI BibTeX RDF |
|
| 13 | Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Roger C. Goerl, Fabian Luis Vargas 0001, Eduardo Augusto Bezerra |
Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy. |
J. Electron. Test. |
2019 |
DBLP DOI BibTeX RDF |
|
| 13 | Derya Malak, Muriel Médard, Edmund M. Yeh |
Spatial Soft-Core Caching. |
CoRR |
2019 |
DBLP BibTeX RDF |
|
| 13 | William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps |
Vulnerability Analysis of a Soft Core Processor through Fine-grain Power Profiling. |
IACR Cryptol. ePrint Arch. |
2019 |
DBLP BibTeX RDF |
|
| 13 | Manuel Iñarrea, Víctor Lanchares, Jesús F. Palacián, Ana I. Pascual, J. Pablo Salas, Patricia Yanguas |
Effects of a soft-core coulomb potential on the dynamics of a hydrogen atom near a metal surface. |
Commun. Nonlinear Sci. Numer. Simul. |
2019 |
DBLP DOI BibTeX RDF |
|
| 13 | Karel Szurman, Zdenek Kotásek |
Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430. |
DDECS |
2019 |
DBLP DOI BibTeX RDF |
|
| 13 | Derya Malak, Muriel Médard, Edmund M. Yeh |
Spatial Soft-Core Caching. |
ISIT |
2019 |
DBLP DOI BibTeX RDF |
|
| 13 | Luca Dello Sterpaio, Antonino Marino, Pietro Nannipieri, Luca Fanucci |
Exploiting LabViewFpga Socketed CLIP to Design and Implement Soft-Core Based Complex Digital Architectures on PXI FPGA Target Boards. |
SMACD |
2019 |
DBLP DOI BibTeX RDF |
|
| 13 | Yoshiki Kimura, Tomoya Kikuchi, Kanemitsu Ootsu, Takashi Yokota |
Proposal of Scalable Vector Extension for Embedded RISC-V Soft-Core Processor. |
CANDAR Workshops |
2019 |
DBLP DOI BibTeX RDF |
|
| 13 | Karel Szurman, Zdenek Kotásek |
Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. |
LATS |
2019 |
DBLP DOI BibTeX RDF |
|
| 13 | Kris Heid |
Automatically Parallelizing Embedded Legacy Software on Soft-Core SoCs. |
|
2019 |
RDF |
|
| 13 | Deshya Wijesundera, Alok Prakash, Thambipillai Srikanthan, Achintha Ihalage |
Framework for Rapid Performance Estimation of Embedded Soft Core Processors. |
ACM Trans. Reconfigurable Technol. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
| 13 | Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotásek |
Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller. |
DSD |
2018 |
DBLP DOI BibTeX RDF |
|
| 13 | Kris Heid, Christian Hochberger |
AutoStreams: Fully Automatic parallelization of Legacy Embedded Applications with Soft-Core MPSoCs. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 13 | Zineb El Hariti, Abdelhakim Alali, Mohamed Sadik |
Power and Temperature Estimation for Soft-core Processor Task at the SystemC/TLM. |
ICMCS |
2018 |
DBLP DOI BibTeX RDF |
|
| 13 | Pedro Henrique Exenberger Becker, Anderson Luiz Sartor, Marcelo Brandalero, Tiago Trevisan Jost, Stephan Wong, Luigi Carro, Antonio C. S. Beck |
A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 13 | Junichiro Kadomoto, Toru Koizumi 0001, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai |
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. |
FPT |
2018 |
DBLP DOI BibTeX RDF |
|
| 13 | Zikun Xiang, Tianqi Wang, Tong Geng, Tian Xiang, Xi Jin 0002, Martin C. Herbordt |
Soft-Core. Multiple-Lane, FPGA-based ADCs for a Liquid Helium Environment. |
HPEC |
2018 |
DBLP DOI BibTeX RDF |
|
| 13 | Muhammad Adeel Pasha, Umer Gul, Muhammad Mushahar, Shahid Masud |
A simulation framework for code-level energy estimation of embedded soft-core processors. |
Simul. |
2017 |
DBLP DOI BibTeX RDF |
|
| 13 | Fernando Olivera Domingo, Felipe Iturriaga Cortés, Christian Abraham Almaraz de Horta |
Procesador soft-core de una única instrucción. |
Res. Comput. Sci. |
2017 |
DBLP BibTeX RDF |
|
| 13 | Sarah L. Harris, David Money Harris, Daniel Chaver, Robert Owen, Zubair L. Kakakhel, Enrique Sedano, Yuri Panchul, Bruce Ableidinger |
MIPSfpga: using a commercial MIPS soft-core in computer architecture education. |
IET Circuits Devices Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
| 13 | Moslem Amiri, Fahad Manzoor Siddiqui, Colm Kelly, Roger F. Woods, Karen Rafferty, Burak Bardak |
FPGA-Based Soft-Core Processors for Image Processing Applications. |
J. Signal Process. Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
| 13 | Maheswari Raja, Pattabiraman Venkatasubbu |
Improved reconfigurable hyper-pipeline soft-core processor on FPGA for SIMD. |
Int. J. High Perform. Comput. Netw. |
2017 |
DBLP DOI BibTeX RDF |
|
| 13 | William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj |
Side-channel resistant soft core processor for lightweight block ciphers. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 13 | Stephan Nolting, Florian Giesemann, Julian Hartig, Achim Schmider, Guillermo Payá Vayá |
Application-specific soft-core vector processor for advanced driver assistance systems. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 13 | László Bakó, Szabolcs Hajdú, Fearghal Morgan |
Evaluation and Comparison of Low FPGA Footprint, Embedded Soft-Core Processors. |
MACRo |
2017 |
DBLP DOI BibTeX RDF |
|
| 13 | Thierry Bonnoit, Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco |
SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core. |
LATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 13 | Vittoriano Muttillo, Giacomo Valente, Fabio Federici, Luigi Pomante, Marco Faccio, Carlo Tieri, Serenella Ferri |
A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system. |
EURASIP J. Embed. Syst. |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Adam Ziebinski, Stanislaw Swierc |
Soft Core Processor Generated Based on the Machine Code of the Application. |
J. Circuits Syst. Comput. |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | David Castells-Rufas, Albert Saà-Garriga, Jordi Carrabina |
Energy Efficiency of Many-Soft-Core Processors. |
CoRR |
2016 |
DBLP BibTeX RDF |
|
| 13 | Hilal Tayara, Woon Chul Ham, Kil To Chong 0001 |
A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor. |
Sensors |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Harald Homulle, Stefan Visser, Edoardo Charbon |
A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Tiago T. Jost, Gabriel L. Nazar, Luigi Carro |
Improving performance in VLIW soft-core processors through software-controlled scratchpads. |
SAMOS |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Qingming Yi, Min Shi, Ming-Min Chen, Song Li |
A design method for an improved soft core of ARMv4 instruction set based on FPGA. |
CITS |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Stefan Visser, Harald Homulle, Edoardo Charbon |
A 1 GSa/s, Reconfigurable Soft-core FPGA ADC (Abstract Only). |
FPGA |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Deshya Wijesundera, Alok Prakash, Siew Kei Lam, Thambipillai Srikanthan |
Exploiting Configuration Dependencies for Rapid Area-efficient Customization of Soft-core Processors. |
SCOPES |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Colm Kelly, Fahad Manzoor Siddiqui, Burak Bardak, Yun Wu, Roger F. Woods, Karen Rafferty |
FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Deshya Wijesundera, Alok Prakash, Thambipillai Srikanthan |
Rapid design space exploration for soft core processor customization and selection. |
FPT |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Changgong Li, Alexander Schwarz, Christian Hochberger |
A readback based general debugging framework for soft-core processors. |
ICCD |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Tiago T. Jost, Gabriel L. Nazar, Luigi Carro |
Scalable memory architecture for soft-core processors. |
ICCD |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Sarah L. Harris, Robert Owen, Enrique Sedano, Daniel A. Chaver Martinez |
MIPSfpga: Hands-on learning on a commercial soft-core. |
EWME |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Werner Nedel, Fernanda Lima Kastensmidt, José Rodrigo Azambuja |
Evaluating the effects of single event upsets in soft-core GPGPUs. |
LATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 13 | Matteo Cuppini, Claudio Mucci, Eleonora Franchi Scarselli |
Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative Analysis. |
IEEE Trans. Very Large Scale Integr. Syst. |
2015 |
DBLP DOI BibTeX RDF |
|
| 13 | Julio C. Sosa, Iván Dominguez-Lopez, Adrián L. García-García, J. D. Oscar Barceinas-Sánchez, Anuar Jassen |
Sistema embebido para la detección de luz láser empleando el soft-core Nios II. |
Res. Comput. Sci. |
2015 |
DBLP BibTeX RDF |
|
| 13 | Rene Broich, Hans Grobler |
Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2015 |
DBLP DOI BibTeX RDF |
|
| 13 | Aiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa |
An energy-efficient FPGA-based soft-core processor with a configurable word size ECC arithmetic accelerator. |
COOL Chips |
2015 |
DBLP DOI BibTeX RDF |
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