Search results for "switching-activity"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
78	Jason Helge Anderson, Farid N. Najm	Switching activity analysis and pre-layout activity prediction for FPGAs.	SLIP	2003	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, power, estimation
63	Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan	Computation of lower bounds for switching activity using decision theory.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
61	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register-transfer level estimation techniques for switching activity and power consumption.	ICCAD	1996	DBLP DOI BibTeX RDF	gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs
60	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	At-speed scan testing, Capture switching activity, X-filling, Test cube, ATPG, Low power testing
60	Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski	Scan-Based Tests with Low Switching Activity.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	scan shift, test response capture, supply current, power dissipation, switching activity, scan-based test
53	Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi	ByZFAD: a low switching activity architecture for shift-and-add multipliers.	SBCCI	2006	DBLP DOI BibTeX RDF	adder bypass, byZFAD, hot-block ring counter, shiftand-add multiplier, low-power, switching activity
51	Seongmoon Wang	Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST.	ITC	2002	DBLP DOI BibTeX RDF
50	Anand Raghunathan, Sujit Dey, Niraj K. Jha	High-level macro-modeling and estimation techniques for switching activity and power consumption.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
50	Felipe Machado, Teresa Riesgo, Yago Torroja	A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
48	Pinhong Chen, Yuji Kukimoto, Kurt Keutzer	Refining switching window by time slots for crosstalk noise calculation.	ICCAD	2002	DBLP DOI BibTeX RDF
46	Eleftheria Athanasopoulou, Christoforos N. Hadjicostis	Bounds on FSM Switching Activity.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	Low power design, Markov models, Hamming distance, State assignment, Switching activity
46	Felipe Machado, Teresa Riesgo, Yago Torroja	Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level.	PATMOS	2008	DBLP DOI BibTeX RDF	activity estimation, CAD, VHDL, BDD, power estimation, RTL, Switching activity, circuit partition, digital circuit design
46	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	test vector ordering, test, low power, switching activity
46	Taku Uchino, Fumihiro Minami, Takashi Mitsuhashi, Nobuyuki Goto	Switching activity analysis using Boolean approximation method.	ICCAD	1995	DBLP DOI BibTeX RDF	Signal Correlation, Power Estimation, Switching Activity, Signal Probability
46	Sanjukta Bhanja, N. Ranganathan	Switching activity estimation of VLSI circuits using Bayesian networks.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
46	Radu Marculescu, Diana Marculescu, Massoud Pedram	Probabilistic modeling of dependencies during switching activity analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
44	Jason Helge Anderson, Farid N. Najm	Power estimation techniques for FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
42	Sanjukta Bhanja, N. Ranganathan	Cascaded Bayesian inferencing for switching activity estimation with correlated inputs.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
41	Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang	Switching-activity driven gate sizing and Vth assignment for low power design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
41	Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia 0001	Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.	PATMOS	2002	DBLP DOI BibTeX RDF
41	Janardhan H. Satyanarayana, Keshab K. Parhi	Theoretical analysis of word-level switching activity in the presence of glitching and correlation.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
41	Janardhan H. Satyanarayana, Keshab K. Parhi	Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
41	José Monteiro 0001, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White 0001	Estimation of average switching activity in combinational logic circuits using symbolic simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
41	Salvador Manich, Joan Figueras	Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model.	ED&TC	1997	DBLP DOI BibTeX RDF
41	Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad Tehranipoor	Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation.	DATE	2008	DBLP DOI BibTeX RDF
40	Zili Shao, Bin Xiao 0001, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Loop scheduling with timing and switching-activity minimization for VLIW DSP.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	instruction bus optimization, low-power optimization, compilers, software pipelining, VLIW, retiming, instruction scheduling, loops
40	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	Reducing the data switching activity of serialized datastreams.	ISCAS	2006	DBLP DOI BibTeX RDF
40	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	Reducing the Data Switching Activity on Serial Link Buses.	ISQED	2006	DBLP DOI BibTeX RDF
39	Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian	Switching activity generation with automated BIST synthesis forperformance testing of interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
38	Vasily G. Moshnyaga	Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	bit-truncation, low-power design, video processing, switching activity
38	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign bit reduction encoding for low power applications.	DAC	2005	DBLP DOI BibTeX RDF	signed multiplier, sing extension, low power, switching activity, bus encoding
37	Jun Yang 0002, Rajiv Gupta 0001, Chuanjun Zhang	Frequent value encoding for low power data buses.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching
36	Seongmoon Wang, Wenlong Wei	A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture.	ASP-DAC	2007	DBLP DOI BibTeX RDF	peak current reduction, average power dissipation, clock tree construction, special scan cells, scan chain reordering, ATPG, scan designs
36	Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski	Low Shift and Capture Power Scan Tests.	VLSI Design	2007	DBLP DOI BibTeX RDF
36	Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin	A Low Power-Delay Product Page-Based Address Bus Coding Method.	VLSI Design	2003	DBLP DOI BibTeX RDF
36	Bruce R. Childers, Tarun Nakra	Reordering Memory Bus Transactions for Reduced Power Consumption.	LCTES	2000	DBLP DOI BibTeX RDF
36	Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao 0001, Edwin Hsing-Mean Sha	Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.	ASAP	2004	DBLP DOI BibTeX RDF
34	Seongmoon Wang, Sandeep K. Gupta 0001	DS-LFSR: a BIST TPG for low switching activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
34	Ashok K. Murugavel, N. Ranganathan	A Real Delay Switching Activity Simulator Based on Petri Net Modeling.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
33	Vamsi Krishna, N. Ranganathan	A Methodology for High Level Power Estimation and Exploration.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Low Power Designs, Power Estimation, Switching Activity, High Level Designs
33	Chuan-Yu Wang, Kaushik Roy 0001	Control unit synthesis targeting low-power processors.	ICCD	1995	DBLP DOI BibTeX RDF	control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming
33	José Monteiro 0001, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh	Optimization of combinational and sequential logic circuits for low power using precomputation.	ARVLSI	1995	DBLP DOI BibTeX RDF	sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle
33	Seongmoon Wang, Sandeep K. Gupta 0001	An automatic test pattern generator for minimizing switching activity during scan testing activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
32	Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz	A Low Power Pseudo-Random BIST Technique.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	low power, BIST, scan, pseudo-random, peak power
32	Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz	A Low Power Pseudo-Random BIST Technique.	ICCD	2002	DBLP DOI BibTeX RDF
32	Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz	A Low Power Pseudo-Random BIST Technique.	IOLTW	2002	DBLP DOI BibTeX RDF
32	Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis	Low power synthesis of sum-of-product computation in DSP algorithms.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
31	Oscar Gustafsson, Saeeid Tahmasbi Oskuii, Kenny Johansson, Per Gunnar Kjeldsberg	Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data.	PATMOS	2007	DBLP DOI BibTeX RDF	dual bit type, coefficient reordering, MAC, FIR filter, switching activity
31	Sanjukta Bhanja, N. Ranganathan	Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams.	ICCD	2002	DBLP DOI BibTeX RDF
30	Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang	Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	maximum switching activity, uncertainty waveforms, circuit reliability
29	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah	A Low Power Approach to Floating Point Adder Design for DSP Applications.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	digital-CMOS, power-consumption-model, VLSI, low-power-design, computer-arithmetic, floating-point, switching-activity
29	Seongmoon Wang	A BIST TPG for Low Power Dissipation and High Fault Coverage.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
29	Ashok K. Murugavel, N. Ranganathan	Petri net modeling of gate and interconnect delays for power estimation.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
29	Wei-Chung Cheng, Massoud Pedram	Low power techniques for address encoding and memory allocation.	ASP-DAC	2001	DBLP DOI BibTeX RDF
29	Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy 0001	Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design.	ICCD	1999	DBLP DOI BibTeX RDF
29	Lakshmikant Bhupathi, Liang-Fang Chao	Dichotomy-based Model for FSM Power Minimization.	ICCD	1996	DBLP DOI BibTeX RDF
29	Chi-Ying Tsui, José Monteiro 0001, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin 0001	Power estimation methods for sequential logic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
28	Raid Ayoub, Alex Orailoglu	A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses.	ASP-DAC	2005	DBLP DOI BibTeX RDF
28	Snehashis Roy, Sukumar Jairam, H. Udayakumar	A Methodology for Switching Activity Based IO Powerpad Optimisation.	VLSI Design	2006	DBLP DOI BibTeX RDF
28	Sanjukta Bhanja, N. Ranganathan	Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
28	Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha, Bin Xiao 0001	Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures.	EUC	2004	DBLP DOI BibTeX RDF
28	Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai	Loop scheduling for minimizing schedule length and switching activities.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
27	Huy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy	Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
27	Irith Pomeranz, Sudhakar M. Reddy	Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity.	VLSI Design	2008	DBLP DOI BibTeX RDF
27	Seongmoon Wang, Sandeep K. Gupta 0001	LT-RTPG: a new test-per-scan BIST TPG for low switching activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
27	Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner	Switching Activity Estimation in Non-linear Architectures.	PATMOS	2003	DBLP DOI BibTeX RDF
27	Eleftheria Athanasopoulou, Christoforos N. Hadjicostis	Upper and lower bounds on FSM switching activity.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
27	Markus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger	Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach.	DATE	1999	DBLP DOI BibTeX RDF
27	Jeremy Lee, Mohammad Tehranipoor	LS-TDF: Low-Switching Transition Delay Fault Pattern Generation.	VTS	2008	DBLP DOI BibTeX RDF
27	Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami	Reducing power consumption of instruction ROMs by exploiting instruction frequency.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
26	Yan Zhang 0028, John C. Lach, Kevin Skadron, Mircea R. Stan	Odd/even bus invert with two-phase transfer for buses with coupling.	ISLPED	2002	DBLP DOI BibTeX RDF	bus invert, buses with coupling, coding for low-power I/O
26	Wang-Dauh Tseng	Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	transition density, switching activity during test, clique, low power testing, full scan
26	Malav Shah	Efficient scan-based BIST scheme for low power testing of VLSI chips.	ISLPED	2006	DBLP DOI BibTeX RDF	test-per-clock, test-per-scan, scan, partial scan, switching activity, test length
26	Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj	Estimation of state line statistics in sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	signal statistics, transition density, finite-state machine, sequential circuit, Power estimation, switching activity, signal probability
26	Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba	Static Compaction Techniques to Control Scan Vector Power Dissipation.	VTS	2000	DBLP DOI BibTeX RDF	Static Compaction, Test Vector Compaction, Heat Minimization, Low Power, Built-In Self-Test, Design-for-Testability, Integrated Circuits, switching activity, Scan Chains, Peak power, Embedded Cores, Digital Testing
26	Raghava V. Cherabuddi, Magdy A. Bayoumi, H. Krishnamurthy	A low power based system partitioning and binding technique for multi-chip module architectures.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	binding technique, multi-chip module architectures, high-level synthesis framework, inter-chip buses, stochastic evolution based technique, multichip modules, switching activity, MCM, functional units, system partitioning, benchmark designs
26	Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang	Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.	ICCD	1996	DBLP DOI BibTeX RDF	pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
26	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	Energy-efficient encoding techniques for off-chip data buses.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Low-power data buses, bus switching, internal capacitances, encoding
26	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar, Laxmi N. Bhuyan	Power efficient encoding techniques for off-chip data buses.	CASES	2003	DBLP DOI BibTeX RDF	FV, FV-MSB-LSB, data bus, low power, bus encoding
26	R. Iris Bahar, Ernest T. Lampe, Enrico Macii	Power optimization of technology-dependent circuits based on symbolic computation of logic implications.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	design synthesis, logic design, automation, aids
26	Tan-Li Chou, Kaushik Roy 0001	Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
25	Jiong Luo, Lin Zhong 0001, Yunsi Fei, Niraj K. Jha	Register binding-based RTL power management for control-flow intensive designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
24	Amir H. Farrahi, Chunhong Chen, Ankur Srivastava 0001, Gustavo E. Téllez, Majid Sarrafzadeh	Activity-driven clock design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
24	Shu-Cheng Chou, Mong-Kai Ku, Chia-Yu Lin	Switching activity reducing layered decoding algorithm for LDPC codes.	ISCAS	2008	DBLP DOI BibTeX RDF
24	Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan	Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks.	VLSI Design	2005	DBLP DOI BibTeX RDF
24	Kenny Johansson, Oscar Gustafsson, Lars Wanhammar	Power Estimation for Ripple-Carry Adders with Correlated Input Data.	PATMOS	2004	DBLP DOI BibTeX RDF
23	Mikael Kerttu, Per Lindgren, Mitchell A. Thornton, Rolf Drechsler	Switching activity estimation of finite state machines for low power synthesis.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
23	Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Yung-Cheng Ma	A multiplication-accumulation computation unit with optimized compressors and minimized switching activities.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
23	Tan-Li Chou, Kaushik Roy 0001, Sharat Prasad	Estimation of circuit activity considering signal correlations and simultaneous switching.	ICCAD	1994	DBLP DOI BibTeX RDF
22	Anshuman Chandra, Rohit Kapur	Bounded Adjacent Fill for Low Capture Power Scan Testing.	VTS	2008	DBLP DOI BibTeX RDF	capture power, random fill, shift power, test, low power, scan
22	Kostas Siozios, Dimitrios Soudris	A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs.	ISVLSI	2007	DBLP DOI BibTeX RDF
22	Amit Kedia, Resve A. Saleh	Power Reduction of On-Chip Serial Links.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King	Hierarchical value cache encoding for off-chip data bus.	ISLPED	2006	DBLP DOI BibTeX RDF	data bus encoding, hierarchical value cache, energy
22	Mehdi Salmani Jelodar, Kiarash Mizanian	Power Aware Scan-Based Testing using Genetic Algorithm.	CCECE	2006	DBLP DOI BibTeX RDF
22	Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo	Logic-Level Fast Current Simulation for Digital CMOS Circuits.	PATMOS	2005	DBLP DOI BibTeX RDF
22	Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay	Flip-flop chaining architecture for power-efficient scan during test application.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
22	Wei-Chung Cheng, Massoud Pedram	Power-optimal encoding for a DRAM address bus.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
22	Li Shang, Alireza Kaviani, Kusuma Bathala	Dynamic power consumption in Virtex[tm]-II FPGA family.	FPGA	2002	DBLP DOI BibTeX RDF
22	K. Basu, Alok N. Choudhary, Jayaprakash Pisharath, Mahmut T. Kandemir	Power protocol: reducing power dissipation on off-chip data buses.	MICRO	2002	DBLP DOI BibTeX RDF
22	Rung-Bin Lin, Chi-Ming Tsai	Weight-Based Bus-Invert Coding for Low-Power Applications.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF