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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 154 occurrences of 90 keywords
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Results
Found 66 publication records. Showing 66 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
66 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9), pp. 1001-1014, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
63 | Srivaths Ravi 0001, Niraj K. Jha |
Test synthesis of systems-on-a-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10), pp. 1211-1217, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
62 | Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel |
Enhancing high-level control-flow for improved testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 322-328, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description |
54 | Alex Orailoglu |
Microarchitectural synthesis for rapid BIST testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6), pp. 573-586, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
52 | Frank F. Hsu, Janak H. Patel |
A distance reduction approach to design for testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 158-163, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flip-flops, flip-flops, synthesis for testability, test function, average distance, DFT techniques |
52 | Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab |
Structural and behavioral synthesis for testability techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6), pp. 777-785, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
48 | Irith Pomeranz, Sudhakar M. Reddy |
Synthesis for Broadside Testability of Transition Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 221-226, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
broadside tests, standard scan, transition faults, test synthesis, full-scan circuits |
48 | Harry Hengster, Bernd Becker 0001 |
Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-29, The Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, USA, June 15-18, 1999, pp. 268-275, 1999, IEEE Computer Society, 0-7695-0213-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
EXOR-based Synthesis, Decision Diagrams, Synthesis for Testability, High Speed Circuits |
48 | Franco Fummi, Donatella Sciuto, M. Serro |
Synthesis for testability of large complexity controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 180-185, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates |
43 | Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken |
Manufacturability and Testability Oriented Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 185-191, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Synthesis Optimization, CAD, System on Chip, Design for Manufacturability, High Level Test Synthesis |
37 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
Synthesis-for-testability of controller-datapath pairs that use gated clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 613-618, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Richard M. Chou, Kewal K. Saluja |
Sequential Circuit Testing: From DFT to SFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 274-278, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques |
37 | Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel |
Testability Insertion in Behavioral Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 9th International Symposium on System Synthesis, ISSS '96, San Diego, CA, USA, November 6-8, 1996., pp. 139-144, 1996, ACM / IEEE Computer Society, 0-8186-7563-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description |
37 | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng |
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 171-176, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions |
37 | Franco Fummi, Donatella Sciuto, Micaela Serra |
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(12), pp. 1305-1323, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
sequential circuits, functional testing, Synthesis for testability, logic minimization, redundant faults, redundancies removal |
37 | Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth |
Synthesis for Testability by Two-Clock Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 279-283, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
two-clock control scheme, split coding system, FSM benchmark, timing, finite state machine, sequential circuit, encoding, logic synthesis, Hamiltonian cycle, synthesis for testability, state transition graph |
37 | Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki |
A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 263-268, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path |
36 | Sujit Dey, Anand Raghunathan, Kenneth D. Wagner |
Design for Testability Techniques at the Behavioral and Register-Transfer Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(2), pp. 79-91, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability |
36 | Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal |
Finite state machine synthesis with fault tolerant test function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(1), pp. 57-69, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
Design for combinational test generation, finite state machine synthesis, test function embedding, synthesis for testability, fault-tolerant design |
29 | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe |
Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 921-922, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Scan chain selection, RT and gate levels, Partial scan, Synthesis for testability |
25 | Srinivas Devadas, Kurt Keutzer |
Synthesis of robust delay-fault-testable circuits: practice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(3), pp. 277-300, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
24 | Christof Nagel |
Synthesis for testability by synthesis controlling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 38(1-5), pp. 767-774, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Meghanad D. Wagh, Chien-In Henry Chen |
High-level design synthesis with redundancy removal for high speed testable adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 358-361, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng |
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12), pp. 1514-1521, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Chip-Hong Chang, Aijiao Cui |
Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7), pp. 1618-1630, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara |
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 90-D(1), pp. 296-305, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth |
A synthesis for testability scheme for finite state machines using clock control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12), pp. 1780-1792, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Chien-Chung Tsai, Malgorzata Marek-Sadowska |
Logic Synthesis for Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 118-121, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Fixed-Polarity Reed-Muller Forms, Logic synthesis, Testability |
19 | Kenneth D. Wagner, Sujit Dey |
High-Level Synthesis for Testability: A Survey and Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996., pp. 131-136, 1996, ACM Press, 0-89791-779-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
Synthesis for testability techniques for asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1569-1577, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita |
Synthesis for Testability by Sequential Redundancy Removal Using Retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-25, The Twenty-Fifth International Symposium on Fault-Tolerant Computing, Pasadena, California, USA, June 27-30, 1995, pp. 33-40, 1995, IEEE Computer Society, 0-8186-7079-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Bernd Becker 0001, Rolf Drechsler |
Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: 1995 European Design and Test Conference, ED&TC 1995, Paris, France, March 6-9, 1995, pp. 592, 1995, IEEE Computer Society, 0-8186-7039-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy |
Synthesis-for-testability using transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995, 1995, ACM, 0-89791-766-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Irith Pomeranz, Sudhakar M. Reddy |
On Synthesis-for-Testability of Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995., pp. 126-132, 1995, ACM Press, 0-89791-725-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
Sequential test generation and synthesis for testability at the register-transfer and logic levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5), pp. 579-598, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer |
Delay-fault test generation and synthesis for testability under a standard scan design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8), pp. 1217-1231, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Irith Pomeranz, Sudhakar M. Reddy |
Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-23, The Twenty-Third Annual International Symposium on Fault-Tolerant Computing, Toulouse, France, June 22-24, 1993, pp. 492-501, 1993, IEEE Computer Society, 0-8186-3680-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Bernd Becker 0001 |
Synthesis for Testability: Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Informatik ![In: Informatik, Festschrift zum 60. Geburtstag von Günter Hotz, pp. 21-39, 1992, Teubner / Springer, 978-3-8154-2033-1. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Chung-Hsing Chen, Daniel G. Saab |
Behavioral synthesis for testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1992 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of Technical Papers, pp. 612-615, 1992, IEEE Computer Society / ACM, 0-8186-3010-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Bernd Becker 0001 |
Synthesis for Testability: Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 92, 9th Annual Symposium on Theoretical Aspects of Computer Science, Cachan, France, February 13-15, 1992, Proceedings, pp. 501-512, 1992, Springer, 3-540-55210-3. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
VLSI structures, (complete, full) testability, synthesis, fault model, algorithms and data structures |
19 | Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
Synthesis for Testability Techniques for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1991 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of Technical Papers, pp. 326-329, 1991, IEEE Computer Society, 0-8186-2157-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
19 | Srinivas Devadas, Kurt Keutzer, Abhijit Ghosh |
Recent progress in synthesis for testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 9th IEEE VLSI Test Symposium (VTS'91), 15-17 Apr 1991, Atlantic City, NJ, USA, pp. 22-29, 1991, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
19 | Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer |
Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991., pp. 80-86, 1991, ACM, 0-89791395-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
19 | |
A D&T Roundtable: Synthesis for Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 7(6), pp. 50-59, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
19 | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
Sequential logic synthesis for testability using register-transfer level descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990, pp. 274-283, 1990, IEEE Computer Society, 0-8186-9064-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
18 | Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya |
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(2), pp. 125-142, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
universal tests, stuck-at fault, path-delay fault, synthesis-for-testability, unate function, symmetric boolean function |
18 | Peter Bukovjan, Laurent Ducerf-Bourbon, Meryem Marzouki |
Cost/Quality Trade-off in Synthesis for BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(2), pp. 109-119, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
DFT reuse, BIST, synthesis for testability, testability analysis |
18 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
Integrated test of interacting controllers and datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(3), pp. 401-422, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
built-in self-test, register transfer level, synthesis-for-testability |
18 | Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi |
False-Path Removal Using Delay Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 463-476, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal |
18 | Albrecht P. Stroele |
Synthesis for Arithmetic Built-In Self-Tes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 165-170, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
test configuration, built-in self-test, high-level synthesis, synthesis for testability, Accumulator |
18 | Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker 0001 |
Testability of 2-Level AND/EXOR Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(3), pp. 219-225, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
AND/EXOR, 2-level circuits, synthesis for testability, random pattern testability |
18 | Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey |
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 193-198, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Respecification, Synthesis for Testability, Don't Cares, High Level Testing |
18 | Frank F. Hsu, Janak H. Patel |
Design for Testability Using State Distances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 93-100, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
state distance, finite-state-machine, design-for-testability, synthesis-for-testability |
18 | Supratik Chakraborty, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri |
Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(7), pp. 769-781, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synthesis for testability (SFT), testable sequential machines, Cellular automata |
18 | Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara |
An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 130-135, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synchronizable finite state machines, sequential circuits synthesis, extended synchronizing sequence, scan inputs, normal inputs, MCNC'91 benchmark FSM, minimum-length extended synchronizing sequence, test generation, finite state machines, DFT, heuristic algorithm, minimization, partial scan, synthesis for testability, state assignment, state transition, state encoding |
18 | Harry Hengster, Rolf Drechsler, Bernd Becker 0001, Stefan Eckrich, Tonja Pfeiffer |
AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 148-, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
EXOR based synthesis, synthesis for testability, delay optimization |
18 | Maria J. Avedillo, José M. Quintana, José Luis Huertas |
Constrained state assignment of easily testable FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 133-138, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Finite state machines, synthesis for testability, state assignment |
18 | Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja |
Incorporating testability considerations in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(1), pp. 43-55, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Automatic synthesis of testable designs, loop breaking, high-level synthesis, binding, synthesis for testability |
18 | Bernhard Eschermann |
Enhancing on-line testability during synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(1), pp. 105-116, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
BIST, synthesis for testability, control flow checking, controller synthesis |
18 | Sen-Pin Lin, Charles Njinda, Melvin A. Breuer |
Generating a family of testable designs using the BILBO methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(1), pp. 71-89, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
BILBO design system, built-in self-test, test scheduling, synthesis for testability |
18 | Bernhard Eschermann |
An implicitly testable boundary scan TAP controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(2), pp. 159-169, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
test controller, BIST, self-test, boundary scan, synthesis for testability, controller design |
18 | Vishwani D. Agrawal, Kwang-Ting Cheng |
Finite state machine synthesis with embedded test function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(3), pp. 221-228, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
VLSI, Computer-Aided Design, Test Generation, Logic Synthesis, Synthesis for Testability |
18 | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton |
Redundancies and don't cares in sequential logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(1), pp. 15-30, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
redundancies, synthesis for testability, don't cares |
14 | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
Heuristic minimization of Boolean relations using testing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(9), pp. 1166-1172, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
11 | Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian |
Switching activity generation with automated BIST synthesis forperformance testing of interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9), pp. 1143-1158, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Vishwani D. Agrawal, Kwang-Ting Cheng |
Test Function Specification in Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 235-240, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
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