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Searching for phrase test-per-scan (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1999-2005 (16) 2006-2021 (12)
Publication types (Num. hits)
article(11) inproceedings(17)
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The graphs summarize 28 occurrences of 23 keywords

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Found 28 publication records. Showing 28 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
111Xiaodong Zhang 0010, Kaushik Roy 0001 Power Reduction in Test-Per-Scan BIST. Search on Bibsonomy IOLTW The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Test-per-scan, Low Power BIST, Testing, Low Power, BIST, Weighted Random Pattern
84Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara Improving test effectiveness of scan-based BIST by scan chain partitioning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
83Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy 0001 Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
74Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
72Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel A Gated Clock Scheme for Low Power Testing of Logic Cores. Search on Bibsonomy J. Electron. Test. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF test-per-scan, test-per-clock, low power design, low power test
68Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001 Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. Search on Bibsonomy IOLTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Test-per-scan BIST, delay sensor, fault diagnosis, fault localization, test point insertion
67Dong Xiang, Mingjing Chen, Hideo Fujiwara Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Random testability, scan enable signal, weighted random testing, scan-based BIST
65Dong Xiang, Mingjing Chen, Jia-Guang Sun Scan BIST with biased scan test signals. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF random testability, test signal, biased random testing, scan-based BIST
65Dong Xiang, Ming-Jing Chen, Kaiwei Li, Yu-Liang Wu Scan-Based BIST Using an Improved Scan Forest Architecture. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
59Nitin Parimi, Xiaoling Sun Toggle-Masking for Test-per-Scan VLSI Circuits. Search on Bibsonomy DFT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
46Abdallatif S. Abu-Issa, Iyad K. Tumar, Wasel T. Ghanem SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST. Search on Bibsonomy IDT The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
45Seongmoon Wang, Sandeep K. Gupta 0001 LT-RTPG: a new test-per-scan BIST TPG for low switching activity. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Ondrej Novák, Jiri Nosek Test Pattern Decompression Using a Scan Chain. Search on Bibsonomy DFT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF hardware test pattern generators, BIST, test pattern generation, scan design
37Chien-In Henry Chen, Kiran George Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
36Malav Shah, Dipankar Nagchoudhuri BIST Scheme for Low Heat Dissipation and Reduced Test Application Time. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Vishnupriya Shivakumar, Chinnaiyan Senthilpari, Zubaida Binti Yusoff A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture. Search on Bibsonomy IEEE Access The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
35Shaochong Lei, Zhen Wang, Zeye Liu 0002, Feng Liang A unified solution to reduce test power and test volume for Test-per-scan schemes. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
31Malav Shah Efficient scan-based BIST scheme for low power testing of VLSI chips. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF test-per-clock, test-per-scan, scan, partial scan, switching activity, test length
31Chien-In Henry Chen, Kiran George Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST]. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
29Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan Multimode scan: Test per clock BIST for IP cores. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF SoC, BIST, scan, digital testing
26Zhiyuan He 0002, Gert Jervan, Zebo Peng, Petru Eles Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment. Search on Bibsonomy DSD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici Power profile manipulation: a new approach for reducing test application time under power constraints. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
25P. Karpodinis, Dimitri Kagaris, Dimitris Nikolos Accumulator based Test-per-Scan BIST. Search on Bibsonomy IOLTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Seongmoon Wang, Sandeep K. Gupta 0001 LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation. Search on Bibsonomy ITC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
24Jacob Savir Distributed BIST Architecture to Combat Delay Faults. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF BIST, LFSR, delay test, MISR, LSSD, SRL
18Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy 0001 A Technique to Reduce Power and Test Application Time in BIST. Search on Bibsonomy IOLTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
18Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001 A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
11Snehal Udar, Dimitri Kagaris LFSR Reseeding with Irreducible Polynomials. Search on Bibsonomy IOLTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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