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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 9063 occurrences of 3443 keywords
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Results
Found 16149 publication records. Showing 16145 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
80 | Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer |
A new framework for static timing analysis, incremental timing refinement, and timing simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 102-107, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation |
77 | Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin |
How accurately can we model timing in a placement engine? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 801-806, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
differential timing analysis, linear programming, static timing analysis, timing-driven placement |
73 | John V. A. Janeri, Daylan B. Darby, Daniel D. Schnackenberg |
Building higher resolution synthetic clocks for signaling in covert timing channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSFW ![In: The Eighth IEEE Computer Security Foundations Workshop (CSFW '95), March 13-15, 1995, Kenmare, County Kerry, Ireland, pp. 85-, 1995, IEEE Computer Society, 0-8186-7033-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
higher resolution synthetic clocks, timing channel countermeasure, Boeing multilevel secure local area network, secure network server, internal timing channels, time reference clock granularity, fine-grained signaling clock, timing channel throughput, timing channel capacities, local area networks, security of data, worst-case analysis, covert timing channels |
69 | Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li 0001, Charles J. Alpert, Shyam Ramji, Chris Chu |
ITOP: integrating timing optimization within placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 83-90, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
placement, timing optimization, physical synthesis |
67 | Aloysius K. Mok, Guangtian Liu |
Early detection of timing constraint violation at runtime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 18th IEEE Real-Time Systems Symposium (RTSS '97), December 3-5, 1997, San Francisco, CA, USA, pp. 176-185, 1997, IEEE Computer Society, 0-8186-8268-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
timing constraint violation detection, timing constraint compliance, conditional guarantees, satisfiability checking algorithm, timing constraint monitoring, time terms, timing constraint specification, real-time systems, real time applications |
65 | Avi Efrati, Moshe Kleyner |
Timing analysis challenges for high speed CPUs at 90nm and below. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 42, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
64 | Jeffrey J. P. Tsai, Steve Jennhwa Yang, Yao-Hsiung Chang |
Timing Constraint Petri Nets and Their Application to Schedulability Analysis of Real-Time System Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 21(1), pp. 32-49, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
real-time systems, Petri nets, synthesis, timing analysis, Timing constraints, time Petri nets, timed Petri nets, specification and verification |
60 | Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta 0001 |
A timing-driven design and validation methodology for embedded real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(4), pp. 533-553, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
period assignment, period derivation, rate assignment, rate derivation, timing-driven codesign, requirements analysis, timing analysis, system-level design, performance verification |
58 | Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula |
Statistical timing analysis using bounds and selective enumeration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 16-21, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
57 | Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu 0001 |
Test structures for delay variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 109, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
57 | Louis Scheffer |
Explicit computation of performance as a function of process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 1-8, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
static timing, process variation, yield, statistical timing |
56 | Leo Motus, R. Kinksaar, Tonu Naks, M. Pall |
Enhancing object modelling technique with timing analysis capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 1st IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '95), November 6-10, 1995, Fort Lauderdale, Florida, USA, pp. 298-301, 1995, IEEE Computer Society, 0-8186-7123-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
enhanced object modelling technique, timing analysis capabilities, timing correctness, software implementation problems, specification problems, time-constraint elicitation, Q-model, noncontradiction analysis, time modelling requirements, performance, software engineering, real-time systems, real-time systems, data integrity, timing, scheduling algorithms, timing constraints, object-oriented methods, consistency checking, application domain, integrity checking, design problems |
55 | Shuo Zhou, Yi Zhu 0002, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng |
Timing model reduction for hierarchical timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 415-422, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
biclique-star replacement, hierarchical timing analysis |
54 | Tai M. Chung, Henry G. Dietz |
Static scheduling of hard real-time code with instruction-level timing accuracy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: Third International Workshop on Real-Time Computing Systems Application (RTCSA '96), October 30 - November 01, 1996, Seoul, Korea, pp. 203-, 1996, IEEE Computer Society, 0-8186-7626-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
timing fault, instruction-level timing accuracy, high-level language code, instruction-level, compiler code scheduling, genetic search algorithm, real-time systems, timing analysis, processor scheduling, search space |
54 | Lo Ko, Christopher A. Healy, Emily Ratliff, Robert D. Arnold, David B. Whalley, Marion G. Harmon |
Supporting the specification and analysis of timing constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 2nd IEEE Real-Time Technology and Applications Symposium, RTAS '96, Boston, MA, USA, June 10-12, 1996, pp. 170-178, 1996, IEEE Computer Society, 0-8186-7448-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
timing constraints analysis, real-time programmers, user-friendly environment, user specification, real-time systems, user interface, formal specification, timing, synchronisation, timing constraints, computer aided software engineering, C language, C program, project support environments |
53 | Zhuo Feng, Peng Li 0001 |
A methodology for timing model characterization for statistical static timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 725-729, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
53 | Mukund Sivaraman, Andrzej J. Strojwas |
Timing analysis based on primitive path delay fault identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 182-189, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
primitive path delay faults, correlated delay, floating mode, timing analysis, timing verification, false path, path delay fault testing |
52 | Ali Dasdan |
Efficient algorithms for debugging timing constraint violations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 50-56, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
over-constraint resolution, scheduling, high-level synthesis, constraint satisfaction, timing constraints, behavioral synthesis, rate analysis |
52 | Markus Lindgren, Hans Hansson, Henrik Thane |
Using measurements to derive the worst-case execution time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 15-22, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
execution time analysis, program flow analysis, low level timing information, low level timing analysis, program execution times, timing measurements, instrumented version, program fragments, non-exhaustive measurements, program paths, realistic processor model, scheduling, real-time systems, real time systems, embedded systems, worst-case execution time, pipeline processing, schedulability analysis, program diagnostics, architectural modeling, pipeline architectures, flow graphs, timing estimates, target architecture, system of linear equations |
51 | Steven Gianvecchio, Haining Wang |
Detecting covert timing channels: an entropy-based approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCS ![In: Proceedings of the 2007 ACM Conference on Computer and Communications Security, CCS 2007, Alexandria, Virginia, USA, October 28-31, 2007, pp. 307-316, 2007, ACM, 978-1-59593-703-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
detection, covert timing channels |
50 | Kurt Keutzer, Michael Orshansky |
From blind certainty to informed uncertainty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 37-41, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
49 | Christopher J. Thompson, Andrew L. Goertzen |
A Method for Determination of the Timing Stability of PET Scanners. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Medical Imaging ![In: IEEE Trans. Medical Imaging 24(8), pp. 1053-1057, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Aloysius K. Mok, Guangtian Liu |
Efficient Run-Time Monitoring of Timing Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 3rd IEEE Real-Time Technology and Applications Symposium, RTAS '97, Montreal, Canada, June 9-11, 1997, pp. 252-262, 1997, IEEE Computer Society, 0-8186-8016-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
49 | Vinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer |
Static timing analysis for self resetting circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 119-126, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
49 | Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim |
An Accurate Worst Case Timing Analysis for RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 21(7), pp. 593-604, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pipelined execution, real-time system, Cache memory, worst case execution time, RISC processor |
49 | Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita |
Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 288, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
overclocking, timing error detection, timing error recovery, fpga |
49 | Ho Kyoung Lee, Woo Jin Lee, Heung Seok Chae, Yong Rae Kwon |
Specification and analysis of timing requirements for real-time systems in the CBD approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 36(1-2), pp. 135-158, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Real-time system, Petri nets, Component, Timing analysis, Timing constraints, CBD, Compositional analysis |
49 | Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer |
TA-PSV - Timing Analysis for Partially Specified Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(1), pp. 73-88, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
timing analysis for partially specified vectors (TA-PSV), crosstalk test generation (ATPG), static timing analysis (STA), delay model |
47 | Uwe Fassnacht, Jürgen Schietke |
Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 325-331, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Timing, static timing analysis, timing optimization |
46 | Bhavana Thudi, David T. Blaauw |
Efficient switching window computation for cross-talk noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 84-91, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Ed Grochowski, Murali Annavaram, Paul Reed |
Implications of device timing variability on full chip timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 68, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
46 | Murali Annavaram, Ed Grochowski, Paul Reed |
Implications of Device Timing Variability on Full Chip Timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 37-45, 2007, IEEE Computer Society, 1-4244-0804-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Min Pan, Chris C. N. Chu, Hai Zhou 0001 |
Timing yield estimation using statistical static timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2461-2464, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Tobias Thiel |
Have I Really Met Timing? - Validating PrimeTime Timing Reports with Spice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 114-119, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Musab AlTurki, Dinakar Dhurjati, Dachuan Yu, Ajay Chander, Hiroshi Inamura |
Formal Specification and Analysis of Timing Properties in Software Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FASE ![In: Fundamental Approaches to Software Engineering, 12th International Conference, FASE 2009, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009, York, UK, March 22-29, 2009. Proceedings, pp. 262-277, 2009, Springer, 978-3-642-00592-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
45 | Guilan Dai, Rujuan Liu, Chongchong Zhao, Changjun Hu |
Timing Constraints Specification and Verification for Web Service Compositions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSCC ![In: Proceedings of the 3rd IEEE Asia-Pacific Services Computing Conference, APSCC 2008, Yilan, Taiwan, 9-12 December 2008, pp. 315-322, 2008, IEEE Computer Society, 978-0-7695-3473-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Dipankar Das 0002, P. P. Chakrabarti 0001, Rajeev Kumar 0004 |
Scenario-based timing verification of multiprocessor embedded applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(3), pp. 37:1-37:58, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
execution scenarios, real time systems, static timing analysis, Timing verification |
45 | David A. Papa, Tao Luo 0002, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li 0001, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov |
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 2-9, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
static timing analysis, timing-driven placement |
45 | Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia |
"Timing closure by design, " a high frequency microprocessor design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 712-717, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
chip integration, dynamic circuits0, CAD, methodology, microprocessor, timing analysis, PLA, timing closure |
43 | Wei-Tek Tsai, Hessam S. Sarjoughian, Wu Li, Xin Sun 0003 |
Timing specification and analysis for service-oriented simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SpringSim ![In: Proceedings of the 2009 Spring Simulation Multiconference, SpringSim 2009, San Diego, California, USA, March 22-27, 2009, 2009, SCS/ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
service-oriented simulation, timing specifications and analysis, DEVS |
43 | Shihheng Tsai, Chung-Yang Huang |
A false-path aware formal static timing analyzer considering simultaneous input transitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 25-30, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
critical path selection, multiple input transitioning, formal method, static timing analysis, false path |
43 | Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer |
SACI: statistical static timing analysis of coupled interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 241-246, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
coupled interconnect, sources of variation, crosstalk noise, statistical timing analysis |
43 | Mike Hutton, David Karchmer, Bryan Archell, Jason Govig |
Efficient static timing analysis and applications using edge masks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 174-183, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cut-path, multicycle, thru-x, FPGA, placement, timing analysis |
43 | Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan |
First-order incremental block-based statistical timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 331-336, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
variability, incremental, statistical timing |
43 | Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester |
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 848-854, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate |
43 | Rajesh K. Gupta 0001 |
A framework for interactive analysis of timing constraints in embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Forth International Workshop on Hardware/Software Codesign, CODES 1996, Pittsburgh, PA, USA, March 18-20, 1996, pp. 44-51, 1996, IEEE Computer Society, 0-8186-7243-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
constraint satisfiability, performance evaluation, real-time systems, embedded systems, timing, computability, logic design, satisfiability, timing constraints, interactive analysis, timing performance |
43 | Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan |
PEPPER - a timing driven early floorplanner. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 230-235, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay |
43 | Anirudh Devgan |
Accurate device modeling techniques for efficient timing simulation of integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 138-143, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
device modeling techniques, Fast-to-evaluate and Accurate Simplified Transistor, aggressive MOS technologies, FAST models, timing, AGES, circuit analysis computing, integrated circuits, circuit simulators, transient analysis, transistors, transistor, transient simulator, timing simulation, timing simulator, electronic engineering computing, semiconductor device models |
43 | Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray |
Concurrent timing optimization of latch-based digital systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 680-685, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period |
43 | Steve Brown, Germán Gutiérrez, Reed Nelson, Chris VanKrevelen |
A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 467-471, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
emitter-coupled logic, triple channel ATE controller, timing verniers, precision edge timing, drive waveforms, returning signals, system clock frequency, ECL, 500 MHz, 40 ps, timing, clocks, automatic test equipment, logic arrays, programmable controllers, gate array, high speed testing |
43 | Hatice Kose-Bagci, Frank Broz, Qiming Shen, Kerstin Dautenhahn, Chrystopher L. Nehaniv |
As Time Goes By: Representing and Reasoning About Timing in Human-Robot Interaction Studies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAAI Spring Symposium: It's All in the Timing ![In: It's All in the Timing, Papers from the 2010 AAAI Spring Symposium, Technical Report SS-10-06, Stanford, California, USA, March 22-24, 2010, 2010, AAAI. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
43 | Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula |
Statistical timing analysis using bounds and selective enumeration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 29-36, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
42 | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 266-271, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen |
Block based statistical timing analysis with extended canonical timing model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 250-253, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Cristinel Ababei, Kia Bazargan |
Timing Minimization by Statistical Timing hMetis-based Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 58-63, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
42 | Farid N. Najm, Noel Menezes |
Statistical timing analysis based on a timing yield model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 460-465, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
statistical timing analysis, principal components, timing yield |
41 | Parimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar |
Optimization strategies to improve statistical timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 476-481, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | Euiseok Hwang, Rohit Negi, B. V. K. Vijaya Kumar |
Extended Kalman Filter Based Acquisition Timing Recovery for Magnetic Recording Read Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2008, Beijing, China, 19-23 May 2008, pp. 1986-1990, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Chan-Gun Lee, Aloysius K. Mok, Prabhudev Konana |
Monitoring of Timing Constraints with Confidence Threshold Requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(7), pp. 977-991, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fault tolerance, Constraints, monitors, temporal logic, real-time and embedded systems |
41 | Chee Sing Lee 0002, Wei Ting Loke, Wenjuan Zhang, Yajun Ha |
Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 279-284, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, Jeff Piaget, Natesan Venkateswaran, Jeffrey G. Hemmett |
First-Order Incremental Block-Based Statistical Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2170-2180, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Aravind R. Nayak, John R. Barry, German S. Feyh, Steven W. McLaughlin |
Timing Recovery With Frequency Offset and Random Walk: Cramer-Rao Bound and a Phase-Locked Loop Postprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 54(10), pp. 1896-1896, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Aravind R. Nayak, John R. Barry, German S. Feyh, Steven W. McLaughlin |
Timing Recovery With Frequency Offset and Random Walk: Cramér-Rao Bound and a Phase- Locked Loop Postprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 54(11), pp. 2004-2013, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Chan-Gun Lee, Aloysius K. Mok, Prabhudev Konana |
Monitoring of Timing Constraints with Confidence Threshold Requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 3-5 December 2003, Cancun, Mexico, pp. 178-187, 2003, IEEE Computer Society, 0-7695-2044-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Sibin Mohan, Frank Mueller 0001 |
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real-Time and Embedded Technology and Applications Symposium ![In: Proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2008, April 22-24, 2008, St. Louis, Missouri, USA, pp. 285-294, 2008, IEEE Computer Society, 978-0-7695-3146-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
hybrid timing anlalysis, hardware/software interactions, real-time systems, embedded systems, computer architecture, timing analysis, worst-case execution time, out-of-order execution |
41 | Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang |
A methodology to improve timing yield in the presence of process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 448-453, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
timing analysis, gate sizing, timing yield |
41 | Peter A. Beerel, Ken S. Stevens, Hoshik Kim |
Relative Timing Based Verification of Timed Circuits and Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 115-124, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Relative Timing, Verification and Timed Circuits, Timing Constraints |
41 | Martin Foltin, Brian Foutz, Sean Tyler |
Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 158-163, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
timing analysis, VLSI design, timing model, circuit optimization |
41 | Karim Khordoc, Eduard Cerny |
Semantics and verification of action diagrams with linear timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(1), pp. 21-50, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
compatibility of interfaces, hardware interfaces, causality, timing verification, timing diagrams |
41 | Sung-Kwan Kim, Sang Lyul Min, Rhan Ha |
Efficient worst case timing analysis of data caching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 2nd IEEE Real-Time Technology and Applications Symposium, RTAS '96, Boston, MA, USA, June 10-12, 1996, pp. 230-240, 1996, IEEE Computer Society, 0-8186-7448-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
efficient worst case timing analysis, accurate timing analysis, pipelined execution, multiple memory locations, pointer based references, dynamic load/store instructions, WCET overestimation, global data flow analysis, benchmark programs, real-time systems, computational complexity, data caching, cache storage, instruction sets, reduced instruction set computing, data dependence analysis, cache block |
41 | Shuichi Oikawa, Hideyuki Tokuda |
Efficient timing management for user-level real-time threads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 1st IEEE Real-Time Technology and Applications Symposium, Chicago, Illinois, USA, May 15-17, 1995, pp. 27-32, 1995, IEEE Computer Society, 0-8186-6980-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
efficient timing management, user-level real-time threads, specified time, upcalled user-level scheduler, user-level scheduler overhead, shared user-level timers, shared kernel/user structure, upcall performance, scheduling, performance evaluations, software engineering, real-time systems, resource allocation, timing, shared memory systems, kernel, processor scheduling, software performance evaluation, operating system kernels, hints, virtual processor |
40 | Serge Egelman, Janice Y. Tsai, Lorrie Faith Cranor, Alessandro Acquisti |
Timing is everything?: the effects of timing and placement of online privacy indicators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI ![In: Proceedings of the 27th International Conference on Human Factors in Computing Systems, CHI 2009, Boston, MA, USA, April 4-9, 2009, pp. 319-328, 2009, ACM, 978-1-60558-246-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
website indicators, privacy, timing, mental models, privacy policies, usable privacy and security |
40 | Lei Ju 0001, Bach Khoa Huynh, Abhik Roychoudhury, Samarjit Chakraborty |
Timing analysis of esterel programs on general-purpose multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 48-51, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multiprocessor, timing analysis, synchronous language, esterel |
40 | Wilsaan M. Joiner, Mark Shelhamer |
A model of time estimation and error feedback in predictive timing behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Neurosci. ![In: J. Comput. Neurosci. 26(1), pp. 119-138, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Error feedback, Prediction, Timing, Saccade |
40 | Steven Gianvecchio, Haining Wang, Duminda Wijesekera, Sushil Jajodia |
Model-Based Covert Timing Channels: Automated Modeling and Evasion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAID ![In: Recent Advances in Intrusion Detection, 11th International Symposium, RAID 2008, Cambridge, MA, USA, September 15-17, 2008. Proceedings, pp. 211-230, 2008, Springer, 978-3-540-87402-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
traffic modeling, evasion, covert timing channels |
40 | Khaled R. Heloue, Farid N. Najm |
Parameterized timing analysis with general delay models and arbitrary variation sources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 403-408, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
nonlinear delay, parameterized timing analysis, variability |
40 | Stephan Thesing |
Modeling a system controller for timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Proceedings of the 6th ACM & IEEE International conference on Embedded software, EMSOFT 2006, October 22-25, 2006, Seoul, Korea, pp. 292-300, 2006, ACM, 1-59593-542-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
aiT, verification, static analysis, VHDL, timing analysis, WCET, worst-case execution time, avionics, peripherals |
40 | Alan Wassyng, Mark Lawford, Xiayong Hu |
Timing Tolerances in Safety-Critical Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FM ![In: FM 2005: Formal Methods, International Symposium of Formal Methods Europe, Newcastle, UK, July 18-22, 2005, Proceedings, pp. 157-172, 2005, Springer, 3-540-27882-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
timing tolerances, real-time, requirements, safety-critical |
40 | Alejandro Hevia, Marcos A. Kiwi |
Strength of two data encryption standard implementations under timing attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Inf. Syst. Secur. ![In: ACM Trans. Inf. Syst. Secur. 2(4), pp. 416-437, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
cryptography, cryptanalysis, data encryption standard, timing attack |
40 | Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury |
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 175-180, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
spice verification, primary-path, secondary-path, timing analysis, assertion, assertibility |
40 | S. Balajee, Ananta K. Majhi |
Automated AC (Timing) Characterization for Digital Circuit Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 374-377, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Timing Characterization, STIL, Setup and Hold Time |
40 | Supratik Chakraborty, David L. Dill, Kun-Yung Chang, Kenneth Y. Yun |
Timing Analysis of Extended Burst-Mode Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 101-111, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Extended burst-mode circuits, 3D design style, global timing constraints, uncertain component delays, thirteen-valued signal algebra, polynomial-time |
39 | Zhuo Li 0001, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou |
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 75-82, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
gate duplication, physical synthesis, timing-driven placement |
39 | Ratnakar Goyal, Harindranath Parameswaran, Sachin Shrivastava |
Computation of Waveform Sensitivity Using Geometric Transforms for SSTA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 373-378, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Timing Library, Accuracy, SSTA |
39 | Salim Chowdhury, John Lillis |
Repeater insertion for concurrent setup and hold time violations with power-delay trade-off. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 59-66, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
early-mode timing, hold violation, late-mode timing, setup violation, timing optimization, repeater insertion |
39 | Aloysius K. Mok, Duu-Chung Tsou, Ruud C. M. de Rooij |
The MSP.RTL real-time scheduler synthesis tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), December 4-6, 1996, Washington, DC, USA, pp. 118-128, 1996, IEEE Computer Society, 0-8186-7689-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
MSP RTL real time scheduler synthesis tool, scheduler synthesis algorithm, real time scheduling problem, temporal constraint satisfaction problem, temporal constraint graph, input timing specification, incremental positive cycle detection algorithm, real time scheduling theory, Boeing 777 Integrated Airplane Information Management System, AIMS, constraint satisfaction, processor scheduling, timing constraints, resource constraints, application domains, search strategies, cyclic schedules, feasible schedule, timing semantics, real time logic |
39 | Tapan J. Chakraborty, Vishwani D. Agrawal |
Simulation of at-speed tests for stuck-at faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 216-220, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test |
39 | Hai Zhou 0001 |
Clock schedule verification with crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 78-83, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
verification, delay, coupling, clock schedule |
39 | Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer |
Minimum-power retiming for dual-supply CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 43-49, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
dual-supply, retiming theory, low-power, synthesis, low-power design |
39 | Kanak Agarwal, Dennis Sylvester, David T. Blaauw |
A library compatible driving point model for on-chip RLC interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 63-69, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
39 | Baris Taskin, Ivan S. Kourtev |
Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 111-118, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
optimization, linear programming, clock skew, cycle stealing |
38 | Bing Li 0005, Christoph Knoth, Walter Schneider 0001, Manuel Schmidt, Ulf Schlichtmann |
Static Timing Model Extraction for Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 156-166, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen |
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 83-88, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | David E. Wallace, Carlo H. Séquin |
Plug-in timing models for an abstract timing verifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 683-689, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
38 | Liangjun Shao, Peng Song, Yufan Yan, Xintao Zhang, Mianjun Xiao, Fang Liu, Huajun Liu, Timing Qu |
Numerical Analysis of Screening-Current Induced Strain in a 16 T REBCO Insert Within a 20 T Background Field. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 115392-115402, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
38 | Yimin Dou, Kewen Li, Hongjie Duan, Timing Li, Lin Dong, Zongchao Huang |
MDA GAN: Adversarial-Learning-Based 3-D Seismic Data Interpolation and Reconstruction for Complex Missing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Geosci. Remote. Sens. ![In: IEEE Trans. Geosci. Remote. Sens. 61, pp. 1-14, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
38 | Zhihao Liu, Yuanyuan Shang, Timing Li, Guanlin Chen, Yu Wang 0106, Qinghua Hu, Pengfei Zhu 0001 |
Robust Multi-Drone Multi-Target Tracking to Resolve Target Occlusion: A Benchmark. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multim. ![In: IEEE Trans. Multim. 25, pp. 1462-1476, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
38 | Yimin Dou, Timing Li, Kewen Li, Hongjie Duan, Zhifeng Xu |
ContrasInver: Voxel-wise Contrastive Semi-supervised Learning for Seismic Inversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2302.06441, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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38 | Yimin Dou, Kewen Li, Jianbing Zhu, Timing Li, Shaoquan Tan, Zongchao Huang |
MD Loss: Efficient Training of 3-D Seismic Fault Segmentation Network Under Sparse Labels by Weakening Anomaly Annotation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Geosci. Remote. Sens. ![In: IEEE Trans. Geosci. Remote. Sens. 60, pp. 1-14, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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38 | Yimin Dou, Kewen Li, Hongjie Duan, Timing Li, Lin Dong, Zongchao Huang |
MDA GAN: Adversarial-Learning-based 3-D Seismic Data Interpolation and Reconstruction for Complex Missing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2204.03197, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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