Search results for "timing-driven"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
68	Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li 0001, Charles J. Alpert, Shyam Ramji, Chris Chu	ITOP: integrating timing optimization within placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, timing optimization, physical synthesis
65	Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta 0001	A timing-driven design and validation methodology for embedded real-time systems.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	period assignment, period derivation, rate assignment, rate derivation, timing-driven codesign, requirements analysis, timing analysis, system-level design, performance verification
57	Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng	Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis.	FPL	2004	DBLP DOI BibTeX RDF
55	Zhuo Li 0001, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou	Ultra-fast interconnect driven cell cloning for minimizing critical path delay.	ISPD	2010	DBLP DOI BibTeX RDF	gate duplication, physical synthesis, timing-driven placement
54	Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang	Timing-driven Steiner trees are (practically) free.	DAC	2006	DBLP DOI BibTeX RDF	arborescence, timing-driven, rectilinear Steiner tree
51	Anmol Mathur, Kuang-Chien Chen, C. L. Liu 0001	Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs.	FPGA	1995	DBLP DOI BibTeX RDF
48	Alexander Marquardt, Vaughn Betz, Jonathan Rose	Timing-driven placement for FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
47	Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin	A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
47	Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai	A Timing-Driven Block Placer Based on Sequence Pair Model.	ASP-DAC	1999	DBLP DOI BibTeX RDF	timing-driven, building block placement, sequence pair, simulated annealing algorithm
47	Keith So	Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals.	FPGA	2008	DBLP DOI BibTeX RDF	lexicographic search, negotiated congestion, timing-driven routing, FPGA
46	Seokjin Lee, D. F. Wong 0001	Timing-driven routing for FPGAs based on Lagrangian relaxation.	ISPD	2002	DBLP DOI BibTeX RDF	timing-driven routing, FPGA, Lagrangian relaxation
44	Jin-Tai Yan	Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	octilinear Steiner tree, Global routing, Elmore delay, Steiner points
44	Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh	Timing-driven placement using design hierarchy guided constraint generation.	ICCAD	2002	DBLP DOI BibTeX RDF
43	Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin	Timing driven force directed placement with physical net constraints.	ISPD	2003	DBLP DOI BibTeX RDF	net constraints, timing driven placement, force directed placement
43	Jaewon Kim, Sung-Mo Kang	A timing-driven data path layout synthesis with integer programming.	ICCAD	1995	DBLP DOI BibTeX RDF	routing, integer programming, timing-driven placement, data path, bit-slice
43	Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh	TIGER: an efficient timing-driven global router for gate array and standard cell layout design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
41	Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen	Sensitivity guided net weighting for placement driven synthesis.	ISPD	2004	DBLP DOI BibTeX RDF	interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight
41	Haoxing Ren, David Zhigang Pan, David S. Kung 0001	Sensitivity guided net weighting for placement driven synthesis.	ISPD	2004	DBLP DOI BibTeX RDF	interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight
40	Di Wu 0017, Jiang Hu, Min Zhao 0001, Rabi N. Mahapatra	Timing driven track routing considering coupling capacitance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
40	Keoncheol Shin, Taewhan Kim	Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
40	Puneet Gupta 0001, Andrew B. Kahng, Stefanus Mantik	A Proposal for Routing-Based Timing-Driven Scan Chain Ordering.	ISQED	2003	DBLP DOI BibTeX RDF
39	Luca Sterpone	Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	fault tolerance, FPGA, Single Event Upset, Triple Modular Redundancy, Timing-driven Placement
39	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
38	Jin-Tai Yan, Zhi-Wei Chen	Resource-constrained timing-driven link insertion for critical delay reduction.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	critical delay, link insertion, non-tree
37	Tao Luo 0002, David A. Papa, Zhuo Li 0001, Chin Ngai Sze, Charles J. Alpert, David Z. Pan	Pyramids: an efficient computational geometry-based approach for timing-driven placement.	ICCAD	2008	DBLP DOI BibTeX RDF
36	Tao Luo 0002, David Newmark, David Z. Pan	A new LP based incremental timing driven placement for high performance designs.	DAC	2006	DBLP DOI BibTeX RDF
36	Shih-Lian T. Ou, Massoud Pedram	Timing-driven placement based on partitioning with dynamic cut-net control.	DAC	2000	DBLP DOI BibTeX RDF
36	Kenneth Eguro, Scott Hauck	Enhancing timing-driven FPGA placement for pipelined netlists.	DAC	2008	DBLP DOI BibTeX RDF	timing-driven, FPGA, simulated annealing, pipelined, placement
35	Lijuan Luo, Qiang Zhou 0001, Yici Cai, Xianlong Hong, Yibo Wang	A novel technique integrating buffer insertion into timing driven placement.	ISCAS	2006	DBLP DOI BibTeX RDF
35	Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal	An LP-based methodology for improved timing-driven placement.	ASP-DAC	2005	DBLP DOI BibTeX RDF
35	PariVallal Kannan, Dinesh Bhatia	Interconnect Estimation for FPGAs under Timing Driven Domains.	ICCD	2003	DBLP DOI BibTeX RDF
35	Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita	Speeding up technology-independent timing optimization by network partitioning.	ICCAD	1997	DBLP DOI BibTeX RDF
34	Jin-Tai Yan, Tzu-Ya Wang, Yu-Cheng Lee	Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
34	Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown	Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
34	Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen	Efficient timing closure without timing driven placement and routing.	DAC	2004	DBLP DOI BibTeX RDF	digital design flow, gate sizing, placement and routing, timing closure
33	Jingyu Xu, Xianlong Hong, Tong Jing	Timing-driven global routing with efficient buffer insertion.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
33	Ashwin K. Kumaraswamy, Ahmet T. Erdogan, Indrajit Atluri	Development of Timing Driven IP Design Flow based on Physical Knowledge Synthesis.	IWSOC	2004	DBLP DOI BibTeX RDF
32	Kenneth Eguro, Scott Hauck	Armada: timing-driven pipeline-aware routing for FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	pipeline FPGA, pipeline routing, reconfigurable computing
32	Keoncheol Shin, Taewhan Kim	An integrated approach to timing-driven synthesis and placement of arithmetic circuits.	ASP-DAC	2004	DBLP DOI BibTeX RDF
32	Yao-Wen Chang, Kai Zhu 0001, D. F. Wong 0001	Timing-driven routing for symmetrical array-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	field-programmable gate array, synthesis, layout, computer-aided design of VLSI
31	Mihir R. Choudhury, Kartik Mohanram	Timing-driven optimization using lookahead logic circuits.	DAC	2009	DBLP DOI BibTeX RDF	logic synthesis, timing optimization, lookahead
31	Hsin-Hsiung Huang, Hui-Yu Huang, Yu-Cheng Lin, Tsai-Ming Hsieh	Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system.	ISCAS	2008	DBLP DOI BibTeX RDF
31	Andrew B. Kahng, Qinke Wang	An analytic placer for mixed-size placement and timing-driven placement.	ICCAD	2004	DBLP DOI BibTeX RDF
31	R. V. Raj, N. S. Murty, P. S. Nagendra Rao, Lalit M. Patnaik	Effective Heuristics for Timing Driven Constructive Placement.	VLSI Design	1997	DBLP DOI BibTeX RDF
31	Debjit Sinha, Narendra V. Shenoy, Hai Zhou 0001	Statistical Timing Yield Optimization by Gate Sizing.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
31	Cristinel Ababei, Kia Bazargan	Timing Minimization by Statistical Timing hMetis-based Partitioning.	VLSI Design	2003	DBLP DOI BibTeX RDF
31	Bill Halpin, Naresh Sehgal, C. Y. Roger Chen	Detailed Placement with Net Length Constraints.	IWSOC	2003	DBLP DOI BibTeX RDF
30	Chanseok Hwang, Massoud Pedram	Timing-driven placement based on monotone cell ordering constraints.	ASP-DAC	2006	DBLP DOI BibTeX RDF
30	Bo Hu	Timing-driven placement for heterogeneous field programmable gate array.	ICCAD	2006	DBLP DOI BibTeX RDF
30	Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown	Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.	SLIP	2006	DBLP DOI BibTeX RDF
30	Shihliang Ou, Massoud Pedram	Timing-Driven Bipartitioning with Replication Using Iterative Quadratic Programming.	ASP-DAC	1999	DBLP DOI BibTeX RDF
29	David A. Papa, Tao Luo 0002, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li 0001, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov	RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.	ISPD	2008	DBLP DOI BibTeX RDF	static timing analysis, timing-driven placement
29	Gang Chen 0020, Jason Cong	Simultaneous timing-driven placement and duplication.	FPGA	2005	DBLP DOI BibTeX RDF	logic duplication, FPGA, legalization, timing-driven placement, redundancy removal
29	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Fast timing-driven partitioning-based placement for island style FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	FPGA placement, partitioning based placement, FPGAs, timing-driven placement
29	Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan	PEPPER - a timing driven early floorplanner.	ICCD	1995	DBLP DOI BibTeX RDF	PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay
29	Dimitrios Karayiannis, Spyros Tragoudas	Uniform area timing-driven circuit implementation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	circuit module, cell library, input-output paths, overall area, timing-driven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NP-hard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay
29	Hsin-Hsiung Huang, Shu-Ping Chang, Yu-Cheng Lin, Tsai-Ming Hsieh	Timing-driven X-architecture router among rectangular obstacles.	ISCAS	2008	DBLP DOI BibTeX RDF
29	Qinghua Liu, Bo Hu 0006, Malgorzata Marek-Sadowska	Individual wire-length prediction with application to timing-driven placement.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
29	Seokjin Lee, Martin D. F. Wong	Timing-driven routing for FPGAs based on Lagrangian relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
29	Jason Cong, Michail Romesis, Min Xie 0004	Optimality and Stability Study of Timing-Driven Placement Algorithms.	ICCAD	2003	DBLP DOI BibTeX RDF
29	Anmol Mathur, C. L. Liu 0001	Timing-driven placement for regular architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
28	Jacob White 0001, Jacob Avidan, Ibrahim Abe M. Elfadel, D. F. Wong 0001	Advances in transistor timing, simulation, and optimization (tutorial abstract).	ICCAD	1999	DBLP DOI BibTeX RDF
27	Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim	Placement for configurable dataflow architecture.	ASP-DAC	2005	DBLP DOI BibTeX RDF
27	Michael D. Moffitt, David A. Papa, Zhuo Li 0001, Charles J. Alpert	Path smoothing via discrete optimization.	DAC	2008	DBLP DOI BibTeX RDF	static timing analysis, timing-driven placement
27	Sherief Reda, Amit Chowdhary	Effective linear programming based placement methods.	ISPD	2006	DBLP DOI BibTeX RDF	relative placement, whitespace management, linear programming, timing-driven placement
27	Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten	Performance driven standard-cell placement using the genetic algorithm.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	connection length, timing-driven placer, /spl alpha/-criticality, delay performance improvement, genetic algorithms, genetic algorithm, delays, timing, logic CAD, circuit layout CAD, cellular arrays, integrated circuit layout, critical paths, area, propagation delays, wire length, timing performance, IC design, standard-cell placement
26	Jinpeng Zhao, Qiang Zhou 0001, Yici Cai	Fast congestion-aware timing-driven placement for island FPGA.	DDECS	2009	DBLP DOI BibTeX RDF
26	Milos Hrkic, John Lillis, Giancarlo Beraudo	An Approach to Placement-Coupled Logic Replication.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
26	Andrew B. Kahng, Stefanus Mantik, Igor L. Markov	Min-max placement for large-scale timing optimization.	ISPD	2002	DBLP DOI BibTeX RDF
25	Shih-Hsu Huang, Yi-Siang Hsu	A timing driven approach for crosstalk minimization in gridded channel routing.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
25	Sung-Woo Hur, Ashok Jagannathan, John Lillis	Timing-driven maze routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
25	Haoxing Ren, David Zhigang Pan, David S. Kung 0001	Sensitivity guided net weighting for placement-driven synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
25	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	False Path and Clock Scheduling Based Yield-Aware Gate Sizing.	VLSI Design	2005	DBLP DOI BibTeX RDF
24	Rashmi Mehrotra, Tom English, Michel P. Schellekens, Steve Hollands, Emanuel M. Popovici	Timing-Driven Power Optimisation and Power-Driven Timing Optimisation of Combinational Circuits.	J. Low Power Electron.	2011	DBLP DOI BibTeX RDF
24	Huan Ren, Shantanu Dutt	Constraint satisfaction in incremental placement with application to performance optimization under power constraints.	ICCD	2007	DBLP DOI BibTeX RDF
24	S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, Donald Cottrell, David Mallis, S. DasGupta, Joseph Morrell, Amrich Chokhavtia	CHDStd - application support for reusable hierarchical interconnect timing views.	ISPD	1998	DBLP DOI BibTeX RDF
24	Bernd Obermeier, Frank M. Johannes	Quadratic placement using an improved timing model.	DAC	2004	DBLP DOI BibTeX RDF	Steiner tree net model, optimization potential, sensitivity, Quadratic placement, timing driven placement
24	Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna Parasuram, Amit Chowdhary, Vladimir Tiourin, Bill Halpin	Force directed mongrel with physical net constraints.	DAC	2003	DBLP DOI BibTeX RDF	mongrel, net constraints, timing driven placement, force directed placement
24	Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen	An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.	ICCAD	1996	DBLP DOI BibTeX RDF	LUT-Based FPGA Technology Mapping, Area/Performance Trade-Off and Timing Driven FPGA Synthesis
23	Hosung (Leo) Kim, John Lillis	A framework for layout-level logic restructuring.	ISPD	2008	DBLP DOI BibTeX RDF	logic resynthesis, timing optimization
23	Bin Liu 0007, Yici Cai, Qiang Zhou 0001, Xianlong Hong	Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
23	Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez	Unification of Budgeting and Placement.	DAC	1997	DBLP DOI BibTeX RDF
22	Shiyan Hu, Zhuo Li 0001, Charles J. Alpert	A faster approximation scheme for timing driven minimum cost layer assignment.	ISPD	2009	DBLP DOI BibTeX RDF	dynamic programming, np-complete, oracle, fully polynomial time approximation scheme, layer assignment
22	Shiyan Hu, Zhuo Li 0001, Charles J. Alpert	A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion.	DAC	2009	DBLP DOI BibTeX RDF	dynamic programming, NP-complete, buffer insertion, fully polynomial time approximation scheme, cost minimization
22	Shantanu Dutt, Hasan Arslan	Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations.	DATE	2006	DBLP DOI BibTeX RDF
22	Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu	A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design.	ASP-DAC	2004	DBLP DOI BibTeX RDF
22	Jerry C.-Y. Kao, C.-F. Su, Allen C.-H. Wu	High-performance FIR generation based on a timing-driven architecture and component selection method.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
22	Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu	An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
22	Amir H. Ajami, Massoud Pedram	Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points.	ASP-DAC	2001	DBLP DOI BibTeX RDF
22	Ankur Srivastava 0001, Chunhong Chen, Majid Sarrafzadeh	Timing driven gate duplication in technology independent phase.	ASP-DAC	2001	DBLP DOI BibTeX RDF
22	Suphachai Sutanthavibul, Eugene Shragowitz	An Adaptive Timing-Driven Layout for High Speed VLSI.	DAC	1990	DBLP DOI BibTeX RDF
21	Ke Cao, Jiang Hu, Mosong Cheng	Wire Sizing and Spacing for Lithographic Printability and Timing Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	H. Chang, Eugene Shragowitz, Jian Liu, Habib Youssef, Bing Lu, Suphachai Sutanthavibul	Net criticality revisited: an effective method to improve timing in physical design.	ISPD	2002	DBLP DOI BibTeX RDF	criticality metrics, net delay bound, routing, placement
20	Puneet Gupta 0001, Andrew B. Kahng, Stefanus Mantik	Routing-aware scan chain ordering.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	testing, Layout, scan chain
20	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Sequential delay budgeting with interconnect prediction.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
20	Andrew B. Kahng, Xu Xu 0001	Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
20	Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur	Integrating DFT in the Physical Synthesis Flow.	ITC	2002	DBLP DOI BibTeX RDF
20	Dimitrios Mangiras, Apostolos Stefanidis, Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos	Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
20	Mateus Fogaça, Guilherme Flach, Jucemar Monteiro, Marcelo O. Johann, Ricardo Reis 0001	Quadratic timing objectives for incremental timing-driven placement optimization.	ICECS	2016	DBLP DOI BibTeX RDF
20	Andrey Ayupov, Leonid Kraginskiy	A novel timing-driven placement algorithm using smooth timing analysis.	EWDTS	2008	DBLP DOI BibTeX RDF