Search results for "Arrays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Itsuo Takanami	Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement.	DFT	2001	DBLP DOI BibTeX RDF	built-in selft-reconfiguration, digital neural circuit, direct spare replacement, fault-tolerance, mesh-connected processor array
31	Pascal R. Serrarens	Distributed Arrays in the Functional Language Concurrent Clean.	Euro-Par	1997	DBLP DOI BibTeX RDF
31	Ding-Ming Kwai, Behrooz Parhami	FFT computation with linear processor arrays using a data-driven control scheme.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
31	Yin Chan, Sun-Yuan Kung	Bit Level Block Matching Systolic Arrays.	ASAP	1995	DBLP DOI BibTeX RDF	bit level systolic array, video signal processing architecture, pipeline, block matching
31	Stephen M. Mansour	Using Defined Operators and Function Arrays to Solve Non-Linear Equations in APL2.	APL	1993	DBLP DOI BibTeX RDF	APL
31	John T. O'Donnell	Data Parallel Implementation of Extensible Sparse Functional Arrays.	PARLE	1993	DBLP DOI BibTeX RDF
31	Shojiro Sakata	Finding a Minimal Polynomial Vector Set of a Vector of nD Arrays.	AAECC	1991	DBLP DOI BibTeX RDF
31	Nam Ling, Magdy A. Bayoumi	Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
31	Andreas Werder	Arrays of Objects in Rationalized APL.	APL	1988	DBLP DOI BibTeX RDF	APL
31	André DeHon	Design of programmable interconnect for sublithographic programmable logic arrays.	FPGA	2005	DBLP DOI BibTeX RDF	Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect
31	André DeHon, Michael J. Wilson	Nanowire-based sublithographic programmable logic arrays.	FPGA	2004	DBLP DOI BibTeX RDF	sublithographic architecture, programmable logic arrays, nanowires
30	Theo Mayer	The 4K format implications for visualization, VR, command & control and special venue application.	EDT	2007	DBLP DOI BibTeX RDF	1080, 2K, 4K, SXGA, SXRD, XGA, blended arrays, cube walls, edge blend, monitor arrays, projected arrays, special venue, video resolution, visualization, VR, video, command and control, HDTV
30	Renée C. Bryce, Charles J. Colbourn	Test prioritization for pairwise interaction coverage.	ACM SIGSOFT Softw. Eng. Notes	2005	DBLP DOI BibTeX RDF	biased covering arrays, pairwise interaction coverage, greedy algorithm, covering arrays, software interaction testing, mixed-level covering arrays
30	Renée C. Bryce, Charles J. Colbourn	Test prioritization for pairwise interaction coverage.	A-MOST	2005	DBLP DOI BibTeX RDF	biased covering arrays, pairwise interaction coverage, greedy algorithm, covering arrays, software interaction testing, mixed-level covering arrays
30	Renée C. Bryce, Charles J. Colbourn	Constructing interaction test suites with greedy algorithms.	ASE	2005	DBLP DOI BibTeX RDF	biased covering arrays, t-way interaction coverage, greedy algorithm, covering arrays, software interaction testing, mixed-level covering arrays
30	Yao-Wen Chang, D. F. Wong 0001, C. K. Wong	Design and analysis of FPGA/FPIC switch modules.	ICCD	1995	DBLP DOI BibTeX RDF	FPGA/FPIC switch modules, routing resources, FPIC, network-flow techniques, field programmable interconnect chip, field programmable gate arrays, FPGA, field programmable gate arrays, logic design, heuristic algorithm, programmable logic arrays, routability
30	Charles L. Seitz	Concurrent VLSI Architectures.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	Computational arrays, logic-enhanced memories, microcomputer arrays, smart memories, parallel processing, VLSI, multiprocessors, systolic arrays, concurrent computation
30	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, dynamic programming, systolic array, throughput optimization, recurrences
30	Shinya Kubota, Minoru Watanabe	A nine-context programmable optically reconfigurable gate array with semiconductor lasers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	holographic memory, optically reconfigurable gate arrays, field programmable gate arrays
30	Jarek Nieplocha, Robert J. Harrison	Shared Memory Programming in Metacomputing Environments: The Global Array Approach.	J. Supercomput.	1997	DBLP DOI BibTeX RDF	NUMA memory architecture, Metacomputing, shared-memory programming, distributed arrays, global arrays
30	Trenchard More Jr.	Transfinite Nesting in Array-Theoretic Figures, Changes, Rigs, and Arms, Part I.	APL	1993	DBLP DOI BibTeX RDF	APL2, Nial, array theory, function arrays, nested arrays, APL, formal systems
29	Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein	Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments.	SCCC	2003	DBLP DOI BibTeX RDF	Reconfigurable Systolic Arrays, Fast Fourier Transform, Rewriting-Logic, Term Rewriting Systems
28	Troels Pedersen, Claus Pedersen, Xuefeng Yin, Bernard H. Fleury	Optimization of Spatiotemporal Apertures in Channel Sounding.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
28	Lian Li 0002, Hui Wu 0001, Hui Feng, Jingling Xue	Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
28	Ronald I. Frank	A generating function that counts the combinatorial full-span sub array structure of a regular array with some applications to APL.	APL	2003	DBLP DOI BibTeX RDF	array structure, null-array expansion, sub array, APL
28	Sitaram Yadavalli, Sandip Kundu	On Fault-Simulation Through Embedded Memories On Large Industrial Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
28	Martin Kutrib, Jan-Thomas Löwe	Massively Parallel Pattern Recognition with Link Failures.	SOFSEM	2000	DBLP DOI BibTeX RDF
28	Patrick M. Lenders, Sanjay V. Rajopadhye	Multirate VLSI Arrays and Their Synthesis.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	Application specific processor arrays, index transformations, VLSI signal processing, systolic arrays, space-time mappings
28	Oleg A. Panfilov	Performance analysis of RAID-5 disk arrays.	HICSS (1)	1995	DBLP DOI BibTeX RDF	peripheral interfaces, RAID-5 disk arrays, SCSIs, application dependent read/write ratio, performance evaluation, performance analysis, storage management, disk arrays, magnetic disc storage, files, system throughput, nonlinear function
28	Shih-Yuang Su, Cheng-Wen Wu	Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	sequential faults, ILA, M-testability, constant-length test sequence, pipelined array multiplier, sequential fault testing, logic testing, logic testing, sequential circuits, test pattern generation, logic arrays, combinatorial circuits, test vectors, C-testability, iterative logic arrays, iterative logic array
28	Pen-Yuang Chang, Jong-Chuang Tsay	A Family of Efficient Regular Arrays for Algebraic Path Problem.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	efficient regular arrays, dependence graph decomposition, multiple phases, m-phase schedule function, cylindrical array, spherical array, parallel algorithms, parallel algorithms, computational complexity, graph theory, systolic arrays, systolic array, matrix multiplication, matrix algebra, VLSI architecture, execution times, transitive closure, orthogonal array, algebraic path problem
28	Edward K. Lee 0001, Randy H. Katz	The Performance of Parity Placements in Disk Arrays.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	redundant arrays of inexpensive disks, parity placements, parity encoding, performance, fault tolerant computing, redundancy, power consumption, RAID, disk arrays, magnetic disc storage, disk failures
28	Chein-Wei Jen, Ding-Ming Kwai	Data Flow Representation of Iterative Algorithms for Systolic Arrays.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	data flow representation, algebraic representation, modeling, parallel architectures, systolic arrays, systolic arrays, digital arithmetic, generating function, iterative algorithms, dependence graph, power series, geometric representation
28	Krishna P. Belkhale, Prithviraj Banerjee	Reconfiguration Strategies for VLSI Processor Arrays and Trees Using a Modified Diogenes Approach.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	reconfiguration strategies, VLSI processor arrays, Diogenes approach, rectangular arrays, VLSI, fault tolerant computing, trees, trees (mathematics), circuit layout CAD, complete binary tree
28	Yiwan Wong, Jean-Marc Delosme	Optimization of Computation Time for Systolic Arrays.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	multiple functional units, pipelined functional units, computation time minimization, linear scheduling function, bounded search space, parallel algorithms, concurrency, multiprocessor interconnection networks, systolic arrays, systolic arrays, minimisation, combinatorial optimization problem, branch-and-bound method
28	Parthasarathy P. Tirumalai, Jon T. Butler	Minimization Algorithms for Multiple-Valued Programmable Logic Arrays.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	minimisation algorithms, multiple-valued programmable logic arrays, sum-of products, MIN operation, random-symmetric functions, constrained implicant sets, charge-coupled device circuits, performance, CMOS, heuristic algorithms, many-valued logics, minimisation, CMOS integrated circuits, backtracking, logic arrays, tree search, multiple-valued functions, charge-coupled device
28	Viktor K. Prasanna, Yu-Chen Tsai	On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	optimal family of linear systolic arrays, local storage, fault wafer scale integration models, VLSI, delay, systolic arrays, matrix multiplication, circuit layout CAD, processing elements
28	Abhijit Chatterjee, Jacob A. Abraham	Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	cell states model, two-dimensional iterative logic arrays, ILA cell truth table, cell interconnection structure, bilateral direction, signal flow, horizontal axis, logic testing, graphs, test generation, integrated circuit testing, automatic testing, logic arrays, test set, N-cube
28	Bruno Codenotti, Roberto Tamassia	A Network Flow Approach to the Reconfiguration of VLSI Arrays.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	network flow approach, VLSI arrays, faulty cells, network flow model, functional cells, fault-free array, Manhattan model, VLSI, reconfiguration, systolic arrays, fault location
28	Amitava Majumdar 0002, Cauligi S. Raghavendra, Melvin A. Breuer	Fault Tolerance in Linear Systolic Arrays Using Time Redundancy.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	triple time redundancy, gracefully degradable mode, fault tolerant computing, logic testing, reconfiguration, throughput, interconnection, switching, performance metrics, cellular arrays, running time, reliability analysis, control structures, fault-tolerant capabilities, linear systolic arrays
28	James Jacob, Nripendra N. Biswas	Further Comments on "Detection of Faults in Programmable Logic Arrays".	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	fault detection, fault location, programmable logic arrays, logic arrays
28	Christos Kaklamanis, Anna R. Karlin, Frank Thomson Leighton, Victor Milenkovic, Prabhakar Raghavan, Satish Rao, Clark D. Thomborson, A. Tsantilas	Asymptotically Tight Bounds for Computing with Faulty Arrays of Processors (Extended Abstract)	FOCS	1990	DBLP DOI BibTeX RDF	asymptotically tight bounds, random fault model, faulty arrays of processors, worst-case fault model, low-dimensional arrays, congestion embedding, route, sort, 3-D, systolic algorithms, knot theory, 2-D
28	Clement Wing Hong Lam, Hon Fung Li, R. Jayakumar	A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	faulty systolic arrays, faulty cells, square array, minimal fault pattern, fault tolerance, fault tolerant computing, redundancy, redundancy, cellular arrays
28	A. Yavuz Oruç, Ajai Thirumalai	A Systematic Design of Cellular Permutation Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	cellular permutation arrays, coset decompositions, permutation cell, coset generator, target network, multiprocessor interconnection networks, network topology, cellular arrays, cost function, propagation delay, fan-out, fan-in
28	Hon Fung Li, R. Jayakumar, Clement Wing Hong Lam	Restructuring for Fault-Tolerant Systolic Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fault-tolerant systolic arrays, faulty cells, data-flow paths, computational sites, programmable delays, fault tolerant computing, cellular arrays, restructuring, processing elements, data skewing
28	Adit D. Singh	Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	area efficient fault tolerance scheme, large area VLSI processor arrays, interstitial sites, operational spares, area efficient layouts, chip area utilization, interstitial redundancy, PE survival probabilities, VLSI, fault tolerant computing, reconfiguration, redundancy, polynomial time algorithm, cellular arrays, switching network, performance degradation, wafer scale integration, circuit layout
28	Alok Aggarwal, James K. Park	Notes on Searching in Multidimensional Monotone Arrays (Preliminary Version)	FOCS	1988	DBLP DOI BibTeX RDF	multidimensional monotone arrays, maximum entry, ith row, (i- 1)-st row, totally monotone, 22 subarray, 22 minor, two-dimensional totally monotone arrays, VLSI river routing, dynamic programming, searching, computational geometry, shortest paths, two-dimensional array
28	Vishwani D. Agrawal	Comments on "An Approach to Highly Integrated Computer-Maintained Cellular Arrays".	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	faults in logic arrays, percolation process, Cellular arrays, random processes, programmable logic
28	J. A. Bate, Jon C. Muzio	Three Cell Structures for Ternary Cellular Arrays.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	combinational switching functions, ternary full adder, universal arrays, Cellular arrays, symmetric functions, ternary logic
27	Josue Bracho-Ríos, Jose Torres-Jimenez, Eduardo Rodriguez-Tello	A New Backtracking Algorithm for Constructing Binary Covering Arrays of Variable Strength.	MICAI	2009	DBLP DOI BibTeX RDF	Software testing, Branch and Bound, Covering Arrays
27	Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang	A comparison of via-programmable gate array logic cell circuits.	FPGA	2009	DBLP DOI BibTeX RDF	logic cell, via-programmable gate arrays
27	José Aires, Gabriel Pereira Lopes, Joaquim Ferreira da Silva	Efficient multi-word expressions extractor using suffix arrays and related structures.	CIKM-iNEWS	2008	DBLP DOI BibTeX RDF	large corpus, multi-word expressions, extraction, suffix arrays, language independent
27	Nicolas Halbwachs, Mathias Péron	Discovering properties about arrays in simple programs.	PLDI	2008	DBLP DOI BibTeX RDF	sentinel, invariant synthesis, abstract interpretation, program verification, arrays, sorting algorithms
27	Jeffrey W. Chastine, Jon A. Preston	Teaching 2D arrays using real-time video filters.	SIGITE Conference	2005	DBLP DOI BibTeX RDF	real-time, programming, filters, teaching, two-dimensional arrays
27	Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky	Engineering a scalable placement heuristic for DNA probe arrays.	RECOMB	2003	DBLP DOI BibTeX RDF	DNA arrays, border minimization, probe placement
27	Chris H. Q. Ding	An Optimal Index Reshuffle Algorithm for Multidimensional Arrays and Its Applications for Parallel Architectures.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	index reshuffle, vacancy tracking cycles, global exchange, dynamic remapping, multidimensional arrays
27	Chor Ping Low	An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Degradable VLSI/WSI arrays, efficient heuristic, NP-completeness, greedy algorithm
27	Jürgen Bierbrauer, Holger Schellwat	Almost Independent and Weakly Biased Arrays: Efficient Constructions and Cryptologic Applications.	CRYPTO	2000	DBLP DOI BibTeX RDF	Low bias, almost independent arrays, Hermitian codes, Suzuki codes, Weil-Carlitz-Uchiyama bound, exponential sum method, Zyablov bound, authentication, Fourier transform, hashing, resiliency, Reed-Solomon codes
27	Min-Young Lee, Myong-Soon Park	Double parity sparing for performance improvement in disk arrays.	ICPADS	1996	DBLP DOI BibTeX RDF	double parity sparing, parity data, performance evaluation, storage management, performance improvement, disk arrays, magnetic disc storage, degradation
27	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
27	Jai Menon 0001	A Performance Comparison of RAID-5 and Log-Structured Arrays.	HPDC	1995	DBLP DOI BibTeX RDF	RAID-5, log-structured arrays, transaction-processing workloads, outboard disk controller, nonvolatile cache, physical disks, storage management, cache storage, performance comparison, compression ratio
27	Daniel Stodolsky, Mark Holland, William V. Courtright II, Garth A. Gibson	Parity-Logging Disk Arrays.	ACM Trans. Comput. Syst.	1994	DBLP DOI BibTeX RDF	RAID, disk arrays
27	Zicheng Guo, Rami G. Melhem	Embedding Binary X-Trees and Pyramids in Processor Arrays with Spanning Buses.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	binaryX-trees, spanning buses, 2-D arrayarchitectures, routing step, parallel architectures, multiprocessor interconnection networks, embedding, network routing, binary trees, processor arrays, pyramids, network embeddings
27	Catherine Mongenet, Guy-René Perrin	Synthesis of Systolic arrays for Inductive Problems.	PARLE (1)	1987	DBLP DOI BibTeX RDF	synthesis, systolic arrays
27	Charles J. Colbourn, Gerzson Kéri	Binary Covering Arrays and Existentially Closed Graphs.	IWCC	2009	DBLP DOI BibTeX RDF
27	David L. MacNair, Jun Ueda	Modeling & characterizing stochastic actuator arrays.	IROS	2009	DBLP DOI BibTeX RDF
27	Tao Xie 0004, Abhinav Sharma	Collaboration-Oriented Data Recovery for Mobile Disk Arrays.	ICDCS	2009	DBLP DOI BibTeX RDF
27	Charles J. Colbourn, Daniel W. McClary	Locating and detecting arrays for interaction faults.	J. Comb. Optim.	2008	DBLP DOI BibTeX RDF	Disjunct matrix, Locating array, Defecting array, Covering array, Orthogonal array, Cover-free family, Factorial design
27	Min Wang, Zhongxiang Shen	Nulling of Antenna Arrays Including the Mutual Coupling Effect.	VTC Spring	2008	DBLP DOI BibTeX RDF
27	Feifei Ma, Jian Zhang 0001	Finding Orthogonal Arrays Using Satisfiability Checkers and Symmetry Breaking Constraints.	PRICAI	2008	DBLP DOI BibTeX RDF
27	Matthieu Maitre, Yoshihisa Shinagawa, Minh N. Do	Symmetric multi-view stereo reconstruction from planar camera arrays.	CVPR	2008	DBLP DOI BibTeX RDF
27	Kento Emoto, Zhenjiang Hu, Kazuhiko Kakehi 0001, Masato Takeichi	A Compositional Framework for Developing Parallel Programs on Two-Dimensional Arrays.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	skeletal parallel programming, matrix, Constructive algorithmics
27	Wing-Kai Hon, Tak Wah Lam, Kunihiko Sadakane, Wing-Kin Sung, Siu-Ming Yiu	A Space and Time Efficient Algorithm for Constructing Compressed Suffix Arrays.	Algorithmica	2007	DBLP DOI BibTeX RDF
27	Wasim Q. Malik, David J. Edwards	Measured MIMO Capacity and Diversity Gain With Spatial and Polar Arrays in Ultra Wideband Channels.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
27	Wasim Q. Malik, David J. Edwards	Measured MIMO Capacity and Diversity Gain With Spatial and Polar Arrays in Ultrawideband Channels.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
27	I. Balmages, Boaz Rafaely	Open-Sphere Designs for Spherical Microphone Arrays.	IEEE Trans. Speech Audio Process.	2007	DBLP DOI BibTeX RDF
27	Richard A. Kiehl	Information processing in nanoscale arrays: DNA assembly, molecular devices, nano-array architectures.	ICCAD	2006	DBLP DOI BibTeX RDF	molecular devices, nanoarchitecture, self-assembly, nanoelectronics
27	Wing On Fung, Tughrul Arslan, Sami Khawam	Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays.	AHS	2006	DBLP DOI BibTeX RDF
27	Sergiy A. Vorobyov, Alex B. Gershman, Kon Max Wong	Maximum likelihood direction-of-arrival estimation in unknown noise fields using sparse sensor arrays.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
27	Boaz Rafaely	Analysis and design of spherical microphone arrays.	IEEE Trans. Speech Audio Process.	2005	DBLP DOI BibTeX RDF
27	Yulin Wang, Guangjun Li, Shuisheng Lin, Xiaojun Wu	A write-prior partitioning LRU algorithm for the multi-port cache in disk arrays.	CIT	2005	DBLP DOI BibTeX RDF
27	Wiebke S. Diestelkamp	Parameter Inequalities for Orthogonal Arrays with Mixed Levels.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	mixed-level orthogonal array, group character, adjacency operator
27	Elizabeth Varki, Arif Merchant, Jianzhang Xu, Xiaozhou Qiu	Issues and Challenges in the Performance Analysis of Real Disk Arrays.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF
27	Frank Hannig, Hritam Dutta, Jürgen Teich	Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology.	IPDPS	2004	DBLP DOI BibTeX RDF
27	Arunprasad P. Marathe, Kenneth Salem	Query processing techniques for arrays.	VLDB J.	2002	DBLP DOI BibTeX RDF	Array manipulation language, Array query optimization, Declarative query language, Pipelined evaluation, Memory-usage optimization, User-defined functions
27	Tak Wah Lam, Kunihiko Sadakane, Wing-Kin Sung, Siu-Ming Yiu	A Space and Time Efficient Algorithm for Constructing Compressed Suffix Arrays.	COCOON	2002	DBLP DOI BibTeX RDF
27	Steven J. E. Wilton	Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
27	Stephen M. Mansour	Houses, windows and DOHR's: (descriptive object of high rank).	APL	2000	DBLP DOI BibTeX RDF	APL, HTML
27	Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic	The memory/logic interface in FPGAs with large embedded memory arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
27	Pradip K. Jha, Steven Barnfield, John B. Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi	Synthesis of Arrays and Records.	ICCD	1999	DBLP DOI BibTeX RDF	Aggregate data types, Synthesis, Array, Record
27	Pieter van Rooyen, Ryuji Kohno, Ian J. Oppermann	DS-CDMA performance with maximum ratio combining and antenna arrays.	Wirel. Networks	1998	DBLP DOI BibTeX RDF
27	Yen-Tai Lai, Ping-Tsung Wang	Hierarchical interconnection structures for field programmable gate arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
27	Peter Fritzson, Roland Wismüller, Olav Hansen, Jonas Sala, Peter Skov	A Parallel Debugger with Support for Distributed Arrays, Multiple Executables and Dynamic Processes.	CC	1996	DBLP DOI BibTeX RDF
27	Leonid Libkin, Rona Machlin, Limsoon Wong	A Query Language for Multidimensional Arrays: Design, Implementation, and Optimization Techniques.	SIGMOD Conference	1996	DBLP DOI BibTeX RDF
27	Wei-keng Liao, Chao-Wei Ou, Sanjay Ranka	Dynamic Alignment and Distribution of Irregularly Coupled Data Arrays for Scalable Parallelization of Particle-in-Cell Problems.	IPPS	1996	DBLP DOI BibTeX RDF
27	Edward K. Lee 0001, Randy H. Katz	An Analytic Performance Model of Disk Arrays.	SIGMETRICS	1993	DBLP DOI BibTeX RDF
27	Weijia Shang, José A. B. Fortes	On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	adaptive-hash join algorithm, hybrid-hash, parallel algorithms, hypercube networks, file organisation, nested-loop, hypercube multicomputer
27	Ralph T. Hoctor, Saleem A. Kassam	High resolution coherent source location using transmit/receive arrays.	IEEE Trans. Image Process.	1992	DBLP DOI BibTeX RDF
27	Hideo Fujiwara	Enhancing random-pattern coverage of programmable logic arrays via masking technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
27	Garth A. Gibson, Lisa Hellerstein, Richard M. Karp, Randy H. Katz, David A. Patterson 0001	Failure Correction Techniques for Large Disk Arrays.	ASPLOS	1989	DBLP DOI BibTeX RDF