Search results for "CMP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
37	Xuemei Zhao, Karl Sammut, Fangpo He, Shaowen Qin	Split Private and Shared L2 Cache Architecture for Snooping-based CMP.	ACIS-ICIS	2007	DBLP DOI BibTeX RDF
37	Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato	A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures.	HPCA	2007	DBLP DOI BibTeX RDF
37	Xudong Shi 0003, Feiqi Su, Jih-Kwon Peir, Ye Xia 0001, Zhen Yang	Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility.	ISPASS	2007	DBLP DOI BibTeX RDF	multiple cache organization, single-pass simulation, on-chip storage space, on-chip cache capacity, single-pass stack simulation, global stack, shared stack, per-core private stack, single simulation pass, average memory access time, chip-multiprocessor, data replication, data accessibility, abstract model, reuse distances
37	Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang	Novel wire density driven full-chip routing for CMP variation control.	ICCAD	2007	DBLP DOI BibTeX RDF
37	Li Zhao 0002, Ravi R. Iyer 0001, Ramesh Illikkal, Donald Newell	Exploring DRAM cache architectures for CMP server platforms.	ICCD	2007	DBLP DOI BibTeX RDF
37	Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio, Pablo Prieto	Rotary router: an efficient architecture for CMP interconnection networks.	ISCA	2007	DBLP DOI BibTeX RDF	interconnection networks, router architecture, chip multi-processors
37	Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson	Parallel depth first vs. work stealing schedulers on CMP architectures.	SPAA	2006	DBLP DOI BibTeX RDF	scheduling, caches, chip multiprocessors
37	Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham	Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor.	MICRO	2005	DBLP DOI BibTeX RDF
36	Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee	UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error Reliability.	IEEE Trans. Parallel Distributed Syst.	2014	DBLP DOI BibTeX RDF
36	Yongbo Wu, Weiping Yang, Masakazu Fujimoto, Libo Zhou	Mirror Surface Finishing of Silicon Wafer Edge Using Ultrasonic Assisted Fixed-Abrasive CMP (UF-CMP).	Int. J. Autom. Technol.	2013	DBLP DOI BibTeX RDF
36	Randy Smith, Dan Gibson, Shijin Kong	To CMP or not to CMP: analyzing packet classification on modern and traditional parallel architectures.	ANCS	2007	DBLP DOI BibTeX RDF	chip multiprocessors, packet classification
36	Daniel Greenfield, Simon W. Moore	Fractal communication in software data dependency graphs.	SPAA	2008	DBLP DOI BibTeX RDF	CMP, communication complexity, fractal, NoC
36	Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin	Adaptive set pinning: managing shared caches in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	inter-processor, intra-processor, set pinning, CMP, shared cache
36	Jichuan Chang, Gurindar S. Sohi	Cooperative cache partitioning for chip multiprocessors.	ICS	2007	DBLP DOI BibTeX RDF	cooperative cache partitioning, multiple time-sharing partitions, QoS, fairness, CMP
36	Christopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim 0001, Sanjeev Kumar, Andrew Selle, Jatin Chhugani, Matthew J. Holliman, Yen-Kuang Chen	Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	parallelization, CMP, characterization, physical simulation
36	Dan Wallin, Henrik Löf, Erik Hagersten, Sverker Holmgren	Multigrid and Gauss-Seidel smoothers revisited: parallelization on chip multiprocessors.	ICS	2006	DBLP DOI BibTeX RDF	Gauss-Seidel, temporal blocking, CMP, OpenMP, relaxation, orderings, multigrid, Poisson equation, cache blocking
35	Takeshi Ogasawara, Ken Sakamura	How lock contention affects energy use in a CMP server.	OOPSLA Companion	2009	DBLP DOI BibTeX RDF	Java, energy efficiency, CMP, DVFS, lock contention
35	Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi	Architectural support for operating system-driven CMP cache management.	PACT	2006	DBLP DOI BibTeX RDF	quotas, QoS, cache, interface, fairness, CMP, SLAs, OS
35	Javier Lira, Carlos Molina, Antonio González 0001	The auction: optimizing banks usage in Non-Uniform Cache Architectures.	ICS	2010	DBLP DOI BibTeX RDF	bank replacement policy, non-uniform cache architecture (NUCA), chip multiprocessors (CMP)
35	Dan Gibson, David A. Wood 0001	Forwardflow: a scalable core for power-constrained CMPs.	ISCA	2010	DBLP DOI BibTeX RDF	scalable core, chip multiprocessor (cmp), power
35	Jinglei Wang, Dongsheng Wang 0002, Yibo Xue, Haixia Wang 0001	An Efficient Lightweight Shared Cache Design for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	Directory-based Cache Coherence Protocol, Lightweight Shared Cache, Chip Multiprocessors (CMP)
35	Valentina Salapura	Scaling up next generation supercomputers.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	scalability of systems, chip multiprocessors (cmp), multicore, coherence protocols, blue gene
35	Slo-Li Chu	Toward to Utilize the Heterogeneous Multiple Processors of the Chip Multiprocessor Architecture.	EUC	2007	DBLP DOI BibTeX RDF	Swing Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
34	Muhammad Mukaram Khan, Javier Navaridas, Alexander D. Rast, Xin Jin 0003, Luis A. Plana, Mikel Luján, John V. Woods, José Miguel-Alonso, Steve B. Furber	Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric.	ISPDC	2009	DBLP DOI BibTeX RDF	Multi-CMP Configuration, Neural Networks, Fault-tolerance, Embedded Systems, Chip Multiprocessor, Real-time Application, Massively Parallel Computing
34	Major Bhadauria, Vincent M. Weaver, Sally A. McKee	PARSEC: hardware profiling of emerging workloads for CMP design.	ICS	2009	DBLP DOI BibTeX RDF	cmp design profiling
28	Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	Understanding sources of inefficiency in general-purpose chips.	ISCA	2010	DBLP DOI BibTeX RDF	tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance
28	Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha	GARNET: A detailed on-chip network model inside a full-system simulator.	ISPASS	2009	DBLP DOI BibTeX RDF
28	Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	A memory system design framework: creating smart memories.	ISCA	2009	DBLP DOI BibTeX RDF	memory access protocol, protocol controller, transactional memory, reconfigurable architecture, cache coherence, memory systems, multi-core processors, stream programming
28	Enric Herrero, José González 0002, Ramon Canal	Distributed cooperative caching.	PACT	2008	DBLP DOI BibTeX RDF	distributed cooperative caching, energy efficiency, chip multiprocessors, memory hierarchy
28	Petko Bakalov, Vassilis J. Tsotras	A Generic Framework for Continuous Motion Pattern Query Evaluation.	ICDE	2008	DBLP DOI BibTeX RDF
28	Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, David M. Brooks	System level analysis of fast, per-core DVFS using on-chip switching regulators.	HPCA	2008	DBLP DOI BibTeX RDF
28	Sushu Zhang, Karam S. Chatha	Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
28	Hashem Hashemi Najaf-abadi, Eric Rotenberg	Configurational Workload Characterization.	ISPASS	2008	DBLP DOI BibTeX RDF
28	Laiquan Han, Jinkuan Wang, Cuirong Wang	A Crosslayer Concurrent Multipath Random Forward Algorithm.	ICYCS	2008	DBLP DOI BibTeX RDF
28	Carolina Bonacic, Carlos García 0001, Mauricio Marín, Manuel Prieto 0001, Francisco Tirado	Exploiting Hybrid Parallelism in Web Search Engines.	Euro-Par	2008	DBLP DOI BibTeX RDF
28	Cor Meenderinck, Ben H. H. Juurlink	(When) Will CMPs Hit the Power Wall?.	Euro-Par Workshops	2008	DBLP DOI BibTeX RDF
28	Padma Apparao, Ravi R. Iyer 0001, Donald Newell	Implications of cache asymmetry on server consolidation performance.	IISWC	2008	DBLP DOI BibTeX RDF
28	Hui Wang, Sandeep Baldawa, Rama Sangireddy	Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures.	VLSI Design	2008	DBLP DOI BibTeX RDF
28	Christopher LaFrieda, Engin Ipek, José F. Martínez, Rajit Manohar	Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor.	DSN	2007	DBLP DOI BibTeX RDF
28	Christof Pitter, Martin Schoeberl	Time Predictable CPU and DMA Shared Memory Access.	FPL	2007	DBLP DOI BibTeX RDF
28	Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose	Evaluating design tradeoffs in on-chip power management for CMPs.	ISLPED	2007	DBLP DOI BibTeX RDF	fetch throttling, dynamic voltage scaling, power-aware, chip multi-processor
28	Davy Genbrugge, Lieven Eeckhout	Statistical simulation of chip multiprocessors running multi-program workloads.	ICCD	2007	DBLP DOI BibTeX RDF
28	Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope	High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids.	AICCSA	2007	DBLP DOI BibTeX RDF
28	Michael R. Marty, Mark D. Hill	Virtual hierarchies to support server consolidation.	ISCA	2007	DBLP DOI BibTeX RDF	virtual machines, partitioning, chip multiprocessors (CMPs), multicore, memory hierarchies, cache coherence, server consolidation
28	Jingling Xue, Qiong Cai	A lifetime optimal algorithm for speculative PRE.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	classic PRE, speculative PRE, data-flow analysis, Partial redundancy elimination, lifetime optimality, computational optimality
28	Hou Rui, Longbing Zhang, Weiwu Hu	A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors.	Euro-Par	2006	DBLP DOI BibTeX RDF
28	Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihin	Helper thread prefetching for loosely-coupled multiprocessor systems.	IPDPS	2006	DBLP DOI BibTeX RDF
28	Pengyong Ma, Xiao Hu, Shuming Chen, Yang Guo	Pseudo Share Data Cache in Multiprocessor: PSDMP.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
28	Neil Vachharajani, Matthew Iyer, Chinmay Ashok, Manish Vachharajani, David I. August, Daniel A. Connors	Chip multi-processor scalability for single-threaded applications.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
28	Julia Chen, Philo Juang, Kevin Ko, Gilberto Contreras, David Penry, Ram Rangan, Adam Stoler, Li-Shiuan Peh, Margaret Martonosi	Hardware-modulated parallelism in chip multiprocessors.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
28	John D. Davis, Stephen E. Richardson, Charis Charitsis, Kunle Olukotun	A chip prototyping substrate: the flexible architecture for simulation and testing (FAST).	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
28	Hisashige Ando, Nestoras Tzartzanis, William W. Walker	A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
28	Annie P. Foong, Gary L. McAlpine, Dave B. Minturn, Greg J. Regnier, Vikram A. Saletore	An Architecture for Software-Based iSCSI on Multiprocessor Servers.	IPDPS	2005	DBLP DOI BibTeX RDF
28	Jose Renau, James Tuck 0001, Wei Liu 0014, Luis Ceze, Karin Strauss, Josep Torrellas	Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation.	ICS	2005	DBLP DOI BibTeX RDF
28	Wm. Benjamin Martz Jr., Venkateshwar K. Reddy	Looking for Indicators of Media Richness Theory in Distance Education.	HICSS	2005	DBLP DOI BibTeX RDF
28	Xin Wang, Charles C. Chiang, Jamil Kawa, Qing Su	A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing.	ISQED	2005	DBLP DOI BibTeX RDF
28	Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar	Optimizing Replication, Communication, and Capacity Allocation in CMPs.	ISCA	2005	DBLP DOI BibTeX RDF
28	Partha Kundu, Murali Annavaram, Trung A. Diep, John Paul Shen	A case for shared instruction cache on chip multiprocessors running OLTP.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF
28	Mohamed M. Zahran	On cache memory hierarchy for Chip-Multiprocessor.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF
28	Jan Kratochvíl, Martin Pergel	Two Results on Intersection Graphs of Polygons.	GD	2003	DBLP DOI BibTeX RDF
28	Chong-liang Ooi, Seon Wook Kim, Il Park 0001, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar	Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor.	ICS	2001	DBLP DOI BibTeX RDF
28	Kim Vejlby Hansen, Jan Larsen	An algorithm for successive identification of reflections.	IEEE Trans. Image Process.	1994	DBLP DOI BibTeX RDF
28	Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio	MRR: Enabling fully adaptive multicast routing for CMP interconnection networks.	HPCA	2009	DBLP DOI BibTeX RDF
28	Chunyang Feng, Hai Zhou 0001, Changhao Yan, Jun Tao 0001, Xuan Zeng 0001	Provably good and practically efficient algorithms for CMP dummy fill.	DAC	2009	DBLP DOI BibTeX RDF	covering linear programming, dummy fill problem, design for manufacturability
28	Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason A. Blome, Scott A. Mahlke	StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems.	CASES	2008	DBLP DOI BibTeX RDF	reliability, architecture, pipeline, multicore
28	Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, Todd C. Mowry	CMP Support for Large and Dependent Speculative Threads.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	databases, Multiprocessor Systems, cache coherence, thread-level speculation
28	Hailong Yao, Yici Cai, Xianlong Hong	CMP-aware Maze Routing Algorithm for Yield Enhancement.	ISVLSI	2007	DBLP DOI BibTeX RDF
28	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network.	HiPC	2007	DBLP DOI BibTeX RDF	Heterogeneus On-Chip Interconnection Network, Chip-Multiprocessor, Energy-Efficient Architectures, Parallel Scientific Applications
28	Lei Miao 0002, Yong Qi, Di Hou, Chang-li Wu, Yue-hua Dai	Dynamic Power Management and Dynamic Voltage Scaling in Real-time CMP Systems.	IEEE NAS	2007	DBLP DOI BibTeX RDF
28	Christof Simons	CMP: A UML Context Modeling Profile for Mobile Distributed Systems.	HICSS	2007	DBLP DOI BibTeX RDF
28	Roberto Giorgi, Zdravko Popovic, Nikola Puzovic	DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
28	Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh	Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP).	SBAC-PAD	2007	DBLP DOI BibTeX RDF
28	Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios N. Serpanos	Preventing Denial-of-Service Attacks in Shared CMP Caches.	SAMOS	2006	DBLP DOI BibTeX RDF
28	Bradford M. Beckmann, Michael R. Marty, David A. Wood 0001	ASR: Adaptive Selective Replication for CMP Caches.	MICRO	2006	DBLP DOI BibTeX RDF
28	Ali El-Moursy, Rajeev Garg, David H. Albonesi, Sandhya Dwarkadas	Compatible phase co-scheduling on a CMP of multi-threaded processors.	IPDPS	2006	DBLP DOI BibTeX RDF
28	Mario Donato Marino	32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
28	Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi	Computation spreading: employing hardware migration to specialize CMP cores on-the-fly.	ASPLOS	2006	DBLP DOI BibTeX RDF	dynamic specialization, cache locality
28	Fredrik Warg, Per Stenström	Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms.	IEEE PACT	2001	DBLP DOI BibTeX RDF
28	Yu Chen 0005, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky	Practical iterated fill synthesis for CMP uniformity.	DAC	2000	DBLP DOI BibTeX RDF
26	Major Bhadauria, Sally A. McKee	An approach to resource-aware co-scheduling for CMPs.	ICS	2010	DBLP DOI BibTeX RDF	scheduling, performance, energy efficiency, CMP
26	Jin Cui, Douglas L. Maskell	Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time system.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dynamic tas, post thermal map, cmp, soft real-time
26	M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt	Accelerating critical section execution with asymmetric multi-core architectures.	ASPLOS	2009	DBLP DOI BibTeX RDF	heterogeneous cores, parallel programming, cmp, multi-core, locks, critical sections
26	Feihui Li, Mahmut T. Kandemir, Mary Jane Irwin	Implementation and evaluation of a migration-based NUCA design for chip multiprocessors.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	NUCA, post office placement problem, CMP, data migration
26	M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Patt	Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs.	ASPLOS	2008	DBLP DOI BibTeX RDF	synchronization, CMP, bandwidth, multi-threaded
26	Bo Zhai, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester	Energy efficient near-threshold chip multi-processing.	ISLPED	2007	DBLP DOI BibTeX RDF	near-threshold, energy efficient, CMP, subthreshold
26	Martin Karlsson, Erik Hagersten, Kevin E. Moore, David A. Wood 0001	Exploring Processor Design Options for Java-Based Middleware.	ICPP	2005	DBLP DOI BibTeX RDF	Java, Middleware, CMP, workloads, ILP, Characterization
25	Shirish Tatikonda, Srinivasan Parthasarathy 0001	An adaptive memory conscious approach for mining frequent trees: implications for multi-core architectures.	PPoPP	2008	DBLP DOI BibTeX RDF	CMP architectures, frequent tree mining
25	Slo-Li Chu	Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture.	LCPC	2007	DBLP DOI BibTeX RDF	Critical Block Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
25	Noel Eisley, Vassos Soteriou, Li-Shiuan Peh	High-level power analysis for multi-core chips.	CASES	2006	DBLP DOI BibTeX RDF	simulation, chip multiprocessor (CMP), multi-core, power analysis, system-on-a-chip (SoC)
25	Mladen Nikitovic, Mats Brorsson	An adaptive chip-multiprocessor architecture for future mobile terminals.	CASES	2002	DBLP DOI BibTeX RDF	chip-multiprocessor (CMP), power consumption, mobile terminals, energy-aware scheduling
19	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan	Compiler directed network-on-chip reliability enhancement for chip multiprocessors.	LCTES	2010	DBLP DOI BibTeX RDF	reliability, compiler, noc, chip multiprocessors
19	Aparna Mandke Dani, Keshavan Varadarajan, Bharadwaj Amrutur, Y. N. Srikant	Accelerating multi-core simulators.	SAC	2010	DBLP DOI BibTeX RDF	chip multi-core, multi-core platform, timed petri-nets, instruction set simulator, cache simulator
19	Stamatis G. Kavadias, Manolis Katevenis, Michail Zampetakis, Dimitrios S. Nikolopoulos	On-chip communication and synchronization mechanisms with cache-integrated network interfaces.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	explicit communication, inter-processor synchronization, cache, network interface
19	Li Zhao 0002, Ravi R. Iyer 0001, Srihari Makineni, Don Newell, Liqun Cheng	NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cache, directory
19	Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke	Necromancer: enhancing system throughput by animating dead cores.	ISCA	2010	DBLP DOI BibTeX RDF	execution abstraction, heterogeneous core coupling, manufacturing defects
19	Daniel Sánchez 0003, Richard M. Yoo, Christos Kozyrakis	Flexible architectural support for fine-grain scheduling.	ASPLOS	2010	DBLP DOI BibTeX RDF	fine-grain scheduling, scheduling, chip-multiprocessors, messaging, many-core, work-stealing
19	Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz	Using a configurable processor generator for computer architecture prototyping.	MICRO	2009	DBLP DOI BibTeX RDF	computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design
19	Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha	In-network coherence filtering: snoopy coherence without broadcasts.	MICRO	2009	DBLP DOI BibTeX RDF
19	Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos	A tagless coherence directory.	MICRO	2009	DBLP DOI BibTeX RDF	directory coherence, cache coherence, Bloom filters
19	Gilles Pokam, Cristiano Pereira, Klaus Danne, Rolf Kassa, Ali-Reza Adl-Tabatabai	Architecting a chunk-based memory race recorder in modern CMPs.	MICRO	2009	DBLP DOI BibTeX RDF	memory race recorder, determinism, deterministic replay