Search results for "Cache"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
54	Xavier Vera, Björn Lisper, Jingling Xue	Data Caches in Multitasking Hard Real-Time Systems.	RTSS	2003	DBLP DOI BibTeX RDF
54	Scott McFarling	Program Optimization for Instruction Caches.	ASPLOS	1989	DBLP DOI BibTeX RDF	RISC
54	Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer	Adaptive insertion policies for managing shared caches.	PACT	2008	DBLP DOI BibTeX RDF	set dueling, shared cache, replacement, cache partitioning
54	Jun Wang 0001, Xiaoyu Yao, Christopher Mitchell, Peng Gu	A New Hierarchical Data Cache Architecture for iSCSI Storage Server.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
54	Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Exact and fast L1 cache simulation for embedded systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
54	Xiaoyu Yao, Jun Wang 0001	Toward Effective NIC Caching: A Hierarchical Data Cache Architecture for iSCSI Storage Servers.	ICPP	2005	DBLP DOI BibTeX RDF
54	Evan Speight, Hazim Shafi, Lixin Zhang 0002, Ramakrishnan Rajamony	Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors.	ISCA	2005	DBLP DOI BibTeX RDF
54	Xiaomei Ji, Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta 0001	Compiler-Directed Cache Assist Adaptivity.	ISHPC	2000	DBLP DOI BibTeX RDF
54	Jih-Kwon Peir, Yongjoon Lee, Windsor W. Hsu	Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology.	ASPLOS	1998	DBLP DOI BibTeX RDF
54	Soontae Kim, Jongmin Lee 0002	Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low power, data cache, write buffer
54	Guy E. Blelloch, Phillip B. Gibbons, Harsha Vardhan Simhadri	Low depth cache-oblivious algorithms.	SPAA	2010	DBLP DOI BibTeX RDF	sparse-matrix vector multiply, schedulers, parallel algorithms, multiprocessors, sorting, graph algorithms, cache-oblivious algorithms
54	Chuanjun Zhang	Reducing cache misses through programmable decoders.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	low power, Cache, dynamic optimization
54	Yudong Tan, Vincent John Mooney III	WCRT analysis for a uniprocessor with a unified prioritized cache.	LCTES	2005	DBLP DOI BibTeX RDF	real-time system, timing analysis, cache design
54	Rui Min, Yiming Hu	Improving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addresses.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Novel memory architectures, cache, memory systems, TLB, performance enhancement
54	Kian-Lee Tan, Jun Cai, Beng Chin Ooi	An Evaluation of Cache Invalidation Strategies in Wireless Environments.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	doze mode, bit-sequences, Mobile computing, energy consumption, access time, disconnection, cache invalidation
54	Roberto Giorgi, Paolo Bennati	Filtering drowsy instruction cache to achieve better efficiency.	SAC	2008	DBLP DOI BibTeX RDF	low-power, leakage, drowsy cache, filter cache
54	Yu Huang 0002, Beihong Jin, Jiannong Cao 0001, Guangzhong Sun, Yulin Feng	A Selective Push Algorithm for Cooperative Cache Consistency Maintenance over MANETs.	EUC	2007	DBLP DOI BibTeX RDF	Cache Status Maintenance, Selective Push, Mobile Ad hoc Networks, Stateful, Cooperative Caching, Cache Consistency
54	Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Analyzing data reuse for cache reconfiguration.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	cache polymorphism, compilers, energy consumption, Embedded software, data reuse, cache locality
54	Jaehyuk Huh 0001, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA substrate for flexible CMP cache sharing.	ICS	2005	DBLP DOI BibTeX RDF	cache sharing, non-uniform cache architecture, chip-multiprocessor
54	Josef Weidendorfer, Carsten Trinitis	Collecting and Exploiting Cache-Reuse Metrics.	International Conference on Computational Science (2)	2005	DBLP DOI BibTeX RDF	Cache Reuse Metrics, Profiling, Cache Simulation
54	Zhijun Wang 0001, Sajal K. Das 0001, Hao Che, Mohan Kumar	A Scalable Asynchronous Cache Consistency Scheme (SACCS) for Mobile Environments.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	stale cache hit, Mobile environments, cache consistency, disconnection, bandwidth utilization
54	Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hendra Saputra, Wei Zhang 0002	Compiler-directed cache polymorphism.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	cache polymorphism, compilers, energy consumption, embedded software, data reuse, cache locality
54	Moinuddin K. Qureshi, M. Aater Suleman, Yale N. Patt	Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines.	HPCA	2007	DBLP DOI BibTeX RDF
54	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai	Value-Conscious Cache: Simple Technique for Reducing Cache Access Power.	DATE	2004	DBLP DOI BibTeX RDF
54	Gi-Ho Park, Kil-Whan Lee, Jae-Hyuk Lee, Tack-Don Han, Shin-Dug Kim	A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure.	LCTES	2000	DBLP DOI BibTeX RDF
54	Chi-Hung Chi, Henry G. Dietz	Unified Management of Registers and Cache Using Liveness and Cache Bypass.	PLDI	1989	DBLP DOI BibTeX RDF
54	Rong Xu, Zhiyuan Li 0001	A sample-based cache mapping scheme.	LCTES	2005	DBLP DOI BibTeX RDF	cache bypass, cache mapping, mini cache, trace sampling, profiling, handheld devices
54	Shigeki Shibayama, Kazumasa Hamaguchi, Toshiyuki Fukui, Yoshiaki Sudo, Tomohiko Shimoyama, Shuichi Nakamura	An Optical Bus Computer Cluster with a deferred cache coherence protocol.	ICPADS	1996	DBLP DOI BibTeX RDF	Optical Bus Computer Cluster, deferred cache coherence protocol, optical star-coupler, one-hop simultaneous broadcasting, wavelength multiplexing, deferred cache coherence, coherence maintenance, protocols, wavelength-division multiplexing, optical interconnections, cache storage
54	Soong Hyun Shin, Cheol Hong Kim, Chu Shik Jhon	An Effective Instruction Cache Prefetch Policy by Exploiting Cache History Information.	EUC	2005	DBLP DOI BibTeX RDF	Computer architecture, embedded processor, instruction cache, cache prefetching
50	Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic	HitME: low power Hit MEmory buffer for embedded systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
50	Ben H. H. Juurlink	Unified Dual Data Caches.	DSD	2003	DBLP DOI BibTeX RDF
50	Jen-Chu Liu, Wen-Tsuen Chen	An Efficient Wireless Internet Access Scheme.	ICOIN	2003	DBLP DOI BibTeX RDF
50	Brannon Batson, T. N. Vijaykumar	Reactive-Associative Caches.	IEEE PACT	2001	DBLP DOI BibTeX RDF
50	Guanghui Liu	ECC-Cache: A Novel Low Power Scheme to Protect Large-Capacity L2 Caches from Transiant Faults.	IAS	2009	DBLP DOI BibTeX RDF
50	Chun-Chieh Lin, Chuen-Liang Chen	Object Placement for Fully Associative Cache.	EUC (2)	2008	DBLP DOI BibTeX RDF
50	Cheol Hong Kim, Sung-Hoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon	First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption.	SAMOS	2005	DBLP DOI BibTeX RDF
50	Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin	Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture.	HPCA	2005	DBLP DOI BibTeX RDF
50	José R. Brunheroto, Valentina Salapura, Fernando F. Redígolo, Dirk Hoenicke, Alan Gara	Data cache prefetching design space exploration for BlueGene/L supercomputer.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
50	Seongbeom Kim, Dhruba Chandra, Yan Solihin	Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture.	IEEE PACT	2004	DBLP DOI BibTeX RDF
50	Ying Zheng, Brian T. Davis, Matthew Jordan	Performance evaluation of exclusive cache hierarchies.	ISPASS	2004	DBLP DOI BibTeX RDF
50	Alaa R. Alameldeen, David A. Wood 0001	Adaptive Cache Compression for High-Performance Processors.	ISCA	2004	DBLP DOI BibTeX RDF
50	Changkyu Kim, Doug Burger, Stephen W. Keckler	An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches.	ASPLOS	2002	DBLP DOI BibTeX RDF
50	Bryan Black, Bohuslav Rychlik, John Paul Shen	The Block-Based Trace Cache.	ISCA	1999	DBLP DOI BibTeX RDF
50	Amir H. Hashemi, David R. Kaeli, Brad Calder	Efficient Procedure Mapping Using Cache Line Coloring.	PLDI	1997	DBLP DOI BibTeX RDF
50	Sung-Eui Yoon, Peter Lindstrom 0001	Mesh Layouts for Block-Based Caches.	IEEE Trans. Vis. Comput. Graph.	2006	DBLP DOI BibTeX RDF	Mesh and graph layouts, cache-aware and cache-oblivious layouts, metrics for cache coherence, data locality
50	W. Lynn Gallagher, Chuan-lin Wu	Evaluation of a memory hierarchy for the MTS multithreaded processor.	ICPADS	1997	DBLP DOI BibTeX RDF	memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
50	Igor Tatarinov, Alex Rousskov, Valery Soloviev	Static caching in Web servers.	ICCCN	1997	DBLP DOI BibTeX RDF	implementation complexity an, static caching, cache policies, LRU-threshold, LFU, LRU-SIZE, LRU-MIN, LRU-k-threshold, Pitkow/Recker policy, Web document access patterns, request log file, small cache sizes, primary Web servers, CPU overhead, performance analysis, cache performance, log files, online front-ends
50	André Seznec, François Bodin	Skewed-associative Caches.	PARLE	1993	DBLP DOI BibTeX RDF	skewed-associative cache, cache, microprocessors, set-associative cache
50	Alexander Heinecke, Carsten Trinitis, Josef Weidendorfer	Porting existing cache-oblivious linear algebra HPC modules to larrabee architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	accelerator space-filling curve, openmp, matrix multiplication, cache-oblivious, lu decomposition, manycore
50	Anca Mariana Molnos, Sorin Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven	Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Predictability, Multiprocessor, Compositionality, Cache management
50	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	Dynamic cache clustering for chip multiprocessors.	ICS	2009	DBLP DOI BibTeX RDF	non-uniform cache architecture (nuca), chip multiprocessor (cmp)
50	Kapil Anand, Rajeev Barua	Instruction cache locking inside a binary rewriter.	CASES	2009	DBLP DOI BibTeX RDF	cache locking, embedded systems, caches, binary rewriting
50	Yutao Zhong 0001, Steven G. Dropsho, Xipeng Shen, Ahren Studer, Chen Ding 0001	Miss Rate Prediction Across Program Inputs and Cache Configurations.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	optimization, compilers, Cache memories, modeling techniques, performance analysis and design aids
50	Lakshmish Ramaswamy, Ling Liu 0001, Arun Iyengar	Scalable Delivery of Dynamic Content Using a Cooperative Edge Cache Grid.	IEEE Trans. Knowl. Data Eng.	2007	DBLP DOI BibTeX RDF	edge computing, cache clouds, cooperative caching, Dynamic content caching
50	Norbert Esser, Renga Sundararajan, Joachim Trescher	Improving TriMedia Cache Performance by Profile Guided Code Reordering.	SAMOS	2007	DBLP DOI BibTeX RDF	cache, profiling, code layout
50	Heiko Falk, Sascha Plazar, Henrik Theiling	Compile-time decided instruction cache locking using worst-case execution paths.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	WC-path, cache locking, optimization, WCET
50	Jichuan Chang, Gurindar S. Sohi	Cooperative cache partitioning for chip multiprocessors.	ICS	2007	DBLP DOI BibTeX RDF	cooperative cache partitioning, multiple time-sharing partitions, QoS, fairness, CMP
50	Tony Givargis	Zero cost indexing for improved processor cache performance.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	index hashing, Cache optimization, design exploration
50	Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu	Design, implementation, and verification of active cache emulator (ACE).	FPGA	2006	DBLP DOI BibTeX RDF	FPGA-based emulator, real-time emulation, cache modeling
50	Fei Guo, Yan Solihin	An analytical model for cache replacement policy performance.	SIGMETRICS/Performance	2006	DBLP DOI BibTeX RDF	analytical model, cache performance, replacement policy
50	Le Cai, Yung-Hsiang Lu	Power reduction of multiple disks using dynamic cache resizing and speed control.	ISLPED	2006	DBLP DOI BibTeX RDF	disk rotation speed, power management, disk cache
50	Tohru Ishihara, Farzan Fallah	A non-uniform cache architecture for low power system design.	ISLPED	2005	DBLP DOI BibTeX RDF	embedded systems, compiler, microprocessor, cache memory
50	Ming Zhang 0026, Qing Yang 0001	BUCS - A Bottom-Up Cache Structure for Networked Storage Servers.	ICPP	2004	DBLP DOI BibTeX RDF	cache structure, intelligent controller, networked storage, bus contention
50	Jung-Hoon Lee, Seh-Woong Jeong, Shin-Dug Kim, Charles C. Weems	An Intelligent Cache System with Hardware Prefetching for High Performance.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	dual data cache, prefetching, Memory hierarchy, temporal locality, spatial locality
50	Jeffrey B. Rothman, Alan Jay Smith	Sector Cache Design and Performance.	MASCOTS	2000	DBLP DOI BibTeX RDF	sector cache, simulation, architecture, workloads, multiprogramming
50	David K. Tam, Reza Azimi, Livio Soares, Michael Stumm	RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations.	ASPLOS	2009	DBLP DOI BibTeX RDF	miss rate curve, performance monitoring unit, shared cache management, chip multiprocessor, dynamic optimization, multicore processor, shared cache, cache management, cache partitioning, hardware performance counters, online optimization
50	Yefim Shuf, Ian M. Steiner	Characterizing a Complex J2EE Workload: A Comprehensive Analysis and Opportunities for Optimizations.	ISPASS	2007	DBLP DOI BibTeX RDF	J2EE workload, Java benchmarks, SPECjvm98, SPECjbb2000, Java 2 Enterprise Edition, SPECjAppServer2004, systems research, software research, cache-to-cache modified data transfers, intelligent thread co-scheduling, Java heap, bursty data cache, Java virtual method calls, optimizations, performance analysis, garbage collection, instruction cache, data prefetching, commercial workload
50	Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran	SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.	DAC	2010	DBLP DOI BibTeX RDF	miss rate, simulation, round robin, cache simulation, L1 cache
50	Chenjie Yu, Xiangrong Zhou, Peter Petrov	Low-power inter-core communication through cache partitioning in embedded multiprocessors.	SBCCI	2009	DBLP DOI BibTeX RDF	low-power cache architectures, low-power cache coherence, MPSoC, on-chip communication
50	Jinglei Wang, Dongsheng Wang 0002, Yibo Xue, Haixia Wang 0001	An Efficient Lightweight Shared Cache Design for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	Directory-based Cache Coherence Protocol, Lightweight Shared Cache, Chip Multiprocessors (CMP)
50	Bingsheng He, Qiong Luo 0001	Cache-oblivious databases: Limitations and opportunities.	ACM Trans. Database Syst.	2008	DBLP DOI BibTeX RDF	cache-conscious, chip multiprocessors, data caches, simultaneous multithreading, Cache-oblivious
50	Stavros Harizopoulos, Anastassia Ailamaki	Improving instruction cache performance in OLTP.	ACM Trans. Database Syst.	2006	DBLP DOI BibTeX RDF	Instruction cache, cache misses
50	Alberto Ros 0001, Manuel E. Acacio, José M. García 0001	An efficient cache design for scalable glueless shared-memory multiprocessors.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	L2, directory structure, glueless shared-memory multiprocessors, cache, cache coherence, memory wall
50	Gerth Stølting Brodal, Rolf Fagerberg	On the limits of cache-obliviousness.	STOC	2003	DBLP DOI BibTeX RDF	Cache-oblivious model, tall cache assumption, lower bound, sorting, permuting
50	Daranee Hormdee, Jim D. Garside, Stephen B. Furber	An Asynchronous Victim Cache.	DSD	2002	DBLP DOI BibTeX RDF	copy-back cache architecture, asynchronous design, victim cache
50	Erez Petrank, Dror Rawitz	The hardness of cache conscious data placement.	POPL	2002	DBLP DOI BibTeX RDF	Cache conscious data placement, cache conscious code rearrangement, computational complexity, memory management, hardness of approximation
50	Tsang-Ling Sheu, Chieh-Hsing Yang	A Novel Hierarchical Cache Architecture for WWW Servers.	ICOIN	2001	DBLP DOI BibTeX RDF	Cache Digest, WWW, Proxy Servers, ICP, Hierarchical Cache
50	Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau	Augmenting Loop Tiling with Data Alignment for Improved Cache Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	data cache, Loop tiling, data alignment, cache conflict
50	Zhiwen Xu, Xiaoxin Guo, Xiangjiu Che, Zhengxuan Wang, Yunjie Pang	The Batch Patching Method Using Dynamic Cache of Proxy Cache for Streaming Media.	GCC	2005	DBLP DOI BibTeX RDF
50	Manuel E. Acacio, José González 0002, José M. García 0001, José Duato	Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture.	SC	2002	DBLP DOI BibTeX RDF
50	Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi	Cache decay: exploiting generational behavior to reduce cache leakage power.	ISCA	2001	DBLP DOI BibTeX RDF
50	Richard E. Ladner, Ray Fortna, Bao-Hoang Nguyen	A Comparison of Cache Aware and Cache Oblivious Static Search Trees Using Program Instrumentation.	Experimental Algorithmics	2000	DBLP DOI BibTeX RDF
50	Hui Li, Kenneth C. Sevcik	Exploiting cache affinity in software cache coherence.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF
50	Rezaul Alam Chowdhury, Vijaya Ramachandran	Cache-efficient dynamic programming algorithms for multicores.	SPAA	2008	DBLP DOI BibTeX RDF	parallelism, multicore, shared cache, distributed cache, cache-efficiency
50	Jaume Abella 0001, Antonio González 0001, Xavier Vera, Michael F. P. O'Boyle	IATAC: a smart predictor to turn-off L2 cache lines.	ACM Trans. Archit. Code Optim.	2005	DBLP DOI BibTeX RDF	turning off cache lines, low power, Cache memories, L2 cache
50	Jamison D. Collins, Dean M. Tullsen	Runtime identification of cache conflict misses: The adaptive miss buffer.	ACM Trans. Comput. Syst.	2001	DBLP DOI BibTeX RDF	adaptive miss buffer, cache exclusion, prefetching, victim cache, Cache architecture, conflict misses
50	Qing Yang 0001, George Thangadurai, Laxmi N. Bhuyan	Design of an Adaptive Cache Coherence Protocol for Large Scale Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	adaptive cache coherence protocol, cache-based multiprocessor, cache coherence scheme, memoryarchitecture, protocols, multiprocessor interconnection networks, multistage interconnection network, buffer storage, hierarchical network
50	Cheol Hong Kim, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon	Adaptive Block Management for Victim Cache by Exploiting L1 Cache History Information.	EUC	2004	DBLP DOI BibTeX RDF	Block Management, Low Power, Computer Architecture, Victim Cache
50	Kamen Yotov, Thomas Roeder, Keshav Pingali, John A. Gunnels, Fred G. Gustavson	An experimental comparison of cache-oblivious and cache-conscious programs.	SPAA	2007	DBLP DOI BibTeX RDF	cache-conscious algorithms, memory hierarchy, memory bandwidth, memory latency, numerical software, cache-oblivious algorithms
46	Kun-Lung Wu, Philip S. Yu	Local Replication for Proxy Web Caches with Hash Routing.	CIKM	1999	DBLP DOI BibTeX RDF
46	Maged M. Michael, Ashwini K. Nanda	Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors.	HPCA	1999	DBLP DOI BibTeX RDF
46	Sanjeev Kumar, Christopher B. Wilkerson	Exploiting Spatial Locality in Data Caches Using Spatial Footprints.	ISCA	1998	DBLP DOI BibTeX RDF
46	Mainak Chaudhuri	Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.	MICRO	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, replacement policy, last-level cache
46	Nasir Mohyuddin, Rashed Zafar Bhatti, Michel Dubois 0001	Controlling leakage power with the replacement policy in slumberous caches.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	tranquility level, leakage power, replacement policy, drowsy cache
46	Johnson Kin, Munish Gupta, William H. Mangione-Smith	Filtering Memory References to Increase Energy Efficiency.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	energy-delay, low power, embedded processor, media processor, Filter cache
46	Shimin Chen, Anastassia Ailamaki, Phillip B. Gibbons, Todd C. Mowry	Improving hash join performance through prefetching.	ACM Trans. Database Syst.	2007	DBLP DOI BibTeX RDF	CPU cache performance, CPU cache prefetching, group prefetching, software-pipelined prefetching, Hash join
46	Naveen Muralimanohar, Rajeev Balasubramonian	Interconnect design considerations for large NUCA caches.	ISCA	2007	DBLP DOI BibTeX RDF	non-uniform cache architecture, network-on-chip, interconnect, memory hierarchies, cache models
46	Stefanos Kaxiras, Polychronis Xekalakis, Georgios Keramidas	A simple mechanism to adapt leakage-control policies to temperature.	ISLPED	2005	DBLP DOI BibTeX RDF	hybrid leakage mechanism, thermal adaptation, drowsy cache, cache decay
46	Paul Berube, Ashley Zinyk, José Nelson Amaral, Mike H. MacGregor	The Bank Nth Chance Replacement Policy for FPGA-Based CAMs.	FPL	2003	DBLP DOI BibTeX RDF	multizone cache, field programmable gate array, cache memories, memory systems, content addressable memories, replacement policy, digital design, Internet routing
46	S. Subha	A two-type data cache model.	EIT	2009	DBLP DOI BibTeX RDF