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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 4769 publication records. Showing 4757 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
30 | Morteza Dorrigiv, Ghassem Jaberipur |
Low area/power decimal addition with carry-select correction and carry-select sum-digits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 47(4), pp. 443-451, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Praveena Murugesan, Thanushkodi Keppanagounder |
Design of Optimal Carry Skip Adder and Carry Skip BCD Adder using Reversible Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. ![In: J. Comput. Sci. 10(5), pp. 723-728, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | P. Balasubramanian 0001, David A. Edwards, William B. Toms |
Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 22(4), 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Lalitha Mohana Kalyani-Garimella, Sri Raga Sudha Garimella, Kevin Duda, Eric S. Fetzer |
New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 1387-1390, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Habib Ghasemizadeh Tamar, Akbar Ghasemizadeh Tamar, Khayrollah Hadidi, Abdollah Khoei, Pourya Hoseini |
High speed area reduced 64-bit static hybrid carry-lookahead/carry-select adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, pp. 460-463, 2011, IEEE, 978-1-4577-1845-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
30 | Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz |
Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1008.3344, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
30 | Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz |
Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1008.3311, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
30 | Yajuan He, Chip-Hong Chang |
A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(1), pp. 336-346, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy 0001 |
Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 90-C(4), pp. 865-876, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Gustavo A. Ruiz, Mercedes Granda |
An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 35(12), pp. 939-944, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija |
Delay optimization of carry-skip adders and block carry-lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 10th IEEE Symposium on Computer Arithmetic, ARITH 1991, Grenoble, France, June 26-28, 1991, pp. 154-164, 1991, IEEE, 0-8186-9151-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
29 | Toshimitsu Fujii, Mitsuru Kaji, Yuya Sasaki 0001, Takahiro Hara, Shojiro Nishio |
A Flooding Control Method with Ack-carry for Location-Based Information Dissemination in Mobile Ad Hoc Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAINT ![In: 11th Annual International Symposium on Applications and the Internet, SAINT 2011, Munich, Germany, 18-21 July, 2011, Proceedings, pp. 128-135, 2011, IEEE Computer Society, 978-1-4577-0531-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
flooding control, ack-carry, mobile ad hoc networks, Time To Live (TTL) |
29 | Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Arun Bhanu |
Modeling of Probabilistic Ripple-Carry Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 201-206, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
ripple-carry adder, noies modeling, error propagation, Probabilistic computation |
29 | Verus Pronk, Jan H. M. Korst |
Comments on "carry-over round robin: a simple cell scheduling mechanism for ATM network". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 9(3), pp. 373, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
carry-over round robin, ATM, delay, fairness |
29 | Stanislaw J. Piestrak |
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(1), pp. 68-77, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
residue generators, multioperand modular adders, arithmetic error detecting codes, binary-to-residue number system, residue generator, digital arithmetic, adders, Chinese remainder theorem, residue number system, arithmetic codes, residue arithmetic, carry-save adders |
29 | Vitit Kantabutra |
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(11), pp. 1389-1393, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
accelerated two-level carry-skip adders, bit positions, bimodal, CMOS VLSI, 12.6 sec, VLSI, delays, adders, CMOS integrated circuits, unimodal, 2 micron |
29 | Vitit Kantabutra |
Designing Optimum One-Level Carry-Skip Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(6), pp. 759-764, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
one-level, 64 bit, 6.23 ns, logic design, digital simulation, adders, SPICE simulation, carry-skip adders, 1 micron |
29 | Jordi Cortadella, José M. Llabería |
Evaluation of A + B = K Conditions Without Carry Propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(11), pp. 1484-1488, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
parallel adders, carry propagation delay, performance, digital arithmetic, response time, adders |
29 | Milos D. Ercegovac, Tomás Lang |
Fast Multiplication Without Carry-Propagate Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(11), pp. 1385-1390, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
fast multiplication, carry-propagate adder, LRCF scheme, general radix r, radix-4 signed-digit implementation, digital arithmetic |
29 | Alain Guyot, Bertrand Hochet, Jean-Michel Muller |
A Way to Build Efficient Carry-Skip Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 36(10), pp. 1144-1152, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
VLSI design, Carry-skip adders |
29 | Tom Rhyne |
Limitations on Carry Lookahead Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(4), pp. 373-374, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
high-speed arithmetic, Binary addition, carry lookahead |
29 | Hung Chi Lai, Saburo Muroga |
Logic Networks of Carry-Save Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(9), pp. 870-882, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders |
29 | John J. Shedletsky |
Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(3), pp. 271-272, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
End-around-carry (EAC) adder, negative zero, one's complement arithmetic |
29 | Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen |
Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 142-145, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Michael T. Frederick, Arun K. Somani |
Non-arithmetic carry chains for reconfigurable fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 137-143, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Himanshu Thapliyal, Sumedha K. Gupta |
Design of Novel Reversible Carry Look-Ahead BCD Subtractor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIT ![In: 9th International Conference in Information Technology, ICIT 2006, Bhubaneswar, Orissa, India, 18-21 December 2006, pp. 253-258, 2006, IEEE Computer Society, 0-7695-2635-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Dilip P. Vasudevan, Parag K. Lala |
A Technique for Modular Design of Self-Checking Carry-Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 325-333, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Michael Nicolaidis |
Carry checking/parity prediction adders and ALUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(1), pp. 121-128, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr. |
Optimal joint module-selection and retiming with carry-save representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7), pp. 836-846, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Mark A. Erle, Michael J. Schulte |
Decimal Multiplication Via Carry-Save Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 348-, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Youngjoon Kim, Ki-Hyuk Sung, Lee-Sup Kim |
A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 461-464, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan |
Partially Duplicated Code-Disjoint Carry-Skip Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 78-86, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Javier D. Bruguera, Tomás Lang |
Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 203-210, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Javier D. Bruguera, Tomás Lang |
Multilevel Reverse-Carry Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 155-162, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr. |
Bit-level arithmetic optimization for carry-save additions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 14-19, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Paolo Montuschi, Luigi Ciminiera |
n × n carry-save multipliers without final addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings., pp. 54-61, 1993, IEEE Computer Society/, 0-8186-3862-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
29 | Naofumi Takagi |
Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, pp. 224-237, 2002, IEEE Computer Society, 0-7695-1462-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
carry-save form, carry-propagation-free addition, multiplier recoding, computer arithmetic, signed-digit number representation, digit-recurrence algorithm |
29 | Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan |
A New Divide and Conquer Method for Achieving High Speed Division in Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 535-540, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Carry Propagate Adders, Pipelineability, Throughput, Latency, Rounding, Carry Save Adders, Radix, SRT |
29 | Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi 0001 |
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(1), pp. 34-42, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
multiple-valued current-mode circuits, high-speed multiplier, carry-propagation-free addition trees, multiple-valued current-mode, carry-propagation-free addition, area efficient design, VLSI, VLSI, tree structure, multiplying circuits, redundant number representations, number representations, multiplier design |
29 | Milos D. Ercegovac, Tomás Lang, Paolo Montuschi |
Very-High Radix Division with Prescaling and Selection by Rounding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(8), pp. 909-918, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
very-high radix division, quotient-digit selection, carry-save, computer arithmetic, digital arithmetic, selection, rounding, redundant representation, prescaling, carry logic, division algorithm |
29 | Stamatis Vassiliadis, James Phillips, Bart Blaner |
Interlock Collapsing ALU's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(7), pp. 825-839, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement |
29 | Daniel E. Atkins, Shauchi Ong |
Time-Component Complexity of Two Approaches to Multioperand Binary Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(12), pp. 918-926, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
time-component complexity, Adder tree, multioperand addition, carry-save adder, carry-lookahead adder, binary addition |
29 | Dharma P. Agrawal |
High-Speed Arithmetic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(3), pp. 215-224, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
carry-look-ahead, carry-save, pipelining, multiplication, division, Arrays, square-root, square, high-speed arithmetic, sign detection, multifunction |
29 | Dharma P. Agrawal |
Arithmetic Algorithms in a Negative Base. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(10), pp. 998-1000, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
basic arithmetic operations, interim carry, multiple operand addition, negative base, twin carry, Algorithms, polarization |
28 | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
A novel FPGA logic block for improved arithmetic performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 171-180, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
6.2 compressor, carry-chain, compressor tree, multi-operand addition, FPGA, arithmetic circuits |
28 | M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas |
New and Improved Architectures for Montgomery Modular Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mob. Networks Appl. ![In: Mob. Networks Appl. 12(4), pp. 281-291, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reconfigurable multiplier, scalable multiplier, RSA, ECC, carry save adders, Montgomery modular multiplication |
28 | Viktor Bunimov, Manfred Schimmler |
Area and Time Efficient Modular Multiplication of Large Integers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 400-, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Montgomery algorithm, interleaved modular multiplication, MSB-first arithmetic, redundant number arithmetic, Modular multiplication, carry save addition |
28 | Radhika S. Grover, Weijia Shang, Qiang Li |
A faster distributed arithmetic architecture for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 31-39, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
DALUT, XC4000, carry propagation, cost-performance analysis, distributed arithmetic |
28 | Çetin Kaya Koç, Ching Yu Hung |
Bit-level systolic arrays for modular multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 3(3), pp. 215-223, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
sign estimation, scheduling, systolic array, modular multiplication, carry save adders |
28 | Jean-Luc Beuchat, Jean-Michel Muller |
Automatic Generation of Modular Multipliers for FPGA Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(12), pp. 1600-1613, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait |
Area-time optimal adder with relative placement generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 141-144, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Andrew Beaumont-Smith, Cheng-Chew Lim |
Parallel Prefix Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 218-, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Gang Zhou, Li Li 0027, Harald Michalik |
Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 671-674, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Michael Kirkedal Thomsen, Holger Bock Axelsen |
Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UC ![In: Unconventional Computing, 7th International Conference, UC 2008, Vienna, Austria, August 25-28, 2008. Proceedings, pp. 228-241, 2008, Springer, 978-3-540-85193-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
quantum computing, adders, circuits, Reversible computing |
24 | Wenjing Rao, Alex Orailoglu, Ramesh Karri |
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 63-68, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu |
Carry Estimation for Two's Complement Fixed-Width Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 345-350, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Erkay Savas |
A Carry-Free Architecture for Montgomery Inversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(12), pp. 1508-1519, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Montgomery inversion, redundant signed representation, elliptic curve cryptography |
24 | Himanshu Thapliyal, M. B. Srinivas |
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 805-817, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Kenny Johansson, Oscar Gustafsson, Lars Wanhammar |
Power Estimation for Ripple-Carry Adders with Correlated Input Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 662-674, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Varun Jindal, Alpana Agarwal |
Carry Circuitry for LUT-Based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 731-734, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Andrea Lodi 0002, Carlo Chiesa, Fabio Campi, Mario Toma |
A flexible LUT-based carry chain for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 133-136, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour |
A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 84-87, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Viv A. Bartlett, Andrew G. Dempster |
Using carry-save adders in low-power multiplier blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 222-225, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Henrik Eriksson, Per Larsson-Edefors, William P. Marnane |
A regular parallel multiplier which utilizes multiple carry-propagate adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 166-169, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan |
Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy, pp. 147-152, 2001, IEEE Computer Society, 0-7695-1290-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Junhyung Um, Taewhan Kim, C. L. Liu 0001 |
Optimal allocation of carry-save-adders in arithmetic optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 410-413, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Gianluca Cena, Paolo Montuschi, Luigi Ciminiera, Andrea Sanna |
A Q-Coder Algorithm with Carry Free Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 282-, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
image compression, arithmetic coding |
24 | Janusz Rajski, Jerzy Tyszer |
Test responses compaction in accumulators with rotate carry adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4), pp. 531-539, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
24 | Michael T. Frederick, Arun K. Somani |
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 37-46, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
carry chain, depth optimal mapping, logic chain |
24 | Levent Aksoy, Ece Olcay Günes |
Area optimization algorithms in high-speed digital FIR filter synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 64-69, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
high-speed filter design, multiple constant multiplications, subexpression sharing, area optimization, carry-save adders |
24 | Mark Goresky, Andrew Klapper |
Periodicity and Distribution Properties of Combined FCSR Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SETA ![In: Sequences and Their Applications - SETA 2006, 4th International Conference, Beijing, China, September 24-28, 2006, Proceedings, pp. 334-341, 2006, Springer, 3-540-44523-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
stream cipher, pseudorandom sequence, Feedback with carry shift register |
24 | Giorgos Dimitrakopoulos, Dimitris Nikolos |
High-Speed Parallel-Prefix VLSI Ling Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(2), pp. 225-231, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
parallel-prefix carry computation, computer arithmetic, VLSI design, Adders |
24 | Jeremy R. Johnson, Werner Krandick, Anatole D. Ruslanov |
Architecture-aware classical Taylor shift by 1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSAC ![In: Symbolic and Algebraic Computation, International Symposium ISSAC 2005, Beijing, China, July 24-27, 2005, Proceedings, pp. 200-207, 2005, ACM, 1-59593-095-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ILP scheduling, Taylor shift, delayed carry propagation, multiprecision arithmetic, register tiling, high-performance computing, code generation, memory hierarchy, polynomials, performance tuning, loop unrolling |
24 | Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos |
Diminished-One Modulo 2n+1 Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(12), pp. 1389-1399, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Modulo $big. 2^{rm n}+1bigr.$ addition, carry look-ahead addition, diminished-one number representation, VLSI adders, parallel-prefix adders |
24 | Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos |
High-Speed Parallel-Prefix Modulo 2n-1 Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(7), pp. 673-680, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Modulo $2^n-1$ adders, VLSI design, parallel-prefix adders, carry look-ahead adders |
24 | Hussain Al-Asaad, John P. Hayes, Brian T. Murray |
Scalable Test Generators for High-Speed Datapath Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 111-125, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
datapath circuits, scalability, built-in self-test, test generation, on-line testing, carry lookahead |
24 | Andrew Klapper, Mark Goresky |
Cryptanalysis Based on 2-Adic Rational Approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO '95, 15th Annual International Cryptology Conference, Santa Barbara, California, USA, August 27-31, 1995, Proceedings, pp. 262-273, 1995, Springer, 3-540-60221-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cryptanalysis, Binary sequences, rational approximation, feedback with carry shift registers, 2-adic numbers |
23 | Jerry W. Bruce, Mitchell A. Thornton, L. Shivakumaraiah, P. S. Kokate, X. Li |
Efficient Adder Circuits Based on a Conservative Reversible Logic Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA, pp. 83-88, 2002, IEEE Computer Society, 0-7695-1486-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis |
The circuit design of multiple-valued logic voltage-mode adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 162-165, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Alireza Namazi, Seyed Ghassem Miremadi, Alireza Ejlali |
A High Speed and Low Cost Error Correction Technique for the Carry Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Forth International Conference on Availability, Reliability and Security, ARES 2009, March 16-19, 2009, Fukuoka, Japan, pp. 635-640, 2009, IEEE Computer Society, 978-1-4244-3572-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10), pp. 1761-1774, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | François Arnault, Thierry P. Berger |
Correction to "Feedback With Carry Shift Registers Synthesis With the Euclidean Algorithm" [May 04 910-917]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 54(1), pp. 502, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Ashis Kumer Biswas, Md. Mahmudul Hasan, Moshaddek Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu |
A Novel Approach to Design BCD Adder and Carry Skip BCD Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 566-571, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Pierre-Alain Fouque, Denis Réal, Frédéric Valette, M'hamed Drissi |
The Carry Leakage on the Randomized Exponent Countermeasure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2008, 10th International Workshop, Washington, D.C., USA, August 10-13, 2008. Proceedings, pp. 198-213, 2008, Springer, 978-3-540-85052-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Roy Want |
Carry Small, Live Large. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Pervasive Comput. ![In: IEEE Pervasive Comput. 6(3), pp. 2-4, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mobile computer, urban computing |
20 | Ranko Lazic 0001, Thomas Christopher Newcomb, Joël Ouaknine, A. W. Roscoe 0001, James Worrell 0001 |
Nets with Tokens Which Carry Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICATPN ![In: Petri Nets and Other Models of Concurrency - ICATPN 2007, 28th International Conference on Applications and Theory of Petri Nets and Other Models of Concurrency, ICATPN 2007, Siedlce, Poland, June 25-29, 2007, Proceedings, pp. 301-320, 2007, Springer, 978-3-540-73093-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Mark A. Erle, Michael J. Schulte, Brian J. Hickmann |
Decimal Floating-Point Multiplication Via Carry-Save Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 25-27 June 2007, Montpellier, France, pp. 46-55, 2007, IEEE Computer Society, 0-7695-2854-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | John Moskal, Erdal Oruklu, Jafar Saniie |
Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1089-1092, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Michael L. Walters, Kerstin Dautenhahn, Sarah N. Woods, Kheng Lee Koay |
Robotic etiquette: results from user studies involving a fetch and carry task. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HRI ![In: Proceedings of the Second ACM SIGCHI/SIGART Conference on Human-Robot Interaction, HRI 2007, Arlington, Virginia, USA, March 10-12, 2007, pp. 317-324, 2007, ACM, 978-1-59593-617-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
live interactions, human-robot interaction, social robot, personal spaces, user trials, social spaces |
20 | J. J. Rodriguez-Navarro |
Comments on "Carry checking/parity prediction adders and ALUs". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(2), pp. 212-213, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Pawan Kumar Jha, Jyotsna Kumar Mandal |
Cascaded Encryption Through Recursive Carry Addition and Key Rotation (CRCAKR) of a Session Key. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIT ![In: 9th International Conference in Information Technology, ICIT 2006, Bhubaneswar, Orissa, India, 18-21 December 2006, pp. 176-177, 2006, IEEE Computer Society, 0-7695-2635-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Shahnam Khabiri, Maitham Shams |
An MCML four-bit ripple-carry adder design in 1 GHz range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1634-1637, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao |
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 233-236, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage |
20 | Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese |
Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 206-211, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Andrew Klapper |
A Survey of Feedback with Carry Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SETA ![In: Sequences and Their Applications - SETA 2004, Third International Conference, Seoul, Korea, October 24-28, 2004, Revised Selected Papers, pp. 56-71, 2004, Springer, 3-540-26084-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas |
Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 181-185, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ECDL, CMOS, adder, digital circuits |
20 | Ajay Kumar Verma, Paolo Ienne |
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 791-798, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Hwang-Cherng Chow, I-Chyn Wey |
A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 121-124, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Bhushan A. Shinkre, James E. Stine |
A pipelined clock-delayed domino carry-lookahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 171-175, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | B. Kiran Kumar, Parag K. Lala |
On-line Detection of Faults in Carry-Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 912-918, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
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