Search results for "Carry"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
30	Morteza Dorrigiv, Ghassem Jaberipur	Low area/power decimal addition with carry-select correction and carry-select sum-digits.	Integr.	2014	DBLP DOI BibTeX RDF
30	Praveena Murugesan, Thanushkodi Keppanagounder	Design of Optimal Carry Skip Adder and Carry Skip BCD Adder using Reversible Logic Gates.	J. Comput. Sci.	2014	DBLP DOI BibTeX RDF
30	P. Balasubramanian 0001, David A. Edwards, William B. Toms	Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic.	J. Circuits Syst. Comput.	2013	DBLP DOI BibTeX RDF
30	Lalitha Mohana Kalyani-Garimella, Sri Raga Sudha Garimella, Kevin Duda, Eric S. Fetzer	New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A.	MWSCAS	2013	DBLP DOI BibTeX RDF
30	Habib Ghasemizadeh Tamar, Akbar Ghasemizadeh Tamar, Khayrollah Hadidi, Abdollah Khoei, Pourya Hoseini	High speed area reduced 64-bit static hybrid carry-lookahead/carry-select adder.	ICECS	2011	DBLP DOI BibTeX RDF
30	Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz	Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders	CoRR	2010	DBLP BibTeX RDF
30	Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz	Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders	CoRR	2010	DBLP BibTeX RDF
30	Yajuan He, Chip-Hong Chang	A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
30	Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy 0001	Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
30	Gustavo A. Ruiz, Mercedes Granda	An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit.	Microelectron. J.	2004	DBLP DOI BibTeX RDF
30	Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija	Delay optimization of carry-skip adders and block carry-lookahead adders.	IEEE Symposium on Computer Arithmetic	1991	DBLP DOI BibTeX RDF
29	Toshimitsu Fujii, Mitsuru Kaji, Yuya Sasaki 0001, Takahiro Hara, Shojiro Nishio	A Flooding Control Method with Ack-carry for Location-Based Information Dissemination in Mobile Ad Hoc Networks.	SAINT	2011	DBLP DOI BibTeX RDF	flooding control, ack-carry, mobile ad hoc networks, Time To Live (TTL)
29	Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Arun Bhanu	Modeling of Probabilistic Ripple-Carry Adders.	DELTA	2010	DBLP DOI BibTeX RDF	ripple-carry adder, noies modeling, error propagation, Probabilistic computation
29	Verus Pronk, Jan H. M. Korst	Comments on "carry-over round robin: a simple cell scheduling mechanism for ATM network".	IEEE/ACM Trans. Netw.	2001	DBLP DOI BibTeX RDF	carry-over round robin, ATM, delay, fairness
29	Stanislaw J. Piestrak	Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	residue generators, multioperand modular adders, arithmetic error detecting codes, binary-to-residue number system, residue generator, digital arithmetic, adders, Chinese remainder theorem, residue number system, arithmetic codes, residue arithmetic, carry-save adders
29	Vitit Kantabutra	Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	accelerated two-level carry-skip adders, bit positions, bimodal, CMOS VLSI, 12.6 sec, VLSI, delays, adders, CMOS integrated circuits, unimodal, 2 micron
29	Vitit Kantabutra	Designing Optimum One-Level Carry-Skip Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	one-level, 64 bit, 6.23 ns, logic design, digital simulation, adders, SPICE simulation, carry-skip adders, 1 micron
29	Jordi Cortadella, José M. Llabería	Evaluation of A + B = K Conditions Without Carry Propagation.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	parallel adders, carry propagation delay, performance, digital arithmetic, response time, adders
29	Milos D. Ercegovac, Tomás Lang	Fast Multiplication Without Carry-Propagate Addition.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	fast multiplication, carry-propagate adder, LRCF scheme, general radix r, radix-4 signed-digit implementation, digital arithmetic
29	Alain Guyot, Bertrand Hochet, Jean-Michel Muller	A Way to Build Efficient Carry-Skip Adders.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	VLSI design, Carry-skip adders
29	Tom Rhyne	Limitations on Carry Lookahead Networks.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	high-speed arithmetic, Binary addition, carry lookahead
29	Hung Chi Lai, Saburo Muroga	Logic Networks of Carry-Save Adders.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders
29	John J. Shedletsky	Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	End-around-carry (EAC) adder, negative zero, one's complement arithmetic
29	Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen	Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection.	SiPS	2007	DBLP DOI BibTeX RDF
29	Michael T. Frederick, Arun K. Somani	Non-arithmetic carry chains for reconfigurable fabrics.	ICCD	2007	DBLP DOI BibTeX RDF
29	Himanshu Thapliyal, Sumedha K. Gupta	Design of Novel Reversible Carry Look-Ahead BCD Subtractor.	ICIT	2006	DBLP DOI BibTeX RDF
29	Dilip P. Vasudevan, Parag K. Lala	A Technique for Modular Design of Self-Checking Carry-Select Adder.	DFT	2005	DBLP DOI BibTeX RDF
29	Michael Nicolaidis	Carry checking/parity prediction adders and ALUs.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
29	Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.	Optimal joint module-selection and retiming with carry-save representation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
29	Mark A. Erle, Michael J. Schulte	Decimal Multiplication Via Carry-Save Addition.	ASAP	2003	DBLP DOI BibTeX RDF
29	Youngjoon Kim, Ki-Hyuk Sung, Lee-Sup Kim	A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
29	Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan	Partially Duplicated Code-Disjoint Carry-Skip Adder.	DFT	2002	DBLP DOI BibTeX RDF
29	Javier D. Bruguera, Tomás Lang	Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
29	Javier D. Bruguera, Tomás Lang	Multilevel Reverse-Carry Adder.	ICCD	2000	DBLP DOI BibTeX RDF
29	Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.	Bit-level arithmetic optimization for carry-save additions.	ICCAD	1999	DBLP DOI BibTeX RDF
29	Paolo Montuschi, Luigi Ciminiera	n × n carry-save multipliers without final addition.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
29	Naofumi Takagi	Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms.	ISMVL	2002	DBLP DOI BibTeX RDF	carry-save form, carry-propagation-free addition, multiplier recoding, computer arithmetic, signed-digit number representation, digit-recurrence algorithm
29	Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan	A New Divide and Conquer Method for Achieving High Speed Division in Hardware.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Carry Propagate Adders, Pipelineability, Throughput, Latency, Rounding, Carry Save Adders, Radix, SRT
29	Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi 0001	High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multiple-valued current-mode circuits, high-speed multiplier, carry-propagation-free addition trees, multiple-valued current-mode, carry-propagation-free addition, area efficient design, VLSI, VLSI, tree structure, multiplying circuits, redundant number representations, number representations, multiplier design
29	Milos D. Ercegovac, Tomás Lang, Paolo Montuschi	Very-High Radix Division with Prescaling and Selection by Rounding.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	very-high radix division, quotient-digit selection, carry-save, computer arithmetic, digital arithmetic, selection, rounding, redundant representation, prescaling, carry logic, division algorithm
29	Stamatis Vassiliadis, James Phillips, Bart Blaner	Interlock Collapsing ALU's.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement
29	Daniel E. Atkins, Shauchi Ong	Time-Component Complexity of Two Approaches to Multioperand Binary Addition.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	time-component complexity, Adder tree, multioperand addition, carry-save adder, carry-lookahead adder, binary addition
29	Dharma P. Agrawal	High-Speed Arithmetic Arrays.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	carry-look-ahead, carry-save, pipelining, multiplication, division, Arrays, square-root, square, high-speed arithmetic, sign detection, multifunction
29	Dharma P. Agrawal	Arithmetic Algorithms in a Negative Base.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	basic arithmetic operations, interim carry, multiple operand addition, negative base, twin carry, Algorithms, polarization
28	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	A novel FPGA logic block for improved arithmetic performance.	FPGA	2008	DBLP DOI BibTeX RDF	6.2 compressor, carry-chain, compressor tree, multi-operand addition, FPGA, arithmetic circuits
28	M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas	New and Improved Architectures for Montgomery Modular Multiplication.	Mob. Networks Appl.	2007	DBLP DOI BibTeX RDF	reconfigurable multiplier, scalable multiplier, RSA, ECC, carry save adders, Montgomery modular multiplication
28	Viktor Bunimov, Manfred Schimmler	Area and Time Efficient Modular Multiplication of Large Integers.	ASAP	2003	DBLP DOI BibTeX RDF	Montgomery algorithm, interleaved modular multiplication, MSB-first arithmetic, redundant number arithmetic, Modular multiplication, carry save addition
28	Radhika S. Grover, Weijia Shang, Qiang Li	A faster distributed arithmetic architecture for FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF	DALUT, XC4000, carry propagation, cost-performance analysis, distributed arithmetic
28	Çetin Kaya Koç, Ching Yu Hung	Bit-level systolic arrays for modular multiplication.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF	sign estimation, scheduling, systolic array, modular multiplication, carry save adders
28	Jean-Luc Beuchat, Jean-Michel Muller	Automatic Generation of Modular Multipliers for FPGA Applications.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
28	Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait	Area-time optimal adder with relative placement generator.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
28	Andrew Beaumont-Smith, Cheng-Chew Lim	Parallel Prefix Adder Design.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
24	Gang Zhou, Li Li 0027, Harald Michalik	Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
24	Michael Kirkedal Thomsen, Holger Bock Axelsen	Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder.	UC	2008	DBLP DOI BibTeX RDF	quantum computing, adders, circuits, Reversible computing
24	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.	ETS	2006	DBLP DOI BibTeX RDF
24	Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu	Carry Estimation for Two's Complement Fixed-Width Multipliers.	SiPS	2006	DBLP DOI BibTeX RDF
24	Erkay Savas	A Carry-Free Architecture for Montgomery Inversion.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Montgomery inversion, redundant signed representation, elliptic curve cryptography
24	Himanshu Thapliyal, M. B. Srinivas	A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
24	Kenny Johansson, Oscar Gustafsson, Lars Wanhammar	Power Estimation for Ripple-Carry Adders with Correlated Input Data.	PATMOS	2004	DBLP DOI BibTeX RDF
24	Varun Jindal, Alpana Agarwal	Carry Circuitry for LUT-Based FPGA.	VLSI Design	2004	DBLP DOI BibTeX RDF
24	Andrea Lodi 0002, Carlo Chiesa, Fabio Campi, Mario Toma	A flexible LUT-based carry chain for FPGAs.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
24	Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour	A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
24	Viv A. Bartlett, Andrew G. Dempster	Using carry-save adders in low-power multiplier blocks.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
24	Henrik Eriksson, Per Larsson-Edefors, William P. Marnane	A regular parallel multiplier which utilizes multiple carry-propagate adders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
24	Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan	Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead.	IOLTW	2001	DBLP DOI BibTeX RDF
24	Junhyung Um, Taewhan Kim, C. L. Liu 0001	Optimal allocation of carry-save-adders in arithmetic optimization.	ICCAD	1999	DBLP DOI BibTeX RDF
24	Gianluca Cena, Paolo Montuschi, Luigi Ciminiera, Andrea Sanna	A Q-Coder Algorithm with Carry Free Addition.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	image compression, arithmetic coding
24	Janusz Rajski, Jerzy Tyszer	Test responses compaction in accumulators with rotate carry adders.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
24	Michael T. Frederick, Arun K. Somani	Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	carry chain, depth optimal mapping, logic chain
24	Levent Aksoy, Ece Olcay Günes	Area optimization algorithms in high-speed digital FIR filter synthesis.	SBCCI	2008	DBLP DOI BibTeX RDF	high-speed filter design, multiple constant multiplications, subexpression sharing, area optimization, carry-save adders
24	Mark Goresky, Andrew Klapper	Periodicity and Distribution Properties of Combined FCSR Sequences.	SETA	2006	DBLP DOI BibTeX RDF	stream cipher, pseudorandom sequence, Feedback with carry shift register
24	Giorgos Dimitrakopoulos, Dimitris Nikolos	High-Speed Parallel-Prefix VLSI Ling Adders.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	parallel-prefix carry computation, computer arithmetic, VLSI design, Adders
24	Jeremy R. Johnson, Werner Krandick, Anatole D. Ruslanov	Architecture-aware classical Taylor shift by 1.	ISSAC	2005	DBLP DOI BibTeX RDF	ILP scheduling, Taylor shift, delayed carry propagation, multiprecision arithmetic, register tiling, high-performance computing, code generation, memory hierarchy, polynomials, performance tuning, loop unrolling
24	Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos	Diminished-One Modulo 2n+1 Adder Design.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Modulo $big. 2^{rm n}+1bigr.$ addition, carry look-ahead addition, diminished-one number representation, VLSI adders, parallel-prefix adders
24	Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos	High-Speed Parallel-Prefix Modulo 2n-1 Adders.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Modulo $2^n-1$ adders, VLSI design, parallel-prefix adders, carry look-ahead adders
24	Hussain Al-Asaad, John P. Hayes, Brian T. Murray	Scalable Test Generators for High-Speed Datapath Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	datapath circuits, scalability, built-in self-test, test generation, on-line testing, carry lookahead
24	Andrew Klapper, Mark Goresky	Cryptanalysis Based on 2-Adic Rational Approximation.	CRYPTO	1995	DBLP DOI BibTeX RDF	cryptanalysis, Binary sequences, rational approximation, feedback with carry shift registers, 2-adic numbers
23	Jerry W. Bruce, Mitchell A. Thornton, L. Shivakumaraiah, P. S. Kokate, X. Li	Efficient Adder Circuits Based on a Conservative Reversible Logic Gate.	ISVLSI	2002	DBLP DOI BibTeX RDF
23	Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis	The circuit design of multiple-valued logic voltage-mode adders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
20	Alireza Namazi, Seyed Ghassem Miremadi, Alireza Ejlali	A High Speed and Low Cost Error Correction Technique for the Carry Select Adder.	ARES	2009	DBLP DOI BibTeX RDF
20	Ajay Kumar Verma, Philip Brisk, Paolo Ienne	Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
20	François Arnault, Thierry P. Berger	Correction to "Feedback With Carry Shift Registers Synthesis With the Euclidean Algorithm" [May 04 910-917].	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
20	Ashis Kumer Biswas, Md. Mahmudul Hasan, Moshaddek Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu	A Novel Approach to Design BCD Adder and Carry Skip BCD Adder.	VLSI Design	2008	DBLP DOI BibTeX RDF
20	Pierre-Alain Fouque, Denis Réal, Frédéric Valette, M'hamed Drissi	The Carry Leakage on the Randomized Exponent Countermeasure.	CHES	2008	DBLP DOI BibTeX RDF
20	Roy Want	Carry Small, Live Large.	IEEE Pervasive Comput.	2007	DBLP DOI BibTeX RDF	mobile computer, urban computing
20	Ranko Lazic 0001, Thomas Christopher Newcomb, Joël Ouaknine, A. W. Roscoe 0001, James Worrell 0001	Nets with Tokens Which Carry Data.	ICATPN	2007	DBLP DOI BibTeX RDF
20	Mark A. Erle, Michael J. Schulte, Brian J. Hickmann	Decimal Floating-Point Multiplication Via Carry-Save Addition.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
20	John Moskal, Erdal Oruklu, Jafar Saniie	Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Michael L. Walters, Kerstin Dautenhahn, Sarah N. Woods, Kheng Lee Koay	Robotic etiquette: results from user studies involving a fetch and carry task.	HRI	2007	DBLP DOI BibTeX RDF	live interactions, human-robot interaction, social robot, personal spaces, user trials, social spaces
20	J. J. Rodriguez-Navarro	Comments on "Carry checking/parity prediction adders and ALUs".	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
20	Pawan Kumar Jha, Jyotsna Kumar Mandal	Cascaded Encryption Through Recursive Carry Addition and Key Rotation (CRCAKR) of a Session Key.	ICIT	2006	DBLP DOI BibTeX RDF
20	Shahnam Khabiri, Maitham Shams	An MCML four-bit ripple-carry adder design in 1 GHz range.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
20	Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao	64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.	ISVLSI	2004	DBLP DOI BibTeX RDF	CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage
20	Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese	Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware.	DATE	2004	DBLP DOI BibTeX RDF
20	Andrew Klapper	A Survey of Feedback with Carry Shift Registers.	SETA	2004	DBLP DOI BibTeX RDF
20	Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas	Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic.	SBCCI	2004	DBLP DOI BibTeX RDF	ECDL, CMOS, adder, digital circuits
20	Ajay Kumar Verma, Paolo Ienne	Improved use of the carry-save representation for the synthesis of complex arithmetic circuits.	ICCAD	2004	DBLP DOI BibTeX RDF
20	Hwang-Cherng Chow, I-Chyn Wey	A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
20	Bhushan A. Shinkre, James E. Stine	A pipelined clock-delayed domino carry-lookahead adder.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF
20	B. Kiran Kumar, Parag K. Lala	On-line Detection of Faults in Carry-Select Adders.	ITC	2003	DBLP DOI BibTeX RDF