Search results for "FETS"

Hits ?▲	Authors	Title	Venue	Year	Link
19	Tao Deng, Zhaohao Zhang, Yang Zhang, Yuning Li, Zewen Liu 0003	Three-dimensional Graphene FETs for pH Detection.	NEMS	2021	DBLP DOI BibTeX RDF
19	Koki Abe, Masataka Ishihara, Yusuke Hatakenaka, Kazuhiro Umetani, Eiji Hiraki	Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs.	ISIE	2021	DBLP DOI BibTeX RDF
19	Vita Pi-Ho Hu, Cheng-Wei Su, Chun-Chi Yu, Chang-Ju Liu, Cheng-Yang Weng	Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node.	ISCAS	2021	DBLP DOI BibTeX RDF
19	Eun-Bin Park, Taigon Song	An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs).	ISOCC	2021	DBLP DOI BibTeX RDF
19	Jun-Sik Yoon, Rock-Hyun Baek	Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications.	IEEE Access	2020	DBLP DOI BibTeX RDF
19	Aakash Kumar Jain, Mamidala Jagadesh Kumar	Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study.	IEEE Access	2020	DBLP DOI BibTeX RDF
19	Jinsu Jeong, Jun-Sik Yoon, Seunghwan Lee, Rock-Hyun Baek	Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application.	IEEE Access	2020	DBLP DOI BibTeX RDF
19	Jun-Sik Yoon, Rock-Hyun Baek	A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications.	IEEE Access	2020	DBLP DOI BibTeX RDF
19	Narasimhulu Thoti, Yiming Li 0005	Influence of Fringing-Field on DC/AC Characteristics of Si₁₋ₓGeₓ Based Multi-Channel Tunnel FETs.	IEEE Access	2020	DBLP DOI BibTeX RDF
19	Sanmitra Banerjee, Arjun Chaudhuri, Krishnendu Chakrabarty	Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
19	Syed Afzal Ahmad, Naushad Alam	Suppression of ambipolarity in tunnel-FETs using gate oxide as parameter: analysis and investigation.	IET Circuits Devices Syst.	2020	DBLP DOI BibTeX RDF
19	Ning Huang, Weijing Liu, Qinghua Li, Wei Bai, Xiadong Tang, Ting Yang	Investigation and optimization of electrical and thermal performance for 5-nm GAA vertically stacked nanowire FETs.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
19	Shaahin Angizi, Navid Khoshavi, Andrew Marshall, Peter Dowben, Deliang Fan	MERAM: Non-Volatile Cache Memory Based on Magneto-Electric FETs.	CoRR	2020	DBLP BibTeX RDF
19	Weixing Huang, Huilong Zhu, Kunpeng Jia, Zhenhua Wu, Xiaogen Yin, Qiang Huo, Yongkui Zhang	The Investigation of Negative Capacitance Vertical Nanowire FETs Based on SPICE Model at Device-Circuit Level.	CoRR	2020	DBLP BibTeX RDF
19	Xiaoming Chen 0003, Kai Ni 0004, Michael T. Niemier, Dayane Reis, Xiaoyu Sun 0001, Panni Wang, Suman Datta, Xiaobo Sharon Hu, Xunzhao Yin, Matthew Jerry, Shimeng Yu, Ann Franchesca Laguna	The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures.	IEEE Des. Test	2020	DBLP DOI BibTeX RDF
19	Satofumi Souma, Matsuto Ogawa	Acceleration of nonequilibrium Green's function simulation for nanoscale FETs by applying convolutional neural network model.	IEICE Electron. Express	2020	DBLP DOI BibTeX RDF
19	Nilotpal Choudhury, Uma Sharma, Huimei Zhou, Richard G. Southwick, Miaomiao Wang 0006, Souvik Mahapatra	Analysis of BTI, SHE Induced BTI and HCD Under Full VG/VD Space in GAA Nano-Sheet N and P FETs.	IRPS	2020	DBLP DOI BibTeX RDF
19	Kuan-Ting Chen, C. Lo, Y.-Y. Lin, C.-Y. Chueh, C. Chang, G.-Y. Siang, Y.-J. Tseng, Y.-J. Yang, F.-C. Hsieh, S.-H. Chang, H. Liang, S.-H. Chiang, J.-H. Liu, Y.-D. Lin, P.-C. Yeh, C.-Y. Wang, H.-Y. Yang, P.-J. Tzeng, M.-H. Liao, Shu-Tong Chang, Y.-Y. Tseng, Min-Hung Lee	Double Layers Omega FETs with Ferroelectric HfZrO2 for One-Transistor Memory.	IRPS	2020	DBLP DOI BibTeX RDF
19	Robin Wuytens, Sybren Santermans, Mihir Gupta, Bert Du Bois, Simone Severi, Liesbet Lagae, Wim Van Roy, Koen M. Martens	Two-Regime Drift in Electrolytically Gated FETs and BioFETs.	IRPS	2020	DBLP DOI BibTeX RDF
19	Ygor Fonseca, Rafael Nóbrega, Ulysses Duarte, Thiago R. Raddo, Iyad Dayoub, Anderson L. Sanches, Murilo Bellezoni Loiola	Analysis of Si and GaN GAA-NW-FETs in High-k Gate Oxides for Next Generation Mobile Systems.	CSNDSP	2020	DBLP DOI BibTeX RDF
19	Marco A. Azpurua, Marc Pous, Ferran Silva	Uncertainty Analysis in the Measurement of Switching Losses in GaN FETs Power Converters.	I2MTC	2020	DBLP DOI BibTeX RDF
19	Sumitha George, Nicholas Jao, Akshay Krishna Ramanathan, Xueqing Li, Sumeet Kumar Gupta, John Sampson, Vijaykrishnan Narayanan	Integrated CAM-RAM Functionality using Ferroelectric FETs.	ISQED	2020	DBLP DOI BibTeX RDF
19	Shelly Garg, Sneh Saurabh	Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis.	IEEE Access	2019	DBLP DOI BibTeX RDF
19	Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek	Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain.	IEEE Access	2019	DBLP DOI BibTeX RDF
19	Xiangzhan Wang, Zhouquan Tang, Lei Cao, Jingchun Li, Yang Liu	Gate Field Plate Structure for Subthreshold Swing Improvement of Si Line-Tunneling FETs.	IEEE Access	2019	DBLP DOI BibTeX RDF
19	Daniel Nagy, Guillermo Indalecio Fernández, Antonio J. García-Loureiro, Gabriel Espineira, Muhammad A. Elmessary, Karol Kalna, Natalia Seoane	Drift-Diffusion Versus Monte Carlo Simulated ON-Current Variability in Nanowire FETs.	IEEE Access	2019	DBLP DOI BibTeX RDF
19	Bahman Hekmatshoar	Electrical Stability and Flicker Noise of Thin-Film Heterojunction FETs on Poly-Si Substrates.	IEEE Access	2019	DBLP DOI BibTeX RDF
19	Yuhua Liang, Zhangming Zhu, Xueqing Li, Sumeet Kumar Gupta, Suman Datta, Vijaykrishnan Narayanan	Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
19	Xunzhao Yin, Xiaoming Chen 0003, Michael T. Niemier, Xiaobo Sharon Hu	Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
19	Xueqing Li, Juejian Wu, Kai Ni 0004, Sumitha George, Kaisheng Ma, John Sampson, Sumeet Kumar Gupta, Yongpan Liu, Huazhong Yang, Suman Datta, Vijaykrishnan Narayanan	Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs.	IEEE Des. Test	2019	DBLP DOI BibTeX RDF
19	Wen-Che Kuo, Indu Sarangadharan, Anil Kumar Pulikkathodi, Po-Hsuan Chen, Shin-Li Wang, Chang-Run Wu, Yu-Lin Wang	Investigation of Electrical Stability and Sensitivity of Electric Double Layer Gated Field-Effect Transistors (FETs) for miRNA Detection.	Sensors	2019	DBLP DOI BibTeX RDF
19	Asha Rani, Kyle DiCamillo, Md Ashfaque Hossain Khan, Makarand Paranjape, Mona E. Zaghloul	Tuning the Polarity of MoTe2 FETs by Varying the Channel Thickness for Gas-Sensing Applications.	Sensors	2019	DBLP DOI BibTeX RDF
19	Xiaoming Chen 0003, Kai Ni 0004, Michael T. Niemier, Yinhe Han 0001, Suman Datta, Xiaobo Sharon Hu	Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
19	Michiel Vandemaele, Ben Kaczer, Stanislav Tyaginov, Zlatan Stanojevic, Alexander Makarov, Adrian Vaisman Chasin, Erik Bury, Hans Mertens, Dimitri Linten, Guido Groeseneken	Full (Vg, Vd) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs.	IRPS	2019	DBLP DOI BibTeX RDF
19	Maria Ruzzarin, Matteo Borga, Enrico Zanoni, Matteo Meneghini, Gaudenzio Meneghesso, Dong Ji, Wenwen Li, Silvia H. Chan, Anchal Agarwal, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Srabanti Chowdhury	Gate Stability and Robustness of In-Situ Oxide GaN Interlayer Based Vertical Trench MOSFETs (OG-FETs).	IRPS	2019	DBLP DOI BibTeX RDF
19	Jong Chang Yi, Young June Kim, Yi Young Kim, Seok Lee, Deok-Ha Woo, Chulki Kim	Detection of single-stranded DNA using the Dirac voltage change of graphene-based FETs.	TENCON	2019	DBLP DOI BibTeX RDF
19	Hiroki Inoue, Takeshi Aoki, Fumika Akasawa, Toshiki Hamada, Toshihiko Takeuchi, Kousei Nei, Takako Seki, Yuto Yakubo, Kei Takahashi, Shuji Fukai, Takahiko Ishizu, Munehiro Kozuma, Ryota Tajima, Takanori Matsuzaki, Takayuki Ikeda, Makoto Ikeda, Shunpei Yamazaki	Micro Short-Circuit Detector Including S/H Circuit for 1hr Retention and 52dB Comparator Composed of C-Axis Aligned Crystalline IGZO FETs for Li-Ion Battery Protection IC.	ISSCC	2019	DBLP DOI BibTeX RDF
19	Takahiko Ishizu, Yuto Yakubo, Kazuma Furutani, Atsuo Isobe, Masashi Fujita, Tomoaki Atsumi, Yoshinori Ando, Tsutomu Murakawa, Kiyoshi Kato, Masahiro Fujita, Shunpei Yamazaki	A 48 MHz 880-nW Standby Power Normally-Off MCU with 1 Clock Full Backup and 4.69-μs Wakeup Featuring 60-nm Crystalline In-Ga-Zn Oxide BEOL-FETs.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
19	Omor Shoron, Timo Schumann, Manik Goyal, David Kealhofer, Susanne Stemmer	Demonstration of FETs with 3D Dirac Semimetal, Cd3As2.	DRC	2019	DBLP DOI BibTeX RDF
19	Sheikh Z. Ahmed, Yaohua Tan, Avik W. Ghosh	Role of transverse effective mass in Auger generation impacted planar III-V Tunnel FETs.	DRC	2019	DBLP DOI BibTeX RDF
19	Zhihui Cheng, Hattan Abuzaid, Yifei Yu, Shreya Singh, Linyou Cao, Aaron D. Franklin	New Observations in Contact Scaling for 2D FETs.	DRC	2019	DBLP DOI BibTeX RDF
19	Yashwanth Balaji, Quentin Smets, Dennis Lin, I. Asselberghs, Iuliana P. Radu, Guido Groeseneken	Tunnel FETs using Phosphorene/ReS2 heterostructures.	DRC	2019	DBLP DOI BibTeX RDF
19	Shalini Lal, Jing Lu, Brian J. Thibeault, Man Hoi Wong, Chris G. Van de Walle, Steven P. DenBaars, Umesh K. Mishra	Reduction of Saturation Voltage in InGaAs-Channel/lnGaN-Drain Vertical FETs and the role of traps at the InGaAs/lnGaN junction.	DRC	2019	DBLP DOI BibTeX RDF
19	Ankur Nipane, Punnu Jose Sebastian, Younghun Jung, Min Sup Choi, Abhinandan Borah, Won Jong Yoo, James C. Hone, James T. Teherani	Atomic Layer Etching (ALE) of WSe2 Yielding High Mobility p-FETs.	DRC	2019	DBLP DOI BibTeX RDF
19	Venkata Appa Rao Yempada, Srivatsava Jandhyala	Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap.	VDAT	2019	DBLP DOI BibTeX RDF
19	Juejian Wu, Hongtao Zhong, Kai Ni 0004, Yongpan Liu, Huazhong Yang, Xueqing Li	A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs.	DAC	2019	DBLP DOI BibTeX RDF
19	Tony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi, Gage Hills, Bryce Hodson, William Hwang, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra	Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
19	Lisong Li, Yuan Gao 0002, Huaxing Jiang, Philip K. T. Mok, Kei May Lau	An Auto-Zero-Voltage-Switching Quasi-Resonant LED Driver With GaN FETs and Fully Integrated LED Shunt Protectors.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
19	Takayuki Mori, Jiro Ida, Shota Inoue, Takahiro Yoshida	Characterization of Hysteresis in SOI-Based Super-Steep Subthreshold Slope FETs.	IEICE Trans. Electron.	2018	DBLP DOI BibTeX RDF
19	Ali Bozorgmehr, Mohammad Hossein Moaiyeri, Keivan Navi, Nader Bagherzadeh	Ultra-Efficient Fuzzy Min/Max Circuits Based on Carbon Nanotube FETs.	IEEE Trans. Fuzzy Syst.	2018	DBLP DOI BibTeX RDF
19	Saleh S. Alharbi, Salah S. Alharbi, Mohammad Matin 0002	Effects of Gallium Nitride (GaN) Cascode FETs on the Efficiency of an Interleaved DC-DC Converter.	EIT	2018	DBLP DOI BibTeX RDF
19	Nikolaos Makris, Matthias Bucher, Farzan Jazaeri, Jean-Michel Sallese	A Compact Model for Static and Dynamic Operation of Symmetric Double-Gate Junction FETs.	ESSDERC	2018	DBLP DOI BibTeX RDF
19	Nicolo Oliva, Emanuele A. Casu, Matteo Cavalleri, Adrian M. Ionescu	Double gate n-type WSe2 FETs with high-k top gate dielectric and enhanced electrostatic control.	ESSDERC	2018	DBLP DOI BibTeX RDF
19	Richard C. Jaeger, Jeffrey C. Suhling	First and Second Order Piezoresistive Characteristics of CMOS FETs: Weak through Strong Inversion.	ESSDERC	2018	DBLP DOI BibTeX RDF
19	Muyu Yang, Erdal Oruklu	Full Adder Circuit Design Using Lateral Gate-All-Around (LGAA) FETs Based on BSIM-CMG Mode.	MWSCAS	2018	DBLP DOI BibTeX RDF
19	Nagothu Karmel Kranthi, Abhishek Mishra, Adil Meersha, Harsha B. Variar, Mayank Shrivastava	Defect-Assisted Safe Operating Area Limits and High Current Failure in Graphene FETs.	IRPS	2018	DBLP DOI BibTeX RDF
19	Yun Li, K. L. Wang, Shaoyan Di, Peng Huang 0004, Gang Du, Xiao-Yan Liu	PBTI evaluation of In0.65Ga0.35As/In0.53Ga0.47As nanowire FETs with Al2O3 and LaAlO3 gate dielectrics.	IRPS	2018	DBLP DOI BibTeX RDF
19	Maria Ruzzarin, Matteo Meneghini, Carlo De Santi, Gaudenzio Meneghesso, Enrico Zanoni, Min Sun, Tomás Palacios	Degradation of vertical GaN FETs under gate and drain stress.	IRPS	2018	DBLP DOI BibTeX RDF
19	Bhawani Shankar, Ankit Soni, Sayak Dutta Gupta, Mayank Shrivastava	Safe Operating Area (SOA) reliability of Polarization Super Junction (PSJ) GaN FETs.	IRPS	2018	DBLP DOI BibTeX RDF
19	Giovanni V. Resta, Jorge Romero Gonzalez, Yashwanth Balaji, Tarun Agarwal, Dennis Lin, Francky Catthoor, Iuliana P. Radu, Giovanni De Micheli, Pierre-Emmanuel Gaillardon	Towards high-performance polarity-controllable FETs with 2D materials.	DATE	2018	DBLP DOI BibTeX RDF
19	Ahmedullah Aziz, Evelyn T. Breyer, An Chen, Xiaoming Chen 0003, Suman Datta, Sumeet Kumar Gupta, Michael Hoffmann 0008, Xiaobo Sharon Hu, Adrian M. Ionescu, Matthew Jerry, Thomas Mikolajick, Halid Mulaosmanovic, Kai Ni 0004, Michael T. Niemier, Ian O'Connor, Atanu Saha, Stefan Slesazeck, Sandeep Krishna Thirumala, Xunzhao Yin	Computing with ferroelectric FETs: Devices, models, systems, and applications.	DATE	2018	DBLP DOI BibTeX RDF
19	Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr 0001, Walter M. Weber, Akash Kumar 0001	A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.	DATE	2018	DBLP DOI BibTeX RDF
19	Dipankar Ghosh	Nanoscale Tunnel FETs for Internet-of-Things Applications.	IEEE SENSORS	2018	DBLP DOI BibTeX RDF
19	Jan Nevoral, Richard Ruzicka, Václav Simek	From Ambipolarity to Multifunctionality: Novel Library of Polymorphic Gates Using Double-Gate FETs.	DSD	2018	DBLP DOI BibTeX RDF
19	Gabriel Cadilha Marques, Farhan Rasheed, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori	From silicon to printed electronics: A coherent modeling and design flow approach based on printed electrolyte gated FETs.	ASP-DAC	2018	DBLP DOI BibTeX RDF
19	Denise Lee, Mei Yu Soh, Tee Hui Teo, Kiat Seng Yeo	Evaluation of Low Voltage Rectifier Design Using IGBT, MOSFET, and GaN FETs.	TENCON	2018	DBLP DOI BibTeX RDF
19	Tony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra	Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study.	ISSCC	2018	DBLP DOI BibTeX RDF
19	Himadri Pandey, M. Shaygan, Simon Sawallich, Satender Kataria, Martin Otto 0003, Zhenxing Wang, Michael Nagel, Daniel Neumaier, Max C. Lemme	All CVD Boron Nitride Encapsulated Graphene FETs.	DRC	2018	DBLP DOI BibTeX RDF
19	Peng Wu, Jörg Appenzeller	High Performance Complementary Black Phosphorus FETs and Inverter Circuits Operating at Record-Low VDD down to 0.2V.	DRC	2018	DBLP DOI BibTeX RDF
19	C. Klinkert, A. Szabo, D. Campi, C. Stieger, Nicola Marzari, Mathieu Luisier	Novel 2-D Materials for Tunneling FETs: an Ab-initio Study.	DRC	2018	DBLP DOI BibTeX RDF
19	Ruiping Zhou, Jörg Appenzeller	Three-Dimensional Integration of Multi-Channel MoS2 Devices for High Drive Current FETs.	DRC	2018	DBLP DOI BibTeX RDF
19	Yury Yu. Illarionov, Kirby K. H. Smithe, Michael Waltl, Ryan W. Grady, Sanchit Deshmukh, Eric Pop, Tibor Grasser	Annealing and Encapsulation of CVD-MoS2 FETs with 1010On/Off Current Ratio.	DRC	2018	DBLP DOI BibTeX RDF
19	Ting Wu 0004, Abdullah Alharbi, Takashi Taniguchi, Kenji Watanabe, Davood Shahrjerdi	Effects of single vacancy defects on 1/f noise in grapbene/b-BN FETs.	DRC	2018	DBLP DOI BibTeX RDF
19	Benjamin Grisafe, Suman Datta	Investigation of Threshold Switch OFF -State Resistance on Performance Enhancement in 2D Mos2 Phase-FETs.	DRC	2018	DBLP DOI BibTeX RDF
19	Atanu K. Saha, Sumeet Kumar Gupta	Modeling and Comparative Analysis of Hysteretic Ferroelectric and Anti-ferroelectric FETs.	DRC	2018	DBLP DOI BibTeX RDF
19	Md. Hasan Raza Ansari, Nupur Navlakha, Jyi-Tsong Lin, Abhinav Kranti	Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory.	VLSID	2018	DBLP DOI BibTeX RDF
19	Gage Hills, Daniel Bankman, Bert Moons, Lita Yang, Jake Hillard, Alex Kahng, Rebecca Park, Marian Verhelst, Boris Murmann, Max M. Shulaker, H.-S. Philip Wong, Subhasish Mitra	TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs.	DAC	2018	DBLP DOI BibTeX RDF
19	Borna Obradovic, Titash Rakshit, Ryan Hatcher, Jorge Kittl, Rwik Sengupta, Joon Goo Hong, Mark S. Rodder	A Multi-Bit Neuromorphic Weight Cell using Ferroelectric FETs, suitable for SoC Integration.	CoRR	2017	DBLP BibTeX RDF
19	Bin Lu, Hongliang Lu, Yuming Zhang, Yimen Zhang, Xiaoran Cui, Chengji Jin, Chen Liu	Improved analytical model of surface potential with modified boundary conditions for double gate tunnel FETs.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
19	Cheng-Yu Zhang 0001, Haipeng Fu, Yuanyuan Zhu, Jianguo Ma, Qijun Zhang	A hybrid model of III-V FETs with accurate high-order derivatives.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
19	Srinidhi R. Ganiga, R. N. Nikitha, S. Raghuram	Averaging circuit using graphene FETs: A novel approach for analog and digital signal averaging.	ICACCI	2017	DBLP DOI BibTeX RDF
19	Saurabh Sant, Andreas Schenk	Modeling the effect of surface roughness on the performance of line tunnel FETs.	ESSDERC	2017	DBLP DOI BibTeX RDF
19	Thomas Grap, Felix Riederer, Charu Gupta, Joachim Knoch	Buried multi-gate InAs-nanowire FETs.	ESSDERC	2017	DBLP DOI BibTeX RDF
19	Takamasa Kawanago, Ryo Ikoma, Tomoaki Oba, Hiroyuki Takagi	Radical oxidation process for hybrid SAM/HfOx gate dielectrics in MoS2 FETs.	ESSDERC	2017	DBLP DOI BibTeX RDF
19	Nicolo Oliva, Emanuele A. Casu, Wolfgang A. Vitale, Igor Stolichnov, Adrian M. Ionescu	Complementary black phosphorous FETs by workfunction engineering of pre-patterned Au and Ag embedded electrodes.	ESSDERC	2017	DBLP DOI BibTeX RDF
19	Muhammad A. Elmessary, Daniel Nagy, Manuel Aldegunde, Antonio J. García-Loureiro, Karol Kalna	Study of strained effects in nanoscale GAA nanowire FETs using 3D Monte Carlo simulations.	ESSDERC	2017	DBLP DOI BibTeX RDF
19	Dae-Young Jeon, Tim Baldauf, So Jeong Park, Sebastian Pregl, Larysa Baraban, Gianaurelio Cuniberti, Thomas Mikolajick, Walter M. Weber	In-depth electrical characterization of carrier transport in ambipolar Si-NW Schottky-barrier FETs.	ESSDERC	2017	DBLP DOI BibTeX RDF
19	Mona Moradi, Sha Tao, Reza Faghih Mirzaee	Physical Unclonable Functions Based on Carbon Nanotube FETs.	ISMVL	2017	DBLP DOI BibTeX RDF
19	Sandeep Kumar Samal, Sourabh Khandelwal, Asif Islam Khan, Sayeef S. Salahuddin, Chenming Hu, Sung Kyu Lim	Full chip power benefits with negative capacitance FETs.	ISLPED	2017	DBLP DOI BibTeX RDF
19	Atresh Sanne, Saungeun Park, Rudresh Ghosh, Maruthi N. Yogeesh, Chison Liu, Deji Akinwande, Sanjay Kumar Banerjee, Leo Mathew, Rajesh Rao	Record fT, fmax, and GHz amplification in 2dimensional CVD MoS2 embedded gate fets.	ISCAS	2017	DBLP DOI BibTeX RDF
19	Dalvir K. Saini, Agasthya Ayachit, Marian K. Kazimierczuk, Tadashi Suetsugu	High switching frequency performance of E-GaN FETs and silicon MOSFETs.	IAS	2017	DBLP DOI BibTeX RDF
19	Rajat Vishnoi, Pratyush Panday, Mamidala Jagadesh Kumar	DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions.	VLSID	2017	DBLP DOI BibTeX RDF
19	Y. Sudha Vani, N. Usha Rani, Ramesh Vaddi	Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics.	VDAT	2017	DBLP DOI BibTeX RDF
19	Moon Seok Kim, Xueqing Li, Huichu Liu, John Sampson, Suman Datta, Vijaykrishnan Narayanan	Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
19	Mohammad Hossein Moaiyeri, Nooshin Khastoo, Molood Nasiri, Keivan Navi, Nader Bagherzadeh	An Efficient Analog-to-Digital Converter Based on Carbon Nanotube FETs.	J. Low Power Electron.	2016	DBLP DOI BibTeX RDF
19	Rahul Pandey, Saurabh Mookerjea, Suman Datta	Opportunities and Challenges of Tunnel FETs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
19	Alan C. Seabaugh, Cristobal Alessandri, Mina Asghari Heidarlou, Hua-Min Li, Leitao Liu, Hao Lu 0006, Sara Fathipour, Paolo Paletti, Pratyush Pandey, Trond Ytterdal	Steep slope transistors: Tunnel FETs and beyond.	ESSDERC	2016	DBLP DOI BibTeX RDF
19	Katsuhiro Tomioka, Junichi Motohisa, Takashi Fukui	Advances in steep-slope tunnel FETs.	ESSDERC	2016	DBLP DOI BibTeX RDF
19	Takamasa Kawanago, Ryo Ikoma, Du Wanjing, Shunri Oda	Adhesion lithography to fabricate MoS2 FETs with self-assembled monolayer-based gate dielectrics.	ESSDERC	2016	DBLP DOI BibTeX RDF
19	Jorgue Daniel Aguirre Morales, Sébastien Fregonese, C. Mukherjee 0001, Cristell Maneux, Thomas Zimmer, Wei Wei, Henri Happy	Physics-based electrical compact model for monolayer Graphene FETs.	ESSDERC	2016	DBLP DOI BibTeX RDF