Search results for "MTDT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, Yunan Xiang, Sue Ann Ung	Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM.	MTDT	2002	DBLP DOI BibTeX RDF
1	Valery A. Vardanian, Yervant Zorian	A March-Based Fault Location Algorithm for Static Random Access Memories.	MTDT	2002	DBLP DOI BibTeX RDF
1	Alvin Jee	Defect-Oriented Analysis of Memory BIST Tests.	MTDT	2002	DBLP DOI BibTeX RDF
1	Masashi Hashimoto	Adder Merged DRAM Architecture.	MTDT	2002	DBLP DOI BibTeX RDF
1	Emmanuel Rondey, Yann Tellier, Simone Borri	A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios.	MTDT	2002	DBLP DOI BibTeX RDF
1	Mario R. Casu, Philippe Flatresse	Converting an Embedded Low-Power SRAM from Bulk to PD-SOI.	MTDT	2002	DBLP DOI BibTeX RDF
1	A. Kablanian	Embedded Memory Test and Repair.	MTDT	2002	DBLP BibTeX RDF
1		10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France	MTDT	2002	DBLP BibTeX RDF
1	Thierry Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, David Roy 0001, B. Borot, Nicolas Planes, Sylvie Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond	Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).	MTDT	2002	DBLP DOI BibTeX RDF
1	Philippe Magarshack	SoC's Trends and Challenges going to 0.10µm.	MTDT	2002	DBLP BibTeX RDF
1	Bruce F. Cockburn	Panel on Advanced Embedded Memory Technologies.	MTDT	2002	DBLP DOI BibTeX RDF
1	Alberto Manzone, Diego De Costantini	Fault Tolerant Insertion and Verification: A Case Study.	MTDT	2002	DBLP DOI BibTeX RDF
1	Michael Nicolaidis	Soft Error Protection for Embedded Memories.	MTDT	2002	DBLP BibTeX RDF
1	Said Hamdioui, Ad J. van de Goor, Mike Rodgers	March SS: A Test for All Static Simple RAM Faults.	MTDT	2002	DBLP DOI BibTeX RDF	simple/linked faults, fault models, fault coverage, Memory testing, march test
1	Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu	A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.	MTDT	2002	DBLP DOI BibTeX RDF	simulation, memory testing, embedded memory, redundancy analysis, memory repair
1	Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil Shukla	A Fault Modeling Technique to Test Memory BIST Algorithms.	MTDT	2002	DBLP DOI BibTeX RDF
1	Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott	An Investigation into Crosstalk Noise in DRAM Structures.	MTDT	2002	DBLP DOI BibTeX RDF
1	Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	An Approach for Evaluation of Redunancy Analysis Algorithms.	MTDT	2001	DBLP DOI BibTeX RDF
1	Osama Khouri, Stefano Gregori, Dario Soltesz, Guido Torelli, Rino Micheloni	Low Output Resistance Charge Pump for Flash Memory Programming.	MTDT	2001	DBLP DOI BibTeX RDF
1		9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, CA, USA	MTDT	2001	DBLP BibTeX RDF
1	Brian R. Kessler, Jeffrey H. Dreibelbis, Tim McMahon, Joshua S. McCloy, Rex Kho	BIST-Based Bitfail Mapping of an Embedded DRAM.	MTDT	2001	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Ad J. van de Goor	Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests.	MTDT	2001	DBLP DOI BibTeX RDF	detection conditions, memory testing, DRAMs, transient faults, functional fault models, defect simulation
1	Simon Napper, Dian Yang	Equivalence Checking a 256MB SDRAM.	MTDT	2001	DBLP DOI BibTeX RDF
1	Stefano Gregori, Guido Torelli, Osama Khouri, Rino Micheloni	An Error Control Code Scheme for Multilevel Flash Memories.	MTDT	2001	DBLP DOI BibTeX RDF
1	G. Harling	A DRAM Compiler for Fully Optimized Memory Instances.	MTDT	2001	DBLP DOI BibTeX RDF
1	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Carry Logic Modules of SRAM-based FPGAs.	MTDT	2001	DBLP DOI BibTeX RDF
1	Sandeep Koranne, Tom Waayers, Robert Beurze, Clemens Wouters, Sunil Kumar, G. S. Visweswara	A P1500 Compliant Programable BistShell for Embedded Memories.	MTDT	2001	DBLP DOI BibTeX RDF
1	Stella Matarrese, Luca Fasoli	A Method to Caculate Redundancy Coverage for FLASH Memory.	MTDT	2001	DBLP DOI BibTeX RDF
1	Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers	Realistic Fault Models and Test Procedures for Multi-Port SRAMs.	MTDT	2001	DBLP DOI BibTeX RDF
1	Kyung-Saeng Kim, KwangMyoung Rho, Kwyro Lee	Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme.	MTDT	2001	DBLP DOI BibTeX RDF
1	Raymond J. Sung, John C. Koob, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn	Design of an Embedded Fully-Depleted SOI SRAM.	MTDT	2001	DBLP DOI BibTeX RDF
1	Farzin Karimi, Fabrizio Lombardi, V. Swamy Irrinki, T. Crosby	A Parallel Approach for Testing Multi-Port Static Random Access Memories.	MTDT	2001	DBLP DOI BibTeX RDF
1	Osama Khouri, Rino Micheloni, Stefano Gregori, Guido Torelli	Fast Voltage Regulator for Multilevel Flash Memories.	MTDT	2000	DBLP DOI BibTeX RDF
1	Khoan Truong	A Simple Built-In Self Test For Dual Ported SRAMs.	MTDT	2000	DBLP DOI BibTeX RDF
1	Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne	Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions.	MTDT	2000	DBLP DOI BibTeX RDF
1	Said Hamdioui, Ad J. van de Goor, Mike Rodgers, David Eastwick	March Tests for Realistic Faults in Two-Port Memories.	MTDT	2000	DBLP DOI BibTeX RDF
1	Ray Haythornthwaite	Failure Mechanisms in Semiconductor Memory Circuits.	MTDT	2000	DBLP DOI BibTeX RDF
1	Kamal Rajkanan	Yield Analysis Methodology for Low Defectivity Wafer Fabs.	MTDT	2000	DBLP DOI BibTeX RDF
1	Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Redeker	Diagnostic Testing of Embedded Memories Based on Output Tracing.	MTDT	2000	DBLP DOI BibTeX RDF
1	Wen-Tsong Shiue	Optimizing Memory Bandwidth with ILP Based Memory Exploration and Assignment for Low Power Embedded Systems.	MTDT	2000	DBLP DOI BibTeX RDF
1	Michael Redeker, Markus Rudack, Thomas Lobbe, Dirk Niggemeyer	Using GLFSRs for Pseudo-Random Memory BIST.	MTDT	2000	DBLP DOI BibTeX RDF
1	Jörg E. Vollrath	Synchronous Dynamic Memory Test Construction: A Field Approach.	MTDT	2000	DBLP DOI BibTeX RDF
1		8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA	MTDT	2000	DBLP BibTeX RDF
1	Kamran Zarrineh, R. Dean Adams, Aneesha P. Deo	Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories.	MTDT	2000	DBLP DOI BibTeX RDF
1	Christophe Frey, F. Genevaux, C. Issartel, D. Turgis, Jean-Pierre Schoellkopf	A Low Voltage Embedded Single Port SRAM Generator in a 0.18µm Standard CMOS Process.	MTDT	2000	DBLP DOI BibTeX RDF
1	Zemo Yang, Samiha Mourad	Crosstalk in Deep Submicron DRAMs.	MTDT	2000	DBLP DOI BibTeX RDF	Noise and Submicron, Crosstalk, DRAM
1	Rino Micheloni, Matteo Zammattio, Giovanni Campardo, Osama Khouri, Guido Torelli	Hierarchical Sector Biasing Organization for Flash Memories.	MTDT	2000	DBLP DOI BibTeX RDF
1	Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi	Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models.	MTDT	2000	DBLP DOI BibTeX RDF
1	Alvin Jee, Jonathon E. Colburn, V. Swamy Irrinki, Mukesh Puri	Optimizing Memory Tests by Analyzing Defect Coverage.	MTDT	2000	DBLP DOI BibTeX RDF
1	Valerie Lines, Abdullah Ahmed, Peter Ma, Stanley Ma, Robert McKenzie, Hong-Seok Kim, Cynthia Mar	66MHz 2.3M Ternary Dynamic Content Addressable Memory.	MTDT	2000	DBLP DOI BibTeX RDF
1	Ruili Zhang, William C. Black Jr., Marwan M. Hassoun	Windowed MRAM Sensing Scheme.	MTDT	2000	DBLP DOI BibTeX RDF
1	Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno	Computing in Memory Architectures for Digital Image Processing.	MTDT	1999	DBLP DOI BibTeX RDF
1	Daniel P. Van der Velde, Ad J. van de Goor	Designing a Memory Module Tester.	MTDT	1999	DBLP DOI BibTeX RDF
1	Gershom Birk, Duncan G. Elliott, Bruce F. Cockburn	A Comparative Simulation Study of Four Multilevel DRAMs.	MTDT	1999	DBLP DOI BibTeX RDF
1	Betty Prince	A Tribute to Graphics Drams.	MTDT	1999	DBLP DOI BibTeX RDF
1	Larry Fenstermaker, Ilyoung Kim, Jim L. Lewandowski, Jeffrey J. Nagy	Built In Self Test for Ring Addressed FIFOs with Transparent Latches.	MTDT	1999	DBLP DOI BibTeX RDF	Built In Self Test, Memory testing, Embedded memories
1	Jörg E. Vollrath	Tutorial: Characterizing SDRAMS.	MTDT	1999	DBLP DOI BibTeX RDF
1	G. Jack Lipovski, Clement T. Yu	The Dynamic Associative Access Memory Chip and Its Application to SIMD Processing and Full-Text Database Retrieval.	MTDT	1999	DBLP DOI BibTeX RDF
1	Doug Malone	Design Validation of .18 um 1 Ghz Cache and Register Arrays.	MTDT	1999	DBLP DOI BibTeX RDF
1	Piotr R. Sidorowicz	Modeling and Testing Transistor Faults in Content-Addressable Memories.	MTDT	1999	DBLP DOI BibTeX RDF
1	Sue Brown 0002, Jeff Campbell, Sherri Griffin, Dick James, Ray Haythornthwaite	Failure Mechanisms Detected in Memory Chips during Routine Construction Analysis.	MTDT	1999	DBLP DOI BibTeX RDF
1	Mark Brehob, Richard J. Enbody	The Potential of Carbon-Based Memory Systems.	MTDT	1999	DBLP DOI BibTeX RDF	nanotube, buckyball, nanomemory, carbon, memory, nanotechnology, DRAM, RAM
1	Martin Margala	Low Power SRAMs for Battery Operation.	MTDT	1999	DBLP DOI BibTeX RDF
1	Raju Khubchandani	A Fast Test to Generate Flash Memory Threshold Voltage Distribution Map.	MTDT	1999	DBLP DOI BibTeX RDF	flash memory, memory testing, bitmap, threshold voltage
1	Martin Margala	Low-Power SRAM Circuit Design.	MTDT	1999	DBLP DOI BibTeX RDF	design, VLSI, low-power, SRAM, low-voltage
1	David L. Rhodes, Wayne H. Wolf	Unbalanced Cache Systems.	MTDT	1999	DBLP DOI BibTeX RDF
1	Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi	Interconnect Diagnosis of Bus-Connected Multi-RAM Systems.	MTDT	1999	DBLP DOI BibTeX RDF
1	Julie D. Segal, Sergei Bakarian, Jonathon E. Colburn, Madan Kumar, Chang Hong, Alex Shubat	Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis.	MTDT	1999	DBLP DOI BibTeX RDF
1		7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA	MTDT	1999	DBLP BibTeX RDF

Publications at "MTDT"( http://dblp.L3S.de/Venues/MTDT )