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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1030 occurrences of 542 keywords
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Results
Found 1492 publication records. Showing 1492 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
41 | Irith Pomeranz, Sudhakar M. Reddy |
An approach for improving the levels of compaction achieved by vector omission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 463-466, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Alain Darte, Guillaume Huard |
Loop Shifting for Loop Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 12th International Workshop, LCPC'99, La Jolla/San Diego, CA, USA, August 4-6, 1999, Proceedings, pp. 415-431, 1999, Springer, 3-540-67858-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy |
On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 467-471, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
41 | Marc Pouzet |
The Program Compaction Revisited: the Functional Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '95 Parallel Processing, First International Euro-Par Conference, Stockholm, Sweden, August 29-31, 1995, Proceedings, pp. 441-456, 1995, Springer, 3-540-60247-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
41 | Janusz Rajski, Jerzy Tyszer |
Test responses compaction in accumulators with rotate carry adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4), pp. 531-539, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
41 | Chung-Kuan Cheng, Xiaotie Deng, Yuh-Zen Liao, So-Zen Yao |
Symbolic layout compaction under conditional design rules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4), pp. 475-486, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
41 | Chung-Kuan Cheng, David N. Deutsch, Craig Shohara, Mark Taparauskas, Mark Bubien |
Geometric compaction on channel routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(1), pp. 115-127, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
41 | Kurt Mehlhorn, Stefan Näher |
A faster compaction algorithm with automatic jog insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2), pp. 158-166, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
41 | Pei-Yung Hsiao, Wu-Shiung Feng |
Using a multiple storage quad tree on a hierarchical VLSI compaction scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5), pp. 522-536, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
41 | John Valainis, Sinan Kaptanoglu, Erwin Liu, Roberto Suaya |
Two-dimensional IC layout compaction based on topological design rule checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3), pp. 260-275, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
41 | Gaétan Hains |
The Compaction of Acyclic Terms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (2) ![In: PARLE '89: Parallel Architectures and Languages Europe, Volume II: Parallel Languages, Eindhoven, The Netherlands, June 12-16, 1989, Proceedings, pp. 288-303, 1989, Springer, 3-540-51285-3. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
Implementation, memory management, systolic algorithm |
41 | Hyunchul Shin, Chi-Yuan Lo |
An Efficient Two-Dimensional Layout Compaction Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 290-295, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
41 | J. Royle, Mikael Palczewski, H. VerHeyen, N. Naccache, Jiri Soukup |
Geometrical Compaction in One Dimension for Channel Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 140-145, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
41 | Joseph A. Fisher, David Landskov, Bruce D. Shriver |
Microcode compaction: looking backward and looking forward. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1981 National Computer Conference, 4-7 May 1981, Chicago, Illinois, USA, pp. 95-102, 1981, AFIPS Press, 978-1-4503-7921-2. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
|
41 | Dennis W. Ting |
Allocation and compaction - a mathematical model for memory management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the Joint International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 1976, March 29-31, 1976, Cambridge, MA, USA, pp. 311-317, 1976, ACM. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
|
40 | Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy |
Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 450-455, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Layout migration, compaction, constraint generation |
40 | Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy |
On Efficient and Robust Constraint Generation for Practical Layout Legalization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 379-384, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Layout legalization, constraint reduction, compaction, constraint generation |
40 | Ta-Te Lu, Kuo-Wei Wen, Pao-Chi Chang |
Block Reordering Wavelet Packet SPIHT Image Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Pacific Rim Conference on Multimedia ![In: Advances in Multimedia Information Processing - PCM 2001, Second IEEE Pacific Rim Conference on Multimedia, Bejing, China, October 24-26, 2001, Proceedings, pp. 442-449, 2001, Springer, 3-540-42680-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Block reordering, Energy compaction, image coding, Wavelet packet, SPIHT |
40 | Surendra Bommu, Kiran B. Doreswamy, Srimat T. Chakradhar |
A Practical Vector Restoration Technique for Large Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 521-539, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
vector restoration, validation and refinement, fault diagnosis, fault simulation, compaction |
40 | Nikolaos G. Bourbakis, Mohammad Mortazavi |
An efficient building block layout methodology for compact placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 118-123, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
building block layout methodology, compact placement, synthesis placement, GEOMETRIA, geometric reshapings, VLSI regulation, functional performance, connection lines, occupied chip area, neighboring relations, dead space, open holes, channels merging process, legal overlapping, VLSI, formal languages, formal language, network routing, circuit layout CAD, compaction, global routing, integrated circuit layout, integrated circuit interconnections, local routing |
37 | Tomoharu Ugawa, Masahiro Yasugi, Taiichi Yuasa |
Replication-Based Incremental Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISORC ![In: 11th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2008), 5-7 May 2008, Orlando, Florida, USA, pp. 516-524, 2008, IEEE Computer Society, 978-0-7695-3132-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
embedded system, compaction, real-time garbage collection |
37 | Heon-Mo Koo, Prabhat Mishra 0001 |
Specification-based compaction of directed tests for functional validation of pipelined processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 137-142, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
processor validation, test compaction |
37 | Doina Logofatu, Rolf Drechsler |
Comparative Study by Solving the Test Compaction Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 44-49, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Backtracking, Multi-Valued Logic, Test Compaction, Set Cover Problem, Greedy, Don't Cares |
37 | Zheng Wang, D. M. H. Walker |
Dynamic Compaction for High Quality Delay Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 243-248, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dynamic compaction, test generation, delay test, path delay fault |
37 | Ritesh Garg, Richard Putman, Nur A. Touba |
Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 35-42, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
X-tolerant, Linear Compression, Gaussian Elimination, Response Compaction |
37 | Grzegorz Mrugalski, Janusz Rajski, Chen Wang 0014, Artur Pogiel, Jerzy Tyszer |
Isolation of Failing Scan Cells through Convolutional Test Response Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(1), pp. 35-45, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
convolutional compactors, fault diagnosis, test response compaction, scan-based designs |
37 | Sounil Biswas, Ronald D. Blanton |
Statistical Test Compaction Using Binary Decision Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(6), pp. 452-462, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
statistical test compaction, redundant tests, kept tests, go/no-go testing, heterogeneous devices, binary decision trees |
37 | Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei |
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1083-1088, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
design for test, test response compaction |
37 | Bjorn De Sutter, Bruno De Bus, Koen De Bosschere |
Link-time binary rewriting techniques for program compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 27(5), pp. 882-945, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
code abstraction, linker, whole-program optimization, compaction, interprocedural analysis, Program representation, binary rewriting |
37 | Irith Pomeranz, Sudhakar M. Reddy |
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(6), pp. 596-607, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
synchronous sequential circuits, test application time, Static test compaction |
37 | Irith Pomeranz, Sudhakar M. Reddy |
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 541-552, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
scan circuits, test application time, static test compaction |
37 | Toshiyuki Maeda, Kozo Kinoshita |
Compaction of IDDQ Test Sequence Using Reassignment Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 243-249, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reassignment method, weighted random vector, sequential circuit, IDDQ testing, test compaction |
37 | Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy |
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 205-212, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Test Segment, Parallel Pattern Simulator, Vector Restoration, Single Fault Restoration, Fault Coverage, Synchronous Sequential Circuits, Test Length, Static Test Compaction |
37 | Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy |
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 583-587, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
static test compaction synchronous sequential circuits |
37 | Nicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano |
Power invariant vector compaction based on bit clustering and temporal partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 118-120, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power VLSI design, vector compaction, Markov chains, power estimation |
37 | Seiji Kajihara, Kewal K. Saluja |
On Test Pattern Compaction Using Random Pattern Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 464-469, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
test generation, combinational circuit, fault simulation, stuck-at fault, test compaction |
37 | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel |
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 188-195, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
inert subsequence, recurrence subsequence, test set compaction |
37 | Elizabeth M. Rudnick, Janak H. Patel |
Simulation-based techniques for dynamic test sequence compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 67-73, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
dynamic test compaction, compact test sets, genetic algorithms, sequential circuit test generation |
37 | Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak |
Syndrome signature in output compaction for VLSI BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 337-338, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing |
37 | Slawomir Pilarski, André Ivanov, Tiko Kameda |
On minimizing aliasing in scan-based compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(1), pp. 83-90, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
built-in self-test, linear feedback shift register, signature analysis, Aliasing probability, scan path, test response compaction |
37 | Srinivas Devadas, Kurt Keutzer, Sharad Malik |
A synthesis-based test generation and compaction algorithm for multifaults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(1), pp. 91-104, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
Iogic synthesis, test generation, multiple fault, test compaction |
35 | Shuohao Zhang, Curtis E. Dyreson, Zhe Dang |
Compacting XML Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASFAA ![In: Database Systems for Advanced Applications, 11th International Conference, DASFAA 2006, Singapore, April 12-15, 2006, Proceedings, pp. 767-776, 2006, Springer, 3-540-33337-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Lih-Yang Wang, Yen-Tai Lai |
Graph-theory-based simplex algorithm for VLSI layout spacingproblems with multiple variable constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(8), pp. 967-979, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Youtao Zhang, Rajiv Gupta 0001 |
Timestamped Whole Program Path Representation and its Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2001 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Snowbird, Utah, USA, June 20-22, 2001, pp. 180-190, 2001, ACM, 1-58113-414-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Ioannis Voyiatzis |
An Accumulator-Based Compaction Scheme For Online BIST of RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(9), pp. 1248-1251, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Michael Westergaard, Lars Michael Kristensen, Gerth Stølting Brodal, Lars Arge |
The ComBack Method - Extending Hash Compaction with Backtracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICATPN ![In: Petri Nets and Other Models of Concurrency - ICATPN 2007, 28th International Conference on Applications and Theory of Petri Nets and Other Models of Concurrency, ICATPN 2007, Siedlce, Poland, June 25-29, 2007, Proceedings, pp. 445-464, 2007, Springer, 978-3-540-73093-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar |
Hybrid BIST Optimization Using Reseeding and Test Set Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 596-603, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait |
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2556-2564, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Christian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus |
Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 433-438, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato |
A dynamic test compaction procedure for high-quality path delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 348-353, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 659-664, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Keiji Kida, Takehiko Matsuo, Tetsuya Tashiro, Shigetoshi Nakatake |
Sequence-Pair Based Compaction under Equi-Length Constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1015-1018, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke |
Fault detection and diagnosis with parity trees for space compaction of test responses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1095-1098, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fault diagnosis, fault detection, test data compression |
32 | Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait |
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 378-385, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Irith Pomeranz, Sudhakar M. Reddy |
Dynamic Test Compaction for Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 250-255, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Yongfeng Ju, Guangfeng Lin, Yindi Fan, Zongyi Liu |
Intelligent Compaction Control Based on Fuzzy Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2005), 5-8 December 2005, Dalian, China, pp. 930-934, 2005, IEEE Computer Society, 0-7695-2405-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Subhasish Mitra, Kee Sup Kim |
X-compact: an efficient response compaction technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3), pp. 421-432, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | O. N. Malykh, Yu. S. Shakhnovskii |
Optimization of a Data Dependence Graph for the Local Microcode Compaction Problem. Part 1: Problem Statement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Program. Comput. Softw. ![In: Program. Comput. Softw. 30(1), pp. 34-46, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | O. N. Malykh, Yu. S. Shakhnovskii |
Optimization of a Data Dependence Graph for the Local Microcode Compaction Problem. Part 2: Algorithms and Experimental Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Program. Comput. Softw. ![In: Program. Comput. Softw. 30(3), pp. 134-141, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Michael G. Dimopoulos, Panagiotis Linardis |
Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 194-201, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Yinhe Han 0001, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001, Anshuman Chandra |
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 298-305, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Irith Pomeranz, Sudhakar M. Reddy |
Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12), pp. 1663-1670, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Irith Pomeranz, Sudhakar M. Reddy |
A New Approach to Test Generation and Test Compaction for Scan Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11000-11005, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Yinhe Han 0001, Yongjun Xu, Huawei Li 0001, Xiaowei Li 0001, Anshuman Chandra |
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 440-445, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Petros Drineas, Yiorgos Makris |
Independent Test Sequence Compaction through Integer Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 380-386, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | James Wingfield, Jennifer Dworak, M. Ray Mercer |
Function-Based Dynamic Compaction and its Impact on Test Set Sizes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 167-174, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Janusz Rajski, Jerzy Tyszer, Chen Wang 0014, Sudhakar M. Reddy |
Convolutional Compaction of Test Responses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 745-754, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Irith Pomeranz, Sudhakar M. Reddy |
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 335-340, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, Sujoy Mukherjee |
Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWDC ![In: Distributed Computing, Mobile and Wireless Computing 4th International Workshop, IWDC 2002, Calcutta, India, December 28-31, 2002, Proceedings, pp. 234-245, 2002, Springer, 3-540-00355-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Chih-Yang Hsu, Chaur-Wen Wei, Wen-Zen Shen |
A pattern compaction technique for power estimation based on power sensitivity information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 467-470, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Gunnar W. Klau, Petra Mutzel |
Combining Graph Labeling and Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GD ![In: Graph Drawing, 7th International Symposium, GD'99, Stirín Castle, Czech Republic, September 1999, Proceedings, pp. 27-37, 1999, Springer, 3-540-66904-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Krishnendu Chakrabarty, John P. Hayes |
Zero-aliasing space compaction of test responses using multiple parity signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(2), pp. 309-313, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Krishnendu Chakrabarty, John P. Hayes |
On the quality of accumulator-based compaction of test responses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8), pp. 916-922, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
32 | Xiaoling Sun, Wes Tutak |
Error Identification and Data Recovery in MISR-based Data Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 252-260, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
32 | Miroslaw Kutylowski, Tomasz Wierzbicki |
Approximate Compaction and Padded-Sorting on Exclusive Write PRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 174-181, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
32 | André Ivanov, Yervant Zorian |
Count-based BIST compaction schemes and aliasing probability computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(6), pp. 768-777, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
32 | Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli, Carlo H. Séquin |
'Zone-refining' techniques for IC layout compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2), pp. 167-179, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
32 | J. L. Linn, C. D. Ardoin |
All example of using pseudofields to eliminate version shuffling in horizontal code compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989, Dublin, Ireland, August 14-16, 1989, pp. 172-180, 1989, ACM/IEEE, 0-89791-324-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
32 | Shantanu Ganguly, Vijay Pitchumani |
Compaction of a Routed Channel on the Connection Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 779-782, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
32 | Micaela Serra, Jon C. Muzio |
Space compaction for multiple-output circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10), pp. 1105-1113, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
32 | Wayne H. Wolf, Robert G. Mathews, John A. Newkirk, Robert W. Dutton |
Algorithms for optimizing, two-dimensional symbolic layout compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4), pp. 451-466, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
32 | Werner L. Schiele |
Compaction with Incremental Over-Constraint Resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 390-395, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
32 | D. B. Polkl |
A Three-Layer Gridless Channel Router with Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 146-151, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
31 | Tomoharu Ugawa, Hideya Iwasaki, Taiichi Yuasa |
Improved replication-based incremental garbage collection for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 9th International Symposium on Memory Management, ISMM 2010, Toronto, Ontario, Canada, June 5-6, 2010, pp. 73-82, 2010, ACM, 978-1-4503-0054-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
embedded systems, garbage collection, fragmentation, compaction, real-time garbage collection |
31 | Joon-Sung Yang, Nur A. Touba |
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 345-351, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Trace Buffer Observation Window, Two-Dimensional (2-D) Compaction, Cycling Register, Silicon Debug, MISR |
31 | Dominique Chanet, Bjorn De Sutter, Bruno De Bus, Ludo Van Put, Koen De Bosschere |
Automated reduction of the memory footprint of the Linux kernel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 6(4), pp. 23, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
operating system, compression, compaction, specialization, system calls, Linux kernel |
31 | Jing Wang 0006, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger |
Modeling Power Supply Noise in Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(3), pp. 226-234, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power supply noise model, filling, delay test, compaction |
31 | Max H. Garzon, Kiranchand V. Bobba, Andrew Neel |
Efficiency and Reliability of Semantic Retrieval in DNA-Based Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DNA ![In: DNA Computing, 9th International Workshop on DNA Based Computers, DNA9, Madison, WI, USA, June 1-3, 2003, revised Papers, pp. 157-169, 2003, Springer, 3-540-20930-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
DNA-based memories, optimal concentration, data mining in vitro, pattern classification, semantic retrieval, data compaction |
31 | Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu |
High-speed generation of LFSR signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 222-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
high-speed generation, LFSR signatures, compaction simulation, single-input signature register, equivalent multiple-input implementation, finite field theory, high-speed signature computations, lookahead technique, internal-XOR LFSR, external-XOR LFSR, performance evaluation, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, BIST, linear feedback shift register, binary sequences, subsequences |
29 | Lingzhe Zhang, Xiang-Dong Huang, Yan-Kai Wang, Jialin Qiao, Shaoxu Song, Jian-Min Wang |
Time-tired compaction: An elastic compaction scheme for LSM-tree based time-series database. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adv. Eng. Informatics ![In: Adv. Eng. Informatics 59, pp. 102224, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
29 | Junkai Yao, Mao Yue, Hongsheng Ma, Changwei Yang |
Wave Propagation Characteristics and Compaction Status of Subgrade during Vibratory Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 23(4), pp. 2183, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Rajitha Ranasinghe, Arooran Sounthararajah, Jayantha Kodikara 0001 |
An Intelligent Compaction Analyzer: A Versatile Platform for Real-Time Recording, Monitoring, and Analyzing of Road Material Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 23(17), pp. 7507, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Ruicheng Liu, Peiquan Jin, Xiaoliang Wang, Yongping Luo, Zhaole Chu, Yigui Yuan |
Closing the Performance Gap between Leveling and Tiering Compaction via Bundle Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the 32nd International Symposium on High-Performance Parallel and Distributed Computing, HPDC 2023, Orlando, FL, USA, June 16-23, 2023, pp. 143-154, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Irith Pomeranz |
Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2019, Washington, DC, USA, November 9-15, 2019, pp. 1-7, 2019, IEEE, 978-1-7281-4823-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Jiajun Wang, Denghua Zhong, Binping Wu, Mengnan Shi |
Evaluation of Compaction Quality Based on SVR with CFA: Case Study on Compaction Quality of Earth-Rock Dam. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Civ. Eng. ![In: J. Comput. Civ. Eng. 32(3), 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
29 | Narayan Vikas |
Computational Complexity Relationship between Compaction, Vertex-Compaction, and Retraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Discrete Algorithms ![In: J. Discrete Algorithms 52-53, pp. 168-181, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
29 | Fengfeng Pan, Yinliang Yue, Jin Xiong |
dCompaction: Speeding up Compaction of the LSM-Tree via Delayed Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 32(1), pp. 41-54, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
29 | Narayan Vikas |
Computational Complexity Relationship between Compaction, Vertex-Compaction, and Retraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWOCA ![In: Combinatorial Algorithms - 28th International Workshop, IWOCA 2017, Newcastle, NSW, Australia, July 17-21, 2017, Revised Selected Papers, pp. 154-166, 2017, Springer, 978-3-319-78824-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
29 | Narayan Vikas |
Algorithms for Partition of Some Class of Graphs under Compaction and Vertex-Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 67(2), pp. 180-206, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
29 | Tarun Kumar Goyal, Amarpal Singh, Rahul Aggarwal |
Efficient selective compaction and un-compaction of inconsequential logical design units in the schematic representation of a design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 9th East-West Design & Test Symposium, EWDTS 2011, Sevastopol, Ukraine, September 9-12, 2011, pp. 106-112, 2011, IEEE Computer Society, 978-1-4577-1957-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
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