Search results for "microprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Joachim Gläß, Andreas Wurz, Reinhard Männer	SYNAPSE-1: a high-speed general purpose parallel neurocomputer system.	IPPS	1995	DBLP DOI BibTeX RDF	SYNAPSE-1, high-speed general purpose parallel neurocomputer system, neural algorithms, neuro signal processor MA16, general purpose microprocessors, multiprocessor system, systolic arrays, systolic array, neural nets, test algorithm, neural net architecture, processing speed
23	Preeti Ranjan Panda, Nikil D. Dutt	1995 high level synthesis design repository.	ISSS	1995	DBLP DOI BibTeX RDF	1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units
23	Jay K. Adams, Donald E. Thomas	Multiple-process behavioral synthesis for mixed hardware-software systems.	ISSS	1995	DBLP DOI BibTeX RDF	automated iterative improvement technique, concurrency optimization, concurrency tradeoffs, cost/performance ratio, hardware-software tradeoffs, mixed hardware-software systems, multiple-process behavioral synthesis, software engineering, resource allocation, concurrency control, controllers, optimisation, high level synthesis, logic design, multiprocessing systems, microprocessors, ASICs, application specific integrated circuits, ASIC, microprocessor chips, cost-benefit analysis
23	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita	Power analysis and low-power scheduling techniques for embedded DSP software.	ISSS	1995	DBLP DOI BibTeX RDF	circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
23	Santanu Dutta, Wayne H. Wolf, Andrew Wolfe	VLSI issues in memory-system design for video signal processors.	ICCD	1995	DBLP DOI BibTeX RDF	VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design
23	Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller	Emulation verification of the Motorola 68060.	ICCD	1995	DBLP DOI BibTeX RDF	emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level
23	Ching-Long Su, Alvin M. Despain	Cache designs for energy efficiency.	HICSS (1)	1995	DBLP DOI BibTeX RDF	cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits
23	Marc Tremblay, Bill Joy 0001, Ken Shin	A three dimensional register file for superscalar processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows
23	M. J. van der Westhuizen, R. G. Harley, D. C. Levy, D. R. Woodward	Using EDIF for software generation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	EDIF, parallel microprocessors, codesign methods, hardware development tools, real-time parallel C code, FPGA, parallel programming, simulated annealing, simulated annealing, software tools, software tool, logic CAD, circuit CAD, C language, scheduling theory, software generation, development systems
23	B. Hamdi, Hakim Bederr, Michael Nicolaidis	A tool for automatic generation of self-checking data paths.	VTS	1995	DBLP DOI BibTeX RDF	self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers
23	André Seznec, François Bodin	Skewed-associative Caches.	PARLE	1993	DBLP DOI BibTeX RDF	skewed-associative cache, cache, microprocessors, set-associative cache
21	Daniele Rossi 0001, Martin Omaña 0001, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche	Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	microprocessor, on-line testing, control logic
21	George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units.	IEEE Trans. Dependable Secur. Comput.	2009	DBLP DOI BibTeX RDF
21	Rupesh S. Shelar	An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors.	ISPD	2009	DBLP DOI BibTeX RDF	routing, power, clock distribution
21	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis	Test Set Development for Cache Memory in Modern Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
21	Lin Zhang, Aaron Carpenter, Berkehan Ciftcioglu, Alok Garg, Michael C. Huang 0001, Hui Wu	Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
21	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
21	Michael Katelman, José Meseguer 0001, Santiago Escobar 0001	Directed-Logical Testing for Functional Verification of Microprocessors.	MEMOCODE	2008	DBLP DOI BibTeX RDF
21	Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran	When FPGAs are better at floating-point than microprocessors.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, floating-point, arithmetic
21	Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez 0001, Matteo Sonza Reorda	Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.	EvoWorkshops	2008	DBLP DOI BibTeX RDF	microprocessor, BDD, MOEA, path-delay testing
21	Chandramouli V. Kashyap, Pouria Bastani, Kip Killpack, Chirayu S. Amin	Silicon feedback to improve frequency of high-performance microprocessors: an overview.	ICCAD	2008	DBLP DOI BibTeX RDF	speedpath, learning, timing analysis
21	Cecilia Metra, Martin Omaña 0001, T. M. Mak, Asifur Rahman, Simon Tam 0001	Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
21	Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda	A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.	VTS	2008	DBLP DOI BibTeX RDF	SBST, path-delay faults, microprocessor test
21	David S. Hardin	Invited Tutorial: Considerations in the Design and Verification of Microprocessors for Safety-Critical and Security-Critical Applications.	FMCAD	2008	DBLP DOI BibTeX RDF
21	David M. Brooks, Robert P. Dick, Russ Joseph, Li Shang	Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors.	IEEE Micro	2007	DBLP DOI BibTeX RDF	process variation, power models, reliability models, modeling of computer architecture, thermal analysis
21	Loganathan Lingappan, Niraj K. Jha	Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	Youngjin Cho, Naehyuck Chang	Energy-Aware Clock-Frequency Assignment in Microprocessors and Memory Devices for Dynamic Voltage Scaling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
21	Leslie Barnes	Performance Modeling and Analysis for AMD's High Performance Microprocessors.	ISPASS	2007	DBLP DOI BibTeX RDF
21	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
21	Ziyad Hanna	Abstract Modeling and Formal Verification of Microprocessors.	CSR	2007	DBLP DOI BibTeX RDF
21	Cecilia Metra, Martin Omaña 0001, T. M. Mak, Simon Tam 0001	Novel Approach to Clock Fault Testing for High Performance Microprocessors.	VTS	2007	DBLP DOI BibTeX RDF
21	Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin B. Cohen, Jamil A. Wakil	Temperature-limited microprocessors: Measurements and design implications.	VLSI Design	2007	DBLP DOI BibTeX RDF
21	Nitin Yogi, Vishwani D. Agrawal	Spectral RTL Test Generation for Microprocessors.	VLSI Design	2007	DBLP DOI BibTeX RDF
21	Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang	High Performance General-Purpose Microprocessors: Past and Future.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	high performance general-purpose microprocessor, Godson processor, chip multiprocessors, instruction level parallelism, thread level parallelism, data level parallelism
21	Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso	Data-Driven Multithreading Using Conventional Microprocessors.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	nonblocking threads, multiprocessors, high performance computing, multithreading, network of workstations, Dataflow, cache prefetching
21	Nicholas J. Wang, Sanjay J. Patel	ReStore: Symptom-Based Soft Error Detection in Microprocessors.	IEEE Trans. Dependable Secur. Comput.	2006	DBLP DOI BibTeX RDF	Simulation, fault tolerance, fault injection, redundant design
21	Shuai Wang 0006, Jie S. Hu, Sotirios G. Ziavras	On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
21	Hassan Al-Sukhni, David Lindberg, James Holt, Michele Reese	Workload Slicing for Characterizing New Features in High Performance Microprocessors.	MTV	2006	DBLP DOI BibTeX RDF
21	Oguz Ergin	Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors.	PATMOS	2006	DBLP DOI BibTeX RDF
21	Sumeet Kumar, Aneesh Aggarwal	Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors.	HPCA	2006	DBLP DOI BibTeX RDF
21	André V. Fidalgo, Manuel G. Gericota, Gustavo R. Alves, José M. Ferreira 0001	Using NEXUS compliant debuggers for real time fault injection on microprocessors.	SBCCI	2006	DBLP DOI BibTeX RDF	on chip debug, real time systems, fault injection
21	Jörg Platte, Raúl Durán Díaz, Edwin Naroska	A New Encryption and Hashing Scheme for the Security Architecture for Microprocessors.	Communications and Multimedia Security	2006	DBLP DOI BibTeX RDF
21	Zoran A. Salcic, Flavius Gruian, Partha S. Roop, Alif Wahid	A Scheduler Support Unit for Reactive Microprocessors.	RTCSA	2006	DBLP DOI BibTeX RDF
21	Pong-Fei Lu, Nianzheng Cao, Leon J. Sigal, Pieter Woltgens, Raphael Robertazzi, David F. Heidel	A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors.	ISLPED	2006	DBLP DOI BibTeX RDF	pulse latch, low-power, latch
21	Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos	Fast bit permutation unit for media enhanced microprocessors.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Miroslav N. Velev	Formal Verification of Pipelined Microprocessors with Delayed Branches.	ISQED	2006	DBLP DOI BibTeX RDF
21	Wei Wu 0024, Lingling Jin, Jun Yang 0002, Pu Liu, Sheldon X.-D. Tan	A systematic method for functional unit power estimation in microprocessors.	DAC	2006	DBLP DOI BibTeX RDF	microprocessor, power estimation, performance counter
21	Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss 0001	A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.	DAC	2006	DBLP DOI BibTeX RDF	instruction queue, reliability, error correcting codes
21	Bramha Allu, Wei Zhang 0002	Exploiting the replication cache to improve performance for multiple-issue microprocessors.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
21	Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer	An Experimental Study of Soft Errors in Microprocessors.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Soft error sensitivity, Assessment and Protection Techniques, Fault Injection, Soft errors, Microprocessor Architecture
21	Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh	Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
21	Cristian Constantinescu	Neutron SER Characterization of Microprocessors.	DSN	2005	DBLP DOI BibTeX RDF
21	Nicholas J. Wang, Sanjay J. Patel	ReStore: Symptom Based Soft Error Detection in Microprocessors.	DSN	2005	DBLP DOI BibTeX RDF
21	Bin Xue, D. M. H. Walker	Is IDDQ Test of Microprocessors Feasible?	MTV	2005	DBLP DOI BibTeX RDF
21	Sreejit Chakravarty	Improving Logic Test Quality of Microprocessors.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
21	Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail	A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.	ICCD	2005	DBLP DOI BibTeX RDF
21	Kyeong-Jae Lee, Kevin Skadron, Wei Huang 0004	Analytical Model for Sensor Placement on Microprocessors.	ICCD	2005	DBLP DOI BibTeX RDF
21	Haihua Shen, Lin Ma, Heng Zhang	CRPG: a configurable random test-program generator for microprocessors.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
21	Michele Portolan, Régis Leveugle	On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors.	IOLTS	2005	DBLP DOI BibTeX RDF
21	Hans Eberle, Arvinderpal Wander, Nils Gura, Sheueling Chang Shantz, Vipul Gupta	Architectural Extensions for Elliptic Curve Cryptography over GF(2m) on 8-bit Microprocessors.	ASAP	2005	DBLP DOI BibTeX RDF
21	Qing K. Zhu, David Ayers	Power Grid Planning for Microprocessors and SOCS.	ISQED	2005	DBLP DOI BibTeX RDF
21	Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee	Transition Tests for High Performance Microprocessors.	VTS	2005	DBLP DOI BibTeX RDF
21	Mikhail N. Dorojevets	Opportunities, Challenges, and Projections for Superconductor RSFQ Microprocessors.	SC	2005	DBLP DOI BibTeX RDF
21	K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti 0001	A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip.	VLSI Design	2005	DBLP DOI BibTeX RDF
21	Fulvio Corno, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	Code Generation for Functional Validation of Pipelined Microprocessors.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	pipelined micro processors, evolutionary algorithms, functional validation, automatic test program generation
21	Sergio López-Buedo, Eduardo I. Boemo	Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report.	FPGA	2004	DBLP DOI BibTeX RDF	JBits, FPGA, embedded processors, run-time reconfiguration, ring-oscillator, temperature measurement
21	Miroslav N. Velev	Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors.	DATE	2004	DBLP DOI BibTeX RDF
21	Miroslav N. Velev	Using positive equality to prove liveness for pipelined microprocessors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
21	Miroslav N. Velev	Efficient translation of boolean formulas to CNF in formal verification of microprocessors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
21	Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De	Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.	ISLPED	2004	DBLP DOI BibTeX RDF	integrated magnetics, on-die switching converter, power delivery, DC-DC converter, 3-D integration
21	Lorena Anghel, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco	Coupling Different Methodologies to Validate Obsolete Microprocessors.	DFT	2004	DBLP DOI BibTeX RDF
21	Christian Tenllado, Carlos García 0001, Manuel Prieto 0001, Luis Piñuel, Francisco Tirado	Exploiting Multilevel Parallelism Within Modern Microprocessors: DWT as a Case Study.	VECPAR	2004	DBLP DOI BibTeX RDF
21	Wei Qin, Sharad Malik	Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation.	DATE	2003	DBLP DOI BibTeX RDF
21	Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh	Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.	ISLPED	2003	DBLP DOI BibTeX RDF	power supply noise, inductive noise
21	Cecilia Metra, T. M. Mak, Daniele Rossi 0001	Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors.	DFT	2003	DBLP DOI BibTeX RDF
21	Jeremy A. Rowlette, Travis M. Eiles	Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA).	ITC	2003	DBLP DOI BibTeX RDF
21	Jessica H. Tseng, Krste Asanovic	Banked Multiported Register Files for High-Frequency Superscalar Microprocessors.	ISCA	2003	DBLP DOI BibTeX RDF
21	A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl	Electrical and optical clock distribution networks for gigascale microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
21	Mohan G. Kabadi, Natarajan Kannan, Palanidaran Chidambaram, Suriya Narayanan, M. Subramanian, Ranjani Parthasarathi	Dead-Block Elimination in Cache: A Mechanism to Reduce I-cache Power Consumption in High Performance Microprocessors.	HiPC	2002	DBLP DOI BibTeX RDF
21	Daniel Chaver, Christian Tenllado, Luis Piñuel, Manuel Prieto 0001, Francisco Tirado	-D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation.	HiPC	2002	DBLP DOI BibTeX RDF
21	Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich	Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.	VTS	2002	DBLP DOI BibTeX RDF	Microprocessor, Delay Testing
21	Daniel Chaver, Christian Tenllado, Luis Piñuel, Manuel Prieto 0001, Francisco Tirado	Wavelet Transform for Large Scale Image Processing on Modern Microprocessors.	VECPAR	2002	DBLP DOI BibTeX RDF
21	Kanji Hirabayashi	An Algebraic Approach to Formal Verification of Microprocessors.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	formal verification, microprocessor
21	Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple	Power Management in the Amulet Microprocessors.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
21	David M. Brooks, Margaret Martonosi	Dynamic Thermal Management for High-Performance Microprocessors.	HPCA	2001	DBLP DOI BibTeX RDF
21	Alfred Strey, Martin Bange	Accelerating RBF Network Simulation by Using Multimedia Extensions of Modern Microprocessors.	ICANN	2001	DBLP DOI BibTeX RDF
21	David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook	Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.	IEEE Micro	2000	DBLP DOI BibTeX RDF
21	Li-C. Wang, Magdy S. Abadir	On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	custom circuits, high level circuit extraction, ATPG, DFT, time-to-market
21	Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto	Energy estimation for 32-bit microprocessors.	CODES	2000	DBLP DOI BibTeX RDF
21	Rafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado	Power-Efficient Value Speculation for High-Performance Microprocessors.	EUROMICRO	2000	DBLP DOI BibTeX RDF
21	Rafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado	A Power Perspective of Value Speculation for Superscalar Microprocessors.	ICCD	2000	DBLP DOI BibTeX RDF
21	Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube	Formal Verification for Microprocessors with Extendable Instruction Set.	ASAP	2000	DBLP DOI BibTeX RDF	reconfigurable processor architecture, abstraction techniques, formal verification, pipeline processor
21	Miroslav N. Velev, Randal E. Bryant	Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction.	DAC	2000	DBLP DOI BibTeX RDF
21	Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger	Formal verification of iterative algorithms in microprocessors.	DAC	2000	DBLP DOI BibTeX RDF
21	Eric Rotenberg	AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors.	FTCS	1999	DBLP DOI BibTeX RDF	branch prediction and value prediction, trace processors, transient faults, simultaneous multithreading, time redundancy
21	David W. Lloyd, Jim D. Garside, D. A. Gilbert	Memory Faults in Asynchronous Microprocessors.	ASYNC	1999	DBLP DOI BibTeX RDF
21	Jeffrey L. Burns, Jack A. Feldman	C5M-a control-logic layout synthesis system for high-performance microprocessors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
21	Ravi Hosabettu, Mandayam K. Srivas, Ganesh Gopalakrishnan	Decomposing the Proof of Correctness of pipelined Microprocessors.	CAV	1998	DBLP DOI BibTeX RDF
21	Mario Paniccia, Travis M. Eiles, V. R. M. Rao, Wai Mun Yee	Novel optical probing technique for flip chip packaged microprocessors.	ITC	1998	DBLP DOI BibTeX RDF
21	Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden	Design and Analysis of Power Distribution Networks in PowerPC Microprocessors.	DAC	1998	DBLP DOI BibTeX RDF	reliability, PowerPC, PowerPC, IR-drop, power distribution network