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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1754 occurrences of 998 keywords
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Results
Found 2330 publication records. Showing 2330 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
23 | Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Joachim Gläß, Andreas Wurz, Reinhard Männer |
SYNAPSE-1: a high-speed general purpose parallel neurocomputer system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 774-781, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
SYNAPSE-1, high-speed general purpose parallel neurocomputer system, neural algorithms, neuro signal processor MA16, general purpose microprocessors, multiprocessor system, systolic arrays, systolic array, neural nets, test algorithm, neural net architecture, processing speed |
23 | Preeti Ranjan Panda, Nikil D. Dutt |
1995 high level synthesis design repository. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 170-174, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units |
23 | Jay K. Adams, Donald E. Thomas |
Multiple-process behavioral synthesis for mixed hardware-software systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 10-15, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
automated iterative improvement technique, concurrency optimization, concurrency tradeoffs, cost/performance ratio, hardware-software tradeoffs, mixed hardware-software systems, multiple-process behavioral synthesis, software engineering, resource allocation, concurrency control, controllers, optimisation, high level synthesis, logic design, multiprocessing systems, microprocessors, ASICs, application specific integrated circuits, ASIC, microprocessor chips, cost-benefit analysis |
23 | Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita |
Power analysis and low-power scheduling techniques for embedded DSP software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 110-115, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor |
23 | Santanu Dutta, Wayne H. Wolf, Andrew Wolfe |
VLSI issues in memory-system design for video signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 498-503, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design |
23 | Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller |
Emulation verification of the Motorola 68060. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 150-158, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level |
23 | Ching-Long Su, Alvin M. Despain |
Cache designs for energy efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 306-315, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits |
23 | Marc Tremblay, Bill Joy 0001, Ken Shin |
A three dimensional register file for superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 191-201, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows |
23 | M. J. van der Westhuizen, R. G. Harley, D. C. Levy, D. R. Woodward |
Using EDIF for software generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 172-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
EDIF, parallel microprocessors, codesign methods, hardware development tools, real-time parallel C code, FPGA, parallel programming, simulated annealing, simulated annealing, software tools, software tool, logic CAD, circuit CAD, C language, scheduling theory, software generation, development systems |
23 | B. Hamdi, Hakim Bederr, Michael Nicolaidis |
A tool for automatic generation of self-checking data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 460-466, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers |
23 | André Seznec, François Bodin |
Skewed-associative Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE ![In: PARLE '93, Parallel Architectures and Languages Europe, 5th International PARLE Conference, Munich, Germany, June 14-17, 1993, Proceedings, pp. 304-316, 1993, Springer, 3-540-56891-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
skewed-associative cache, cache, microprocessors, set-associative cache |
21 | Daniele Rossi 0001, Martin Omaña 0001, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche |
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 113-114, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
microprocessor, on-line testing, control logic |
21 | George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis |
Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Dependable Secur. Comput. ![In: IEEE Trans. Dependable Secur. Comput. 6(2), pp. 124-134, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Rupesh S. Shelar |
An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 141-148, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
routing, power, clock distribution |
21 | Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis |
Test Set Development for Cache Memory in Modern Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(6), pp. 725-732, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Lin Zhang, Aaron Carpenter, Berkehan Ciftcioglu, Alok Garg, Michael C. Huang 0001, Hui Wu |
Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(9), pp. 1251-1256, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Ilya Wagner, Valeria Bertacco, Todd M. Austin |
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 380-393, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Michael Katelman, José Meseguer 0001, Santiago Escobar 0001 |
Directed-Logical Testing for Functional Verification of Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), June 5-7, 2008, Anaheim, CA, USA, pp. 89-100, 2008, IEEE Computer Society, 978-1-4244-2417-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran |
When FPGAs are better at floating-point than microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 260, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, floating-point, arithmetic |
21 | Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez 0001, Matteo Sonza Reorda |
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings, pp. 224-234, 2008, Springer, 978-3-540-78760-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
microprocessor, BDD, MOEA, path-delay testing |
21 | Chandramouli V. Kashyap, Pouria Bastani, Kip Killpack, Chirayu S. Amin |
Silicon feedback to improve frequency of high-performance microprocessors: an overview. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 778-782, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
speedpath, learning, timing analysis |
21 | Cecilia Metra, Martin Omaña 0001, T. M. Mak, Asifur Rahman, Simon Tam 0001 |
Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 465-473, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda |
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 389-394, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SBST, path-delay faults, microprocessor test |
21 | David S. Hardin |
Invited Tutorial: Considerations in the Design and Verification of Microprocessors for Safety-Critical and Security-Critical Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, FMCAD 2008, Portland, Oregon, USA, 17-20 November 2008, pp. 1-8, 2008, IEEE, 978-1-4244-2735-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | David M. Brooks, Robert P. Dick, Russ Joseph, Li Shang |
Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(3), pp. 49-62, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
process variation, power models, reliability models, modeling of computer architecture, thermal analysis |
21 | Loganathan Lingappan, Niraj K. Jha |
Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(5), pp. 518-530, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Youngjin Cho, Naehyuck Chang |
Energy-Aware Clock-Frequency Assignment in Microprocessors and Memory Devices for Dynamic Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6), pp. 1030-1040, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Leslie Barnes |
Performance Modeling and Analysis for AMD's High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari |
Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 67-74, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing |
21 | Ziyad Hanna |
Abstract Modeling and Formal Verification of Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSR ![In: Computer Science - Theory and Applications, Second International Symposium on Computer Science in Russia, CSR 2007, Ekaterinburg, Russia, September 3-7, 2007, Proceedings, pp. 23, 2007, Springer, 978-3-540-74509-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Cecilia Metra, Martin Omaña 0001, T. M. Mak, Simon Tam 0001 |
Novel Approach to Clock Fault Testing for High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 441-446, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin B. Cohen, Jamil A. Wakil |
Temperature-limited microprocessors: Measurements and design implications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 427-432, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Nitin Yogi, Vishwani D. Agrawal |
Spectral RTL Test Generation for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 473-478, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang |
High Performance General-Purpose Microprocessors: Past and Future. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 21(5), pp. 631-640, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
high performance general-purpose microprocessor, Godson processor, chip multiprocessors, instruction level parallelism, thread level parallelism, data level parallelism |
21 | Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso |
Data-Driven Multithreading Using Conventional Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 17(10), pp. 1176-1188, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
nonblocking threads, multiprocessors, high performance computing, multithreading, network of workstations, Dataflow, cache prefetching |
21 | Nicholas J. Wang, Sanjay J. Patel |
ReStore: Symptom-Based Soft Error Detection in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Dependable Secur. Comput. ![In: IEEE Trans. Dependable Secur. Comput. 3(3), pp. 188-201, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Simulation, fault tolerance, fault injection, redundant design |
21 | Shuai Wang 0006, Jie S. Hu, Sotirios G. Ziavras |
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006, pp. 14-20, 2006, IEEE, 1-4244-0155-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Hassan Al-Sukhni, David Lindberg, James Holt, Michele Reese |
Workload Slicing for Characterizing New Features in High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA, pp. 61-67, 2006, IEEE Computer Society, 978-0-7695-2839-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Oguz Ergin |
Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 477-485, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Sumeet Kumar, Aneesh Aggarwal |
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 12th International Symposium on High-Performance Computer Architecture, HPCA-12 2006, Austin, Texas, USA, February 11-15, 2006, pp. 212-221, 2006, IEEE Computer Society, 0-7803-9368-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | André V. Fidalgo, Manuel G. Gericota, Gustavo R. Alves, José M. Ferreira 0001 |
Using NEXUS compliant debuggers for real time fault injection on microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 214-219, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
on chip debug, real time systems, fault injection |
21 | Jörg Platte, Raúl Durán Díaz, Edwin Naroska |
A New Encryption and Hashing Scheme for the Security Architecture for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Communications and Multimedia Security ![In: Communications and Multimedia Security, 10th IFIP TC-6 TC-11 International Conference, CMS 2006, Heraklion, Crete, Greece, October 19-21, 2006, Proceedings, pp. 120-129, 2006, Springer, 3-540-47820-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Zoran A. Salcic, Flavius Gruian, Partha S. Roop, Alif Wahid |
A Scheduler Support Unit for Reactive Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 16-18 August 2006, Sydney, Australia, pp. 368-372, 2006, IEEE Computer Society, 0-7695-2676-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Pong-Fei Lu, Nianzheng Cao, Leon J. Sigal, Pieter Woltgens, Raphael Robertazzi, David F. Heidel |
A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 85-88, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pulse latch, low-power, latch |
21 | Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos |
Fast bit permutation unit for media enhanced microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Miroslav N. Velev |
Formal Verification of Pipelined Microprocessors with Delayed Branches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 296-299, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Wei Wu 0024, Lingling Jin, Jun Yang 0002, Pu Liu, Sheldon X.-D. Tan |
A systematic method for functional unit power estimation in microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 554-557, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
microprocessor, power estimation, performance counter |
21 | Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss 0001 |
A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 705-708, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
instruction queue, reliability, error correcting codes |
21 | Bramha Allu, Wei Zhang 0002 |
Exploiting the replication cache to improve performance for multiple-issue microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 33(3), pp. 63-71, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer |
An Experimental Study of Soft Errors in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 25(6), pp. 30-39, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Soft error sensitivity, Assessment and Protection Techniques, Fault Injection, Soft errors, Microprocessor Architecture |
21 | Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh |
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(1), pp. 75-85, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Cristian Constantinescu |
Neutron SER Characterization of Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June - 1 July 2005, Yokohama, Japan, Proceedings, pp. 754-759, 2005, IEEE Computer Society, 0-7695-2282-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Nicholas J. Wang, Sanjay J. Patel |
ReStore: Symptom Based Soft Error Detection in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June - 1 July 2005, Yokohama, Japan, Proceedings, pp. 30-39, 2005, IEEE Computer Society, 0-7695-2282-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Bin Xue, D. M. H. Walker |
Is IDDQ Test of Microprocessors Feasible? ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 63-69, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Sreejit Chakravarty |
Improving Logic Test Quality of Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail |
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 253-257, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Kyeong-Jae Lee, Kevin Skadron, Wei Huang 0004 |
Analytical Model for Sensor Placement on Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 24-30, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Haihua Shen, Lin Ma, Heng Zhang |
CRPG: a configurable random test-program generator for microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4171-4174, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Michele Portolan, Régis Leveugle |
On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 247-252, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Hans Eberle, Arvinderpal Wander, Nils Gura, Sheueling Chang Shantz, Vipul Gupta |
Architectural Extensions for Elliptic Curve Cryptography over GF(2m) on 8-bit Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 343-349, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Qing K. Zhu, David Ayers |
Power Grid Planning for Microprocessors and SOCS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 352-356, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee |
Transition Tests for High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 29-34, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Mikhail N. Dorojevets |
Opportunities, Challenges, and Projections for Superconductor RSFQ Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, November 12-18, 2005, Seattle, WA, USA, CD-Rom, pp. 65, 2005, IEEE Computer Society, 1-59593-061-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti 0001 |
A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 207-212, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Fulvio Corno, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero |
Code Generation for Functional Validation of Pipelined Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(3), pp. 269-278, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
pipelined micro processors, evolutionary algorithms, functional validation, automatic test program generation |
21 | Sergio López-Buedo, Eduardo I. Boemo |
Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 79-86, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
JBits, FPGA, embedded processors, run-time reconfiguration, ring-oscillator, temperature measurement |
21 | Miroslav N. Velev |
Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 266-271, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Miroslav N. Velev |
Using positive equality to prove liveness for pipelined microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 316-321, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Miroslav N. Velev |
Efficient translation of boolean formulas to CNF in formal verification of microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 310-315, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De |
Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 263-268, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
integrated magnetics, on-die switching converter, power delivery, DC-DC converter, 3-D integration |
21 | Lorena Anghel, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco |
Coupling Different Methodologies to Validate Obsolete Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 250-255, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Christian Tenllado, Carlos García 0001, Manuel Prieto 0001, Luis Piñuel, Francisco Tirado |
Exploiting Multilevel Parallelism Within Modern Microprocessors: DWT as a Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VECPAR ![In: High Performance Computing for Computational Science - VECPAR 2004, 6th International Conference, Valencia, Spain, June 28-30, 2004, Revised Selected and Invited Papers, pp. 556-568, 2004, Springer, 3-540-25424-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Wei Qin, Sharad Malik |
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10556-10561, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh |
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 229-234, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
power supply noise, inductive noise |
21 | Cecilia Metra, T. M. Mak, Daniele Rossi 0001 |
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 63-70, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Jeremy A. Rowlette, Travis M. Eiles |
Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 264-273, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Jessica H. Tseng, Krste Asanovic |
Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 62-71, 2003, IEEE Computer Society, 0-7695-1945-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl |
Electrical and optical clock distribution networks for gigascale microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(5), pp. 582-594, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Mohan G. Kabadi, Natarajan Kannan, Palanidaran Chidambaram, Suriya Narayanan, M. Subramanian, Ranjani Parthasarathi |
Dead-Block Elimination in Cache: A Mechanism to Reduce I-cache Power Consumption in High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2002, 9th International Conference, Bangalore, India, December 18-21, 2002, Proceedings, pp. 79-88, 2002, Springer, 3-540-00303-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Daniel Chaver, Christian Tenllado, Luis Piñuel, Manuel Prieto 0001, Francisco Tirado |
-D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2002, 9th International Conference, Bangalore, India, December 18-21, 2002, Proceedings, pp. 9-21, 2002, Springer, 3-540-00303-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich |
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 3-8, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Microprocessor, Delay Testing |
21 | Daniel Chaver, Christian Tenllado, Luis Piñuel, Manuel Prieto 0001, Francisco Tirado |
Wavelet Transform for Large Scale Image Processing on Modern Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VECPAR ![In: High Performance Computing for Computational Science - VECPAR 2002, 5th International Conference, Porto, Portugal, June 26-28, 2002, Selected Papers and Invited Talks, pp. 549-564, 2002, Springer, 3-540-00852-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Kanji Hirabayashi |
An Algebraic Approach to Formal Verification of Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(6), pp. 543-544, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
formal verification, microprocessor |
21 | Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple |
Power Management in the Amulet Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 18(2), pp. 42-52, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | David M. Brooks, Margaret Martonosi |
Dynamic Thermal Management for High-Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 171-182, 2001, IEEE Computer Society, 0-7695-1019-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Alfred Strey, Martin Bange |
Accelerating RBF Network Simulation by Using Multimedia Extensions of Modern Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANN ![In: Artificial Neural Networks - ICANN 2001, International Conference Vienna, Austria, August 21-25, 2001 Proceedings, pp. 164-169, 2001, Springer, 3-540-42486-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook |
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 20(6), pp. 26-44, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Li-C. Wang, Magdy S. Abadir |
On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 121-130, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
custom circuits, high level circuit extraction, ATPG, DFT, time-to-market |
21 | Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto |
Energy estimation for 32-bit microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA, 2000, pp. 24-28, 2000, ACM, 1-58113-268-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Rafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado |
Power-Efficient Value Speculation for High-Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1292-1299, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Rafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado |
A Power Perspective of Value Speculation for Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 147-154, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube |
Formal Verification for Microprocessors with Extendable Instruction Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 47-55, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reconfigurable processor architecture, abstraction techniques, formal verification, pipeline processor |
21 | Miroslav N. Velev, Randal E. Bryant |
Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 112-117, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger |
Formal verification of iterative algorithms in microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 201-206, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Eric Rotenberg |
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-29, The Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, USA, June 15-18, 1999, pp. 84-91, 1999, IEEE Computer Society, 0-7695-0213-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
branch prediction and value prediction, trace processors, transient faults, simultaneous multithreading, time redundancy |
21 | David W. Lloyd, Jim D. Garside, D. A. Gilbert |
Memory Faults in Asynchronous Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 19-22 April 1999, Barcelona, Spain, pp. 71-, 1999, IEEE Computer Society, 0-7695-0031-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Jeffrey L. Burns, Jack A. Feldman |
C5M-a control-logic layout synthesis system for high-performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1), pp. 14-23, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Ravi Hosabettu, Mandayam K. Srivas, Ganesh Gopalakrishnan |
Decomposing the Proof of Correctness of pipelined Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 10th International Conference, CAV '98, Vancouver, BC, Canada, June 28 - July 2, 1998, Proceedings, pp. 122-134, 1998, Springer, 3-540-64608-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Mario Paniccia, Travis M. Eiles, V. R. M. Rao, Wai Mun Yee |
Novel optical probing technique for flip chip packaged microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 740-747, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden |
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 738-743, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reliability, PowerPC, PowerPC, IR-drop, power distribution network |
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