Search results for "programmable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Bill Carter	The Evolution of Programmable Logic: Past, Present, and Future Predictions [Abstract].	FPL	2001	DBLP DOI BibTeX RDF
31	Paul Chow, P. Glenn Gulak	A Field-Programmable Mixed-Analog-Digital Array.	FPGA	1995	DBLP DOI BibTeX RDF
30	Daby M. Sow, Alexandros Eleftheriadis	Algorithmic Representation of Visual Information.	ICIP (2)	1997	DBLP DOI BibTeX RDF	algorithmic representation, complexity distortion theory, programmable communication systems design, programmable decoders, intelligent encoders design, tools downloading, audio-visual information, video coding, MPEG-4, rate distortion theory, visual information, algorithm selection
30	Wai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau	Smart-pixel array processors based on optimal cellular neural networks for space sensor applications.	ICCD	1995	DBLP DOI BibTeX RDF	artificial satellites, smart-pixel array processors, optimal cellular neural networks, space sensor applications, hardware annealing, digitally programmable synaptic weights, multisensor parallel interface, programmable multi-dimensional array, optoelectronic neurons, neuroprocessor, scalable multiprocessor system, intelligent multisensor, advanced small satellites, neuroprocessor array chip, performance evaluation, real-time systems, parallel processing, CMOS technology, image sensors, aerospace computing, computing performance, neural chips, intelligent sensors, neural net architecture, active-pixel sensors, cellular neural nets
30	PeiZong Lee, Zvi M. Kedem	Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	nested loop algorithms, multidimensional systolic arrays, correct transformation, programmable systolic arrays, general purpose programmable arrays, planar systolic array implementations, three-dimensional cube-graph algorithm, reindexed Warshall-Floyd path-finding algorithm, parallel algorithms, parallel processing, graph theory, matrix multiplication, data dependence, matrix algebra, cellular arrays, sufficient conditions, necessary conditions, algorithm transformations, automatic compilation
29	Dmitri B. Strukov, Konstantin K. Likharev	A reconfigurable architecture for hybrid CMOS/Nanodevice circuits.	FPGA	2006	DBLP DOI BibTeX RDF	integrated hybrid circuits, architecture, programmable logic, nanoelectronics, programmable interconnect
29	Michael Eisenberg, Gerhard Fischer	Programmable design environments: integrating end-user programming with domain-oriented assistance.	CHI	1994	DBLP DOI BibTeX RDF	programmable applications, programmable design environments, end-user programming, critics, domain-oriented design environments
28	Helger Lipmaa, Guilin Wang, Feng Bao 0001	Designated Verifier Signature Schemes: Attacks, New Security Notions and a New Construction.	ICALP	2005	DBLP DOI BibTeX RDF	Designated verifier signature scheme, non-delegatability, non-programmable random oracle model, signature scheme
28	Rafal Dlugosz, Krzysztof Iniewski	Programmable Switched Capacitor Finite Impulse Response Filter with Circular Memory Implemented in CMOS 0.18 µm Technology.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Baseband filtering, Switched capacitor technique (SC), Finite impulse response (FIR) filter, Programmable filter, GSM, WCDMA
28	Rudolf J. Strijkers, Laurence Muller, Mihai Cristea, Robert G. Belleman, Cees T. A. M. de Laat, Peter M. A. Sloot, Robert J. Meijer	Interactive Control over a Programmable Computer Network Using a Multi-touch Surface.	ICCS (2)	2009	DBLP DOI BibTeX RDF	network management, programmable network, multi-touch interfaces
28	Shinya Kubota, Minoru Watanabe	A nine-context programmable optically reconfigurable gate array with semiconductor lasers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	holographic memory, optically reconfigurable gate arrays, field programmable gate arrays
28	Jonah Probell	Architecture Considerations for Multi-Format Programmable Video Processors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	software programmable processor, hardwired processor, data tiling, SIMD, VLIW, processor architecture, multiprocessing
28	Ioannis Chatzigiannakis, Christos Koninis, Grigorios Prasinos, Christos D. Zaroliagis	Distributed simulation of heterogeneous systems of small programmable objects and traditional processors.	MOBIWAC	2008	DBLP DOI BibTeX RDF	small programmable objects, wireless sensor networks, heterogeneous systems
28	Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne	Design space exploration for field programmable compressor trees.	CASES	2008	DBLP DOI BibTeX RDF	design space exploration (dse), field programmable compressor tree (fpct)
28	Filipe G. Ramos, Laercio Caldeira, Tales Cleber Pimenta	A programmable voltage reference optimized for power management applications.	SBCCI	2007	DBLP DOI BibTeX RDF	DC/DC converter, programmable voltage reference, power management, voltage reference
28	Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol Jeong, Euljoo Jeong, Suk Joong Lee, Hoi-Jun Yoo	A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices.	ISLPED	2007	DBLP DOI BibTeX RDF	mobile multimedia SoC, programmable 3D graphics, low power design
28	Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton	A synthesizable datapath-oriented embedded FPGA fabric.	FPGA	2007	DBLP DOI BibTeX RDF	embedded block, field programmable gate array, system-on-chip, synthesis, integrated circuit, datapath
28	Kenneth L. Calvert, Jim Griffioen, Su Wen	Scalable Network Management Using Lightweight Programmable Network Services.	J. Netw. Syst. Manag.	2006	DBLP DOI BibTeX RDF	ephemeral state, lightweight network services, scalability, network management, Programmable networks
28	Prabhat Mishra 0001, Aviral Shrivastava, Nikil D. Dutt	Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	programmable architecture, design space exploration, Architecture description language, embedded processor, retargetable compilation
28	I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson S. Hall, David V. Anderson	Mapping algorithm for large-scale field programmable analog array.	ISPD	2005	DBLP DOI BibTeX RDF	floating gates, mapping, field programmable analog array
28	Kuan Jen Lin, Shih Hao Huang, Shih Wen Chen	A hardware/software codesign approach for programmable IO devices.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	hardware/software codesign, device driver, programmable controller, software optimization
28	Jan Coppens, Steven Van den Berghe, Herbert Bos, Evangelos P. Markatos, Filip De Turck, Arne Øslebø, Sven Ubik	SCAMPI: A Scalable and Programmable Architecture for Monitoring Gigabit Networks.	MMNS	2003	DBLP DOI BibTeX RDF	High-speed Network Monitoring, Programmable Monitoring, Open Monitoring Platform
28	Bo Hu 0006, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska	Synthesis and placement flow for gain-based programmable regular fabrics.	ISPD	2003	DBLP DOI BibTeX RDF	programmable, regular fabric, gain
28	Michael Conrad, Marcus Schöller, Thomas Fuhrmann, Gerhard Bocksch, Martina Zitterbart	Multiple Language Family Support for Programmable Network Systems.	IWAN	2003	DBLP DOI BibTeX RDF	Flexible Service Platforms, Programming Language, Programmable Networks, Execution Environment
28	Hyong-youb Kim, Vijay S. Pai, Scott Rixner	Exploiting task-level concurrency in a programmable network interface.	PPoPP	2003	DBLP DOI BibTeX RDF	programmable network interface, parallel programming, ethernet, firmware
28	Sanjeev Kumar, Kai Li 0001	Dynamic memory management for programmable devices.	MSP/ISMM	2002	DBLP DOI BibTeX RDF	programmable devices, model checking, reference counting, dynamic memory management
28	Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev	Interconnect enhancements for a high-speed PLD architecture.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA, architecture, interconnect, programmable logic
28	Gerardo Orlando, Christof Paar	A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms.	FCCM	1999	DBLP DOI BibTeX RDF	Galois Fields multiplier, field programmable gate array application, cryptography, elliptic curve cryptography
28	Reiner W. Hartenstein, Jürgen Becker 0001	Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators.	CODES	1997	DBLP DOI BibTeX RDF	structural programmable co-processors, design space exploration, performance estimation
28	Cheng Chang, Chien-Chung Chen, Yao-Liang Chen, Fu-Shin Huang	Real-time scheduling in a programmable radar signal processor.	RTCSA	1997	DBLP DOI BibTeX RDF	programmable radar signal processor, parallel multi-processor architecture, real-time scheduling algorithm, digital signal processing, real-time scheduling, processing speed, radar signal processing
28	An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-Chieh Liu	Parallel programmable video co-processor design.	ICIP	1995	DBLP DOI BibTeX RDF	quadrature mirror filters, parallel programmable video co-processor design, computationally intensive data processing, very high data rate, subband filtering, discrete orthogonal transforms, computational speed, multirate FIR/IIR/DT operations, low-power implementation, QMF, parallel architectures, transforms, high-performance, adaptive filters, adaptive filtering, FIR filters, FIR filtering, video signal processing, digital signal processing chips, low-cost, IIR filters, IIR filtering, hardware overhead, video applications, processing speed
28	Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois 0001	The Design of RPM: An FPGA-based Multiprocessor Emulator.	FPGA	1995	DBLP DOI BibTeX RDF	field-programmable gate arrays, VHDL, rapid prototyping, shared-memory multiprocessors, logic emulation, message-passing multicomputers
28	Paul Metzgen	A high performance 32-bit ALU for programmable logic.	FPGA	2004	DBLP DOI BibTeX RDF	ALU, Apex 20KE, Nios, FPGA, programmable logic, soft processors
27	Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu 0001	Routing for symmetric FPGAs and FPICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
27	Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Efficient FPGAs using nanoelectromechanical relays.	FPGA	2010	DBLP DOI BibTeX RDF	CMOS-NEM FPGA, nanoelectromechanical relay
27	Paul England, Talha Tariq	Towards a Programmable TPM.	TRUST	2009	DBLP DOI BibTeX RDF	Trusted Platforms, Secure Execution, Smart Cards, Trusted Platform Module
27	Min Li 0001, Bruno Bougard, Eduardo Lopez-Estraviz, André Bourdoux, David Novo, Liesbet Van der Perre, Francky Catthoor	Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures.	ICC	2008	DBLP DOI BibTeX RDF
27	Andy Yan, Steven J. E. Wilton	Product-Term-Based Synthesizable Embedded Programmable Logic Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
27	Shuenn-Yuh Lee, Chia-Chyang Chen	VLSI implementation of programmable FFT architectures for OFDM communication system.	IWCMC	2006	DBLP DOI BibTeX RDF	FFT processor, low power, VLSI architecture
27	Charles Hsu	Future Prospective of Programmable Logic Non-volatile Device.	MTDT	2006	DBLP DOI BibTeX RDF
27	Yan Lin 0001, Fei Li 0003, Lei He 0001	Circuits and architectures for field programmable gate array with configurable supply voltage.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
27	Ravi Chawla, Christopher M. Twigg, Paul E. Hasler	An analog modulator/demodulator using a programmable arbitrary waveform generator.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
27	Yan Lin 0001, Fei Li 0003, Lei He 0001	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd
27	A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001	SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis.	FPGA	2004	DBLP DOI BibTeX RDF
27	Binlin Guo, Jiarong Tong	A SC-based novel configurable analog cell.	FPGA	2003	DBLP DOI BibTeX RDF
27	Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama	High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph.	ISVLSI	2002	DBLP DOI BibTeX RDF	FPGA, Reconfigurable processor, Two-dimensional array, Bit-serial architecture
27	Anna Evlogimenou, Raouf Boutaba	Programmable accounting management for virtual private networks.	NOMS	2002	DBLP DOI BibTeX RDF
27	Peter Zipf, Manfred Glesner, Christine Bauer 0002, Hans Wojtkowiak	Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension.	FPL	2002	DBLP DOI BibTeX RDF
27	Andrew T. Campbell, Michael E. Kounavis, John B. Vicente	Programmable Networks.	Informatics	2001	DBLP DOI BibTeX RDF
27	Bogdan Pankiewicz, Marek Wójcikowski, Stanislaw Szczepanski, Yichuang Sun	A CMOS field programmable analog array and its application in continuous-time OTA-C filter design.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
27	Kekoa Proudfoot, William R. Mark, Svetoslav Tzvetkov, Pat Hanrahan	A real-time procedural shading system for programmable graphics hardware.	SIGGRAPH	2001	DBLP DOI BibTeX RDF	shading languages, rendering, graphics hardware, graphics systems
27	T. Lund, Antonio Jesús Torralba Silgado, Ramón González Carvajal	The Architecture of an FPGA-Style Programmable Fuzzy Logic Controller Chip.	ACAC	2000	DBLP DOI BibTeX RDF
27	Elisenda Roca, Servando Espejo-Meana, Rafael Domínguez-Castro, Gustavo Liñán, Ángel Rodríguez-Vázquez	A Programmable Imager for Very High Speed Cellular Signal Processing.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
27	Kamran Zarrineh, Shambhu J. Upadhyaya	Programmable Memory BIST and a New Synthesis Framework.	FTCS	1999	DBLP DOI BibTeX RDF
27	Juan Manuel Moreno, Joan Cabestany, E. Cantó, Julio Faura, Josep Maria Insenser	The Role of Dynamic Reconfiguration for Implementing Artificial Neural Networks Models in Programmable Hardware.	IWANN (2)	1999	DBLP DOI BibTeX RDF
27	Mohammed A. S. Khalid, Jonathan Rose	A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems.	FPGA	1998	DBLP DOI BibTeX RDF
27	Tero Rissa, Tommi Mäkeläinen, Jarkko Niittylahti, Jouni Siirtola	Fast Prototyping Using System Emulators.	FPL	1998	DBLP DOI BibTeX RDF
26	Diego Pedro Morales, Antonio García 0001, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitán-Vallvey	Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration.	FPL	2008	DBLP DOI BibTeX RDF
26	José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras	A configurable and programmable motion estimation processor for the H.264 video codec.	FPL	2008	DBLP DOI BibTeX RDF
26	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Skew-programmable clock design for FPGA and skew-aware placement.	FPGA	2005	DBLP DOI BibTeX RDF	clock architecture, skew optimization, placement
26	Wen Yujie, Jiarong Tong, Charles C. Chiang	Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
26	Jing Ma 0006, Xinming Huang 0001	A System-on-Programmable Chip Approach for MIMO Sphere Decoder.	FCCM	2005	DBLP DOI BibTeX RDF
26	Gordon J. Brebner	Programmable Logic Has More Computational Power than Fixed Logic.	FPL	2004	DBLP DOI BibTeX RDF
26	Adam Donlin, Axel Braun, Adam Rose	SystemC for the Design and Modeling of Programmable Systems.	FPL	2004	DBLP DOI BibTeX RDF
26	Jim Harkin, Michael J. Callaghan, Chris Peters, T. Martin McGinnity, Liam P. Maguire	On-chip and Off-chip Real-Time Debugging for Remotely-Accessed Embedded Programmable Systems.	FPL	2003	DBLP DOI BibTeX RDF
26	John Teifel, Rajit Manohar	Programmable Asynchronous Pipeline Arrays.	FPL	2003	DBLP DOI BibTeX RDF
26	Tyson S. Hall, Paul E. Hasler, David V. Anderson	Field-Programmable Analog Arrays: A Floating-Gate Approach.	FPL	2002	DBLP DOI BibTeX RDF
26	John W. Lockwood, Naji Naufel, Jonathan S. Turner, David E. Taylor	Reprogrammable network packet processing on the field programmable port extender (FPX).	FPGA	2001	DBLP DOI BibTeX RDF	Internet, FPGA, routing, network, ATM, modularity, reconfiguration, processing, IP, hardware, packet
26	John W. Lockwood, Jonathan S. Turner, David E. Taylor	Field programmable port extender (FPX) for distributed routing and queuing.	FPGA	2000	DBLP DOI BibTeX RDF
26	Frank Heile, Andrew Leaver, Kerry Veenstra	Programmable memory blocks supporting content-addressable memory.	FPGA	2000	DBLP DOI BibTeX RDF
26	Guy Lecurieux Lafayette	Programmable System Level Integration Brings System-on-Chip Design to the Desktop.	FPL	2000	DBLP DOI BibTeX RDF
26	Marios Iliopoulos, Theodore Antonakopoulos 0001	Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits.	FPL	2000	DBLP DOI BibTeX RDF
26	Branka Medved Rogina, Karolj Skala, Bozidar Vojnovic	Metastability Characteristics Testing for Programmable Logic Design.	FPL	1996	DBLP DOI BibTeX RDF
26	David W. Trainor, Roger F. Woods	Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays.	FPL	1996	DBLP DOI BibTeX RDF
26	Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx	The Implementation of a Field Programmable Logic Based Co-Processor for the Acceleration of Discrete Event Simulators.	FPL	1996	DBLP DOI BibTeX RDF
26	Andrej Trost, Roman Kuznar, Andrej Zemva, Baldomir Zajc	An Experimental Programmable Environment for Prototyping Digital Circuits.	FPL	1996	DBLP DOI BibTeX RDF
26	C. P. Cowen, S. Monaghan	Performance Characteristics of the Monte-Carlo Clustering Processor (MCCP) - a Field Programmable Logic- based Custom Computing Machine.	FPL	1994	DBLP DOI BibTeX RDF
26	Jo Depreitere, Henk Neefs, Herwig Van Marck, Jan Van Campenhout, Roel Baets, Bart Dhoedt, Hugo Thienpont, Irina Veretennicoff	An Optoelectronic 3-D Field Programmable Gate Array.	FPL	1994	DBLP DOI BibTeX RDF
26	Ricardo de Oliveira Duarte, Michael Nicolaidis	A Test Methodology Applied to Cellular Logic Programmable Gate Arrays.	FPL	1994	DBLP DOI BibTeX RDF
26	Tsuyoshi Isshiki, Wayne Wei-Ming Dai	Hight-Performance Datapath Implementation on Field-Programmable Multi-Chip Module (FPMCM).	FPL	1994	DBLP DOI BibTeX RDF
26	Nigel Toon	Reconfigurable Hardware from Programmable Logic Devices.	FPL	1994	DBLP DOI BibTeX RDF
26	Nigel Toon	Continuous Interconnect Provides Solution to Density/Performance Trade-Off in Programmable Logic.	FPL	1994	DBLP DOI BibTeX RDF
26	David C.-L. Lam	Educational Use of Field Programmable Gate Arrays.	FPL	1994	DBLP DOI BibTeX RDF
26	Juan J. Rodríguez-Andina, Jacobo Álvarez, Enrique Mandado	Design of Safety Systems Using Field Programmable Gate Arrays.	FPL	1994	DBLP DOI BibTeX RDF
26	Jouni Isoaho, Arto Nummela, Hannu Tenhunen	Technologies and Utilization fo Field Programmable Gate Arrays.	FPL	1992	DBLP DOI BibTeX RDF
26	Hartmut Surmann, Ansgar Ungering, Karl Goser	Optimized Fuzzy Controller Architecture for Field Programmable Gate Arrays.	FPL	1992	DBLP DOI BibTeX RDF
26	Naohisa Ohta, Kazuhisa Yamada, Akihiro Tsutsui, Hiroshi Nakada	New Application of FPLs to Programmable Digital Communication Cirucits.	FPL	1992	DBLP DOI BibTeX RDF
26	Alberto L. Sangiovanni-Vincentelli	Some Considerations on Field-Programmable Gate Arrays and Their Impact on System Design.	FPL	1992	DBLP DOI BibTeX RDF
25	Adam Handzlik, Andrzej Jablonski	"Chameleon" Software Defined Control Platform.	EUROCAST	2007	DBLP DOI BibTeX RDF	Signal processing architectures, control platform development, innovative reprogrammable technology, virtual Programmable Logic Controller, Field Programmable Gate Arrays, IP Core
25	Neil W. Bergmann, Yuk Ying Chung	Video Compression on FPGA-Based Custom Computers.	ICIP (1)	1997	DBLP DOI BibTeX RDF	FPGA-based custom computers, 2D DCT algorithms, Scalable Parallel Architecture for Concurrency Experiments, field programmable gate arrays, field programmable gate array, video compression, experimental result, SPACE, workstation, distributed arithmetic, super-computer, processing speed
25	Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi	CODA-R: a reconfigurable testbed for real-time parallel computation.	RTCSA	1997	DBLP DOI BibTeX RDF	CODA-R, reconfigurable testbed, real-time parallel computation, reconfigurable field programmable gate arrays, total execution time, prototype reconfigurable real-time parallel system, real-time parallel architecture, field programmable gate arrays, real-time system, processing elements, computing engine
25	Christian Mandl, Adolfo Fucci	A fast FPGA based coprocessor supporting hard real-time search.	EUROMICRO	1997	DBLP DOI BibTeX RDF	fast FPGA based coprocessor, hard real time search, dual port memories, programmable message driven multi port memories, sequential requests, data acquisition systems, hard real time requirements, DAC systems, coprocessor architectures, file descriptor table, implementation costs, TI DSP C40, hardware strategy, dual port memory, generic searching coprocessor, field programmable gate arrays, hardware implementation, computer systems, high throughput, searching strategy, design approach, DPMs
25	Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology.	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
25	Shriram Kulkarni, Pinaki Mazumder, George I. Haddad	A high-speed 32-bit parallel correlator for spread spectrum communication.	VLSI Design	1996	DBLP DOI BibTeX RDF	pseudonoise codes, radio equipment, high speed pipelined digital parallel correlator, lattice field programmable gate array, 87 MHz, 11.5 ns, field programmable gate arrays, parallel processing, data stream, correlators, CDMA, pipeline processing, CMOS integrated circuit, CMOS digital integrated circuits, transceiver, spread spectrum communication, spread spectrum communication, digital radio, 32 bit, PN sequence
25	Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell	Functional test generation for path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
25	H. A. Xie, Kevin E. Forward, K. M. Adams, Suthikshn Kumar	An SBus Multi-Tracer and its applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	SBus Multi Tracer, SBus monitoring board, logic analyzer, bus analyzer, trace length, board memory, multi occurrences, trigger patterns, multiple partitions, tracing memory, systematic timing information, pattern occurrences, triggering patterns, SUN SPARC station, field programmable gate arrays, Field Programmable Gate Array, FPGA, logic testing, automatic test equipment, system buses, timing diagrams, computerised monitoring
25	Joseph L. Ganley, James P. Cohoon	Thumbnail rectilinear Steiner trees.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	full-set decomposition algorithm, minimum-length set, thumbnail rectilinear Steiner tree problem, VLSI placement algorithms, geometric partitioning, field programmable gate arrays, field-programmable gate arrays, VLSI, dynamic programming, network topology, logic CAD, trees (mathematics), network routing, circuit layout CAD, global routing, line segments
25	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
25	Jean-Francois Guillaud, Max Roger Pokam, Gérard Michel	An ATM-Based Multimedia Integrated Manufacturing System .	HPDC	1995	DBLP DOI BibTeX RDF	ATM-based multimedia integrated manufacturing system, high-speed communication technologies, intelligent network interface board, field programmable gate array component, high speed communication links, field programmable gate arrays, protocols, protocols, asynchronous transfer mode, multimedia systems, multimedia applications, computer integrated manufacturing, real time distributed systems
25	Kimberly Williams	Using object oriented analysis and design in a non-object oriented environment experience report.	ICSM	1995	DBLP DOI BibTeX RDF	control system analysis computing, nonobject oriented environment, subsystem development, independent test, Allen-Bradley's 6200 Series Programming Software for Programmable Controllers, structured analysis/structured design subsystems, function point number, code line number, subsystem function number, defect number, defect fixing time, complexity, metrics, software maintenance, software metrics, programming environments, program testing, object oriented design, object-oriented methods, object oriented analysis, structured programming, programmable controllers, control system CAD, development time, Object Modeling Technique