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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 455 occurrences of 313 keywords
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Results
Found 754 publication records. Showing 754 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | B. Lorente, Raul Aragonés, Joan Oliver, Carles Ferrer 0001 |
Behavioural modelling and simulation for heterogeneous design applied to aerospace inertial microinstrumentation development. |
SCSC |
2007 |
DBLP BibTeX RDF |
smart inertial sensors, UML, design methodology, behavioral modeling, distributed architecture, VHDL-AMS |
19 | Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin |
An efficient H.264 intra frame coder system design. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Esra Sahin, Ilker Hamzaoglu |
Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Esra Sahin, Ilker Hamzaoglu |
An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Serkan Oktem, Ilker Hamzaoglu |
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Taemin Kim, Xun Liu |
Compatibility path based binding algorithm for interconnect reduction in high level synthesis. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf |
Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers. |
IEEE International Workshop on Rapid System Prototyping |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Flavio M. de Paula, Alan J. Hu |
EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation. |
CAV |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Sinan Yalcin, Ilker Hamzaoglu |
A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Youngsun Han, Seokjoong Hwang, Seon Wook Kim |
Jaguar: a compiler infrastructure for Java reconfigurable computing. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Michael Cowell, Adam Postula |
Rachael SPARC: An Open Source 32-bit Microprocessor Core for SoCs. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Mustafa Parlak, Ilker Hamzaoglu |
An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter. |
AHS |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Ansuman Banerjee, Pallab Dasgupta |
The open family of temporal logics: Annotating temporal operators with input constraints. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Pankaj Golani, Peter A. Beerel |
Back Annotation in High Speed Asynchronous Design. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Youngsik Kim, Parija Sule, Nazanin Mansouri |
Exploiting PSL standard assertions in a theorem-proving-based verification environment. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
assertion-based design, modeling, verification, theorem-proving, formal semantics, PSL |
19 | Ivan Blunno, Luciano Lavagno |
Designing an asynchronous microcontroller using Pipefitter. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Hye-On Jang, Minsoo Kang, Myeong-jin Lee, Kwanyeob Chae, Kookpyo Lee, Kyuhyun Shim |
High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Alan G. Strelzoff |
Functional Programming for Reconfigurable Computing. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Arvind, Rishiyur S. Nikhil, Daniel L. Rosenband, Nirav Dave |
High-level synthesis: an essential ingredient for designing complex ASICs. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Kausik Datta, Partha Pratim Das |
Assertion Based Verification Using HDVL. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu |
Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits. |
IWDC |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Jean Oudinot |
The Most Complete Mixed-Signal Simulation Solution with ADVance MS. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson |
Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Tun Li, Yang Guo 0003, Sikun Li |
An Automatic Circuit Extractor for RTL Verification. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi |
The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Grant Martin |
SystemC and the Future of Design Languages: Opportunities for Users and Research. |
SBCCI |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Gérard Berry, Michael Kishinevsky, Satnam Singh |
System Level Design and Verification Using a Synchronous Language. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Manish Amde, Ivan Blunno, Christos P. Sotiriou |
Automating the design of an asynchronous DLX microprocessor. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
DLX, asynchronous, design flow |
19 | Ivan Blunno, Luciano Lavagno |
Designing an Asynchronous Microcontroller Using Pipefitter. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Richard Sharp |
Functional Design Using Behavioural and Structural Components. |
FMCAD |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Raik Brinkmann, Rolf Drechsler |
RTL-Datapath Verification using Integer Linear Programming. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Luc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng |
RTL c-based methodology for designing and verifying a multi-threaded processor. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
formal equivalence, design, verification, RTL, checking, C/C++ |
19 | Kazutoshi Kobayashi, Hidetoshi Onodera |
ST: PERL package for simulation and test environment. |
ISCAS (5) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Akira Matsuzawa |
High Quality Analog CMOS and Mixed Signal LSI Design. |
ISQED |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Edmund M. Clarke, Steven M. German, Yuan Lu 0004, Helmut Veith, Dong Wang |
Executable Protocol Specification in ESL. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Richard Goering, Clifford E. Cummings, Steven E. Schulz, Simon Davidman, John Sanguinetti, Joachim Kunkel, Oz Levia |
The future of system design languages (panel session). |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Richard Kelsey, William D. Clinger, Jonathan Rees |
Revised5 Report on the Algorithmic Language Scheme. |
ACM SIGPLAN Notices |
1998 |
DBLP DOI BibTeX RDF |
SCHEME |
19 | Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò |
Gate-level power and current simulation of CMOS integrated circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Yun-Hung Liaw, Shih-Hao Hung, Chia-Heng Tu |
V2X: An Automated Tool for Building SystemC-Based Simulation Environments in Designing Multicore Systems-on-Chips. |
ISPA |
2010 |
DBLP DOI BibTeX RDF |
Systems-on-Chips, Multicore, translator, SystemC, Verilog, system-level simulation |
19 | Sina Meraji, Wei Zhang 0034, Carl Tropper |
Brief announcement: a reinforcement learning approach for dynamic load-balancing of parallel digital logic simulation. |
SPAA |
2010 |
DBLP DOI BibTeX RDF |
digital logic simulation, reinforcement learning, dynamic load-balancing, time warp, verilog |
19 | ByongChan Lim, Jaeha Kim, Mark A. Horowitz |
An efficient test vector generation for checking analog/mixed-signal functional models. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
linear abstraction, validation, equivalence checking, verilog, functional model, test vector, mixed-signal circuits |
19 | Xiumin Wang, Yang Zhang, Qiang Ye, Shihua Yang |
A New Algorithm for Designing Square Root Calculators Based on FPGA with Pipeline Technology. |
HIS (1) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, algorithm, pipeline, square root, Verilog HDL |
19 | Yang Zhang, Xiumin Wang, Yuduo Wang |
A New Design of HDB3 Encoder and Decoder Based on FPGA. |
HIS (1) |
2009 |
DBLP DOI BibTeX RDF |
HDB3, FPGA, encoder, decoder, Verilog HDL |
19 | Ronny Krashinsky, Christopher Batten, Krste Asanovic |
Implementing the scale vector-thread processor. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
hybrid C++/Verilog simulation, iterative VLSI design flow, procedural datapath pre-placement, vector-thread processors, multithreaded processors, Vector processors |
19 | Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu |
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Verilog-AMS, Static timing analysis, Look-up table |
19 | James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois |
ESys.Net: a new solution for embedded systems modeling and simulation. |
LCTES |
2004 |
DBLP DOI BibTeX RDF |
CIL, ESys.Net, attribute programming, component-based programming, simulation, Java, modeling, embedded systems, C++, framework, system on chip, VHDL, SystemC, hardware/software codesign, C#, Net, Verilog, HDLs, SystemVerilog |
19 | Stephen A. Edwards |
Tutorial: Compiling concurrent languages for sequential processors. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
communication, Petri nets, Compilation, concurrency, code generation, partial evaluation, dataflow, Verilog, Esterel, sequential, Lustre, discrete-event |
19 | Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto |
System-Level Design of IEEE1394 Bus Segment Bridge. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
HW/SW co-simulation, IEEE1394, PLI, bus bridge, C/C++, verilog-HDL |
19 | Oliver Schliebusch, Andreas Hoffmann 0002, Achim Nohl, Gunnar Braun, Heinrich Meyr |
Architecture Implementation Using the Machine Description Language LISA. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Design, Implementation, Synthesis, VHDL, Exploration, SystemC, ASIP, Verilog, LISA |
19 | Marcel Jacomet, Roger Wälti, Lukas Winzenried, Jaime Perez, Martin Gysel |
ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
test bench, test machine, CAT-tool, ProTest, FPGA, VHDL, rapid prototyping, Verilog-HDL |
19 | Gunther Lehmann, Bernhard Wunder, Klaus D. Müller-Glaser |
Basic concepts for an HDL reverse engineering tool-set. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
VHDL Verilog Hardware Description Reuse Reverse Engineering Hypertext CASE Visualization Productivity Design Process Analysis Control Flow ADA Graphical Symbol, VHDL |
18 | Apoorva Banerjee |
Intelligent Traffic Light Controller using Verilog and Xilinx Spartan-3e. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Dias Azhigulov, Zeqin Lu, James Pond, Lukas Chrostowski, Sudip Shekhar |
Enabling data-driven and bidirectional model development in Verilog-A for photonic devices. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Hugh D. Morison, Jagmeet Singh, Nayem Al Kayed, A. Aadhi, Maryam Moridsadat, Marcus Tamura, Alexander N. Tait, Bhavin J. Shastri |
Nonlinear dynamics in neuromorphic photonic networks: physical simulation in Verilog-A. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie |
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu 0001 |
BetterV: Controlled Verilog Generation with Discriminative Guidance. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Andrea Ballo, Alfio Dario Grasso, Marco Privitera |
Demystifying Regulating Active Rectifiers for Energy Harvesting Systems: A Tutorial Assisted by Verilog-A Models. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Sarwono Sutikno, Septafiansyah Dwi Putra, Fajar Wijitrisnanto, Muhamad Erza Aminanto |
Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
18 | C. Mukherjee 0001, Djeber Guendouz, Marina Deng, H. Bertin, Antoine Bobin, Nicolas Vaissiere, Christophe Caillaud, Akshay M. Arabhavi, Rimjhim Chaudhary, Olivier Ostinelli, Colombo R. Bolognesi, Patrick Mounaix, Cristell Maneux |
SPICE Modeling in Verilog-A for Photo-Response in UTC-Photodiodes Targeting Beyond-5G Circuit Design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren |
VerilogEval: Evaluating Large Language Models for Verilog Code Generation. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Enrique Dehaerne, Bappaditya Dey, Sandip Halder, Stefan De Gendt |
A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu |
Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Shailja Thakur, Baleegh Ahmad, Hammond Pearce, Benjamin Tan 0001, Brendan Dolan-Gavitt, Ramesh Karri, Siddharth Garg |
VeriGen: A Large Language Model for Verilog Code Generation. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Anik Mallik, Sanjoy Kundu, Md. Ashikur Rahman |
An FPGA-Based Semi-Automated Traffic Control System Using Verilog HDL. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Vamsi K. Vytla, Larry Doolittle |
Newad: A register map automation tool for Verilog. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Kiran Thorat, Jiahui Zhao, Yaotian Liu, Hongwu Peng, Xi Xie, Bin Lei, Jeff Zhang 0001, Caiwen Ding |
Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Luca Ezio Pozzoni, Fabrizio Ferrandi, Loris Mendola, Alfio Antonino Palazzo, Francesco Pappalardo 0002 |
Using High-Level Synthesis to model System Verilog procedural timing controls. |
DATE |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan 0001, Ramesh Karri, Brendan Dolan-Gavitt, Siddharth Garg |
Benchmarking Large Language Models for Automated Verilog RTL Code Generation. |
DATE |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Yonghun Lee, Daejin Park |
Fast Verilog Simulation using Tel-based Verification Code Generation for Dynamically Reloading from Pre-Simulation Snapshot. |
ICAIIC |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Jun-Cheol Lee, Tae-Oh Kim, Joo-Hyung Chae |
Module Implementation and Simulation of Timing Constraint Check Function of I2C Protocol Using Verilog. |
ICEIC |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Jie Chen, Bo Li 0123, Zhongjiang Yan, Mao Yang |
A System Verilog Based Networked Verification and Testing Method for Wireless Network Protocols on Chip. |
ICSPCC |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu |
Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. |
ICCAD |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren |
Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation. |
ICCAD |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Nicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, Renaud Gillon, Franco Fummi |
Verilog-A Implementation of Generic Defect Templates for Analog Fault Injection. |
ACM Great Lakes Symposium on VLSI |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Lekshmi S. Ajay, Sreenidhi Prabha Rajeev |
Comparative Analysis of Data Compression using Canonical Huffman and Golomb Rice Encoding in Verilog HDL and Implementation in FPGA. |
ICCCNT |
2023 |
DBLP DOI BibTeX RDF |
|
18 | S. Sasikala, P. Sivaranjani, Balambigai Subramanian, Keerthana M |
Verilog Implementation and Functional Verification of Hybrid Cryptography Algorithm. |
ICCCNT |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Pawel Szczepankowski, Wojciech Sleszynski, Tomasz Bajdecki |
A Direct Modulation for Matrix Converters Based on the One-Cycle Atomic Operation Developed in Verilog HDL. |
IEEE Trans. Ind. Electron. |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan 0001, Ramesh Karri, Brendan Dolan-Gavitt, Siddharth Garg |
Benchmarking Large Language Models for Automated Verilog RTL Code Generation. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Andreas Lööw |
A small, but important, concurrency problem in Verilog's semantics? (Work in progress). |
MEMOCODE |
2022 |
DBLP DOI BibTeX RDF |
|
18 | K. N. Raja Praveen, Gadug Sudhamsu |
Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers. |
IC3I |
2022 |
DBLP DOI BibTeX RDF |
|
18 | K. N. Raja Praveen, Gadug Sudhamsu |
Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers. |
IC3I |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Andrea La Gala, Lorenzo Stevenazzi, Elia A. Vallicelli, Mattia Tambaro, Stefano Vassanelli, Andrea Baschirotto, Marcello De Matteis |
Hodgkin-Huxley Verilog-A Electrical Neuron Membrane Model. |
ICECS 2022 |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Rafael Vieira, Fábio Passos, Ricardo Povoa, Ricardo Martins 0003, Nuno Horta, Jorge Guilherme, Nuno Lourenço 0003 |
Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling. |
SMACD |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Hye-Hyun Lee, Yeon-Seob Song, Kang-Yoon Lee |
Modeling of nano-scale PLL using Verilog HDL. |
ICTC |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Prianka Sengupta, Aakash Tyagi, Yiran Chen 0001, Jiang Hu |
How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning. |
ICCAD |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Francesco Tosoni 0002, Nicola Dall'Ora, Enrico Fraccaroli, Franco Fummi |
A Framework for Modeling and Concurrently Simulating Mechanical and Electrical Faults in Verilog-AMS. |
FDL |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Chenyu Huang, Huaien Gao, Yongfeng Zhong, Shuting Cai |
A High-Performance Bidirectional Compiler for conversion between SystemC and Verilog. |
HP3C |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Mihir Achyuta S. P, K. S. V. Pradyumna, Nithesh C, Dinah Ann Varughese, Sriadibhatla Sridevi |
Evaluating Winograd Algorithm for Convolution Neural Network using Verilog. |
iSES |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Xiangdong Wei, Xinfei Guo |
Beyond Verilog: Evaluating Chisel versus High-level Synthesis with Tiny Designs. |
ISQED |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Sadia Azam, Nicola Dall'Ora, Enrico Fraccaroli, Franco Fummi |
Functional Level Abstraction and Simulation of Verilog-AMS Piecewise Linear Models. |
ISQED |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Andreas Lööw |
Reconciling Verified-Circuit Development and Verilog Development. |
FMCAD |
2022 |
DBLP DOI BibTeX RDF |
|
18 | David Maldonado, Francisco Jiménez-Molinos, Juan Bautista Roldán, M. B. González, Francesca Campabadal |
An enhanced Verilog-A compact model for bipolar RRAMs including transient thermal effects and series resistance. |
DCIS |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Jean-Baptiste Kammerer, Maroua Garci, Achraf Kaïd, Fabrice Roqueta |
Multidomain Modeling for Reliability Evaluation of Devices and Microsystems Using Verilog-A. |
MIXDES |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Mike Brinson, Daniel Tomaszewski |
Advances in Qucs-S Schematic Capture for SPICE and Verilog-A Device Modelling and Circuit Simulation. |
MIXDES |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Shuangye Zhao, Youhua Wang, Yongshuang Luo |
System Verilog model design for AGC algorithm verification in SoC. |
ICCSIE |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Nicholas V. Giamblanco, Andrew Schmidt |
vlang: Mapping Verilog Netlists to Modern Technologies. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
18 | Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers |
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
18 | Bala Nagu Puppala, M. Uma Vani |
Design and implementation of a control unit of a micro grid in multi micro grid using Verilog systems. |
Int. J. Comput. Aided Eng. Technol. |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Angeliki Tataridou, Gérard Ghibaudo, Christoforos G. Theodorou |
VERILOR: A Verilog-A Model of Lorentzian Spectra for Simulating Trap-related Noise in CMOS Circuits. |
ESSDERC |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Nicola Dall'Ora, Enrico Fraccaroli, Sara Vinco, Franco Fummi |
Multi-Discipline Fault Modeling with Verilog-AMS. |
ICPS |
2021 |
DBLP DOI BibTeX RDF |
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