Search results for "x-by-wire"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Hua Xiang 0001, Kai-Yuan Chao, D. F. Wong 0001	ECO algorithms for removing overlaps between power rails and signal wires.	ICCAD	2002	DBLP DOI BibTeX RDF
36	Rony Kay, Lawrence T. Pileggi	EWA: efficient wiring-sizing algorithm for signal nets and clock nets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
36	Elmar Dilger, Thomas Führer, Bernd Müller	Distributed Fault-Tolerant and Safety-Critical Application in Vehicles - A Time-Triggered Approach.	SAFECOMP	1998	DBLP DOI BibTeX RDF
36	Zhaoyun Xing, Prithviraj Banerjee	A parallel algorithm for zero skew clock tree routing.	ISPD	1998	DBLP DOI BibTeX RDF
36	Reiji Suda, Ryotaro Kamikawai, Yasuo Wada, Willy Hioe, Mutsumi Hosoya, Eiichi Goto	QFP wiring problem-introduction and analytical considerations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
36	Shigetoshi Nakatake, Yoji Kajitani	Channel-driven global routing with consistent placement (extended abstract).	ICCAD	1994	DBLP DOI BibTeX RDF
35	Jens Lienig, Goeran Jerke, Thorsten Adler	Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	wire width, wire planning, current-driven routing, Design methodology, electromigration, detailed routing, current density, analog circuit design
35	Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang	A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
35	Marcel Brückner, Frank Deinzer, Joachim Denzler	Temporal Estimation of the 3d Guide-Wire Position Using 2d X-ray Images.	MICCAI (1)	2009	DBLP DOI BibTeX RDF
35	Jean-Pierre Merlet	Kinematics of the wire-driven parallel robot MARIONET using linear actuators.	ICRA	2008	DBLP DOI BibTeX RDF
35	Yong-sheng Cheng, Zhiqiang You, Jishun Kuang	Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction.	DELTA	2008	DBLP DOI BibTeX RDF	full scan testing, scan tree, routing complexity, test response data volume, design-for-testability
35	Ke Cao, Jiang Hu, Mosong Cheng	Wire Sizing and Spacing for Lithographic Printability and Timing Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
35	Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang	Novel wire density driven full-chip routing for CMP variation control.	ICCAD	2007	DBLP DOI BibTeX RDF
35	Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong	Minimizing wire length in floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
35	Thorsten Zerfaß, Sebastian Mues-Hinterwäller, Dietrich Paulus, Thomas Wittenberg	Live-Wire Segmentierung für hochaufgelöste Farbbilder mit optimierter Graphensuche.	Bildverarbeitung für die Medizin	2006	DBLP DOI BibTeX RDF
35	Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili	Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
35	Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong	Optimal redistribution of white space for wire length minimization.	ASP-DAC	2005	DBLP DOI BibTeX RDF
35	Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim	Wire congestion and thermal aware 3D global placement.	ASP-DAC	2005	DBLP DOI BibTeX RDF
35	Vinita V. Deodhar, Jeffrey A. Davis	Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
35	Dirk Stroobandt	A priori wire length distribution models with multiterminal nets.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
35	Sandeep Kumar Goel, Erik Jan Marinissen	Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization.	DATE	2003	DBLP DOI BibTeX RDF
35	Martijn T. Bennebroek	Validation of wire length distribution models on commercial designs.	SLIP	2003	DBLP DOI BibTeX RDF
35	Saman P. Amarasinghe	Defying the speed of light: : a spatially-aware compiler for wire-exposed architectures.	ASIA-PEPM	2002	DBLP DOI BibTeX RDF
35	Tanja Alderliesten, Maurits K. Konings, Wiro J. Niessen	Simulation of Guide Wire Propagation for Minimally Invasive Vascular Interventions.	MICCAI (2)	2002	DBLP DOI BibTeX RDF
35	Shirley A. M. Baert, Everine B. van de Kraats, Wiro J. Niessen	3D Guide Wire Reconstruction from Biplane Image Sequences for 3D Navigation in Endovascular Interventions.	MICCAI (1)	2002	DBLP DOI BibTeX RDF
35	Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky	Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
35	Mark A. Hillebrand, Thomas Schurger, Peter-Michael Seidel	How to Half Wire Lengths in the Layout of Cyclic Shifter.	VLSI Design	2001	DBLP DOI BibTeX RDF
35	Youxin Gao, Martin D. F. Wong	Wire-sizing optimization with inductance consideration using transmission-line model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
35	Youxin Gao, Martin D. F. Wong	Optimal shape function for a bidirectional wire under Elmore delay model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
35	Chris C. N. Chu, Martin D. F. Wong	Greedy wire-sizing is linear time.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
35	Masahiro Nagamatu, Shakeel Ismail, Torao Yanaru	A continuous valued iterative algorithm for wire routing problems.	KES (1)	1998	DBLP DOI BibTeX RDF
34	Z. W. Zhong	Overview of wire bonding using copper wire or insulated wire.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
33	Bahareh Fathi, Laleh Behjat, Logan M. Rakai	A pre-placement net length estimation technique for mixed-size circuits.	SLIP	2009	DBLP DOI BibTeX RDF	wire length estimation, placement, physical design, hypergraph clustering
33	Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou 0001	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.	ASP-DAC	2007	DBLP DOI BibTeX RDF	graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining
33	Jaskirat Singh, Sachin S. Sapatnekar	A fast algorithm for power grid design.	ISPD	2005	DBLP DOI BibTeX RDF	power grid design, wire pitch, optimization, locality, macromodel, bipartitioning
32	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Power-delay optimization in VLSI microprocessors by wire spacing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Wire spacing, power optimization, interconnect optimization, delay-optimization
32	Jin-Tai Yan, Zhi-Wei Chen	Redundant wire insertion for yield improvement.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	redundant wire, routing, yield
32	Moi-Tin Chew, Tatt-Huong Tham, Ye Chow Kuang	Electrical Power Monitoring System Using Thermochron Sensor and 1-Wire Communication Protocol.	DELTA	2008	DBLP DOI BibTeX RDF	electrical power monitoring, silicon themperature sensors, 1-wire data communication, datalogging
32	Jing Huang 0001, Mariam Momenzadeh, Fabrizio Lombardi	On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	processing by wire, emerging technologies, defect tolerance, QCA
32	Ya-Qing Zheng	Feedback Linearization Control of a Wire-Driven Parallel Support System in Wind Tunnels.	ISDA (3)	2006	DBLP DOI BibTeX RDF	wind tunnel, wire-driven, parallel support system, feedback linearization control
32	Bo Hu 0006, Malgorzata Marek-Sadowska	Wire length prediction based clustering and its application in placement.	DAC	2003	DBLP DOI BibTeX RDF	wire length prediction, clustering, placement
32	Paolo Gallina, Giulio Rosati, Aldo Rossi	3-d.o.f. Wire Driven Planar Haptic Interface.	J. Intell. Robotic Syst.	2001	DBLP DOI BibTeX RDF	wire driven systems, haptic interfaces, manipulability, polytopes
30	Tsung-Hsien Lee, Ting-Chi Wang	Robust layer assignment for via optimization in multi-layer global routing.	ISPD	2009	DBLP DOI BibTeX RDF	optimization, computer-aided design, global routing, via, layer assignment
30	Edmund Lee 0002, Guy Lemieux, Shahriar Mirabbasi	Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	routing design, FPGA, computer-aided design, interconnect design, FPGA interconnect
30	Chaomin Luo, Miguel F. Anjos, Anthony Vannelli	A nonlinear optimization methodology for VLSI fixed-outline floorplanning.	J. Comb. Optim.	2008	DBLP DOI BibTeX RDF	Circuit layout design, VLSI floorplanning, Facility layout, Combinatorial optimization, Global optimization, Convex programming
30	K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas	Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme.	ISVLSI	2007	DBLP DOI BibTeX RDF
30	Magdy A. El-Moursy, Eby G. Friedman	Power characteristics of inductive interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
30	Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif	A methodology for the simultaneous design of supply and signal networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
30	Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan 0005	Multilevel global placement with congestion control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
30	Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh	A Comparison of Asymptotically Scalable Superscalar Processors.	Theory Comput. Syst.	2002	DBLP DOI BibTeX RDF
30	Chin-Chih Chang, Jason Cong, David Zhigang Pan	Physical hierarchy generation with routing congestion control.	ISPD	2002	DBLP DOI BibTeX RDF	routing, interconnect, placement, hierarchy, congestion, physical, deep sub-micron
30	Steven L. Teig	The X architecture: not your father's diagonal wiring.	SLIP	2002	DBLP DOI BibTeX RDF
30	Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang	Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.	ISQED	2002	DBLP DOI BibTeX RDF	Interconnect-Driven Floorplanning, Performance Optimization
30	Paul Kartschoke, Stephen F. Geissler	Timing Driven Wiring on an Advanced Microprocessor.	DSD	2001	DBLP DOI BibTeX RDF
30	Youxin Gao, D. F. Wong 0001	A fast and accurate delay estimation method for buffered interconnects.	ASP-DAC	2001	DBLP DOI BibTeX RDF
30	Arifur Rahman, Rafael Reif	System-level performance evaluation of three-dimensional integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
29	Stuart Goose, Safia Djennane	WIRE3: Driving Around the Information Super-Highway.	Pers. Ubiquitous Comput.	2002	DBLP DOI BibTeX RDF	3-dimensional audio, Voice browsing, WIRE 3, Mobility, Document structure, WIRE
29	Jhe-Hong Wang, Chen-Hsien Fan, Chao-Chieh Lan	A compact rotational manipulator using shape memory alloy wire actuated flexures.	ICRA	2009	DBLP DOI BibTeX RDF
29	Saleem Abdul Hamid, Nabil Simaan	Design and synthesis of wire-actuated universal-joint wrists for surgical applications.	ICRA	2009	DBLP DOI BibTeX RDF
29	Juan Andrade-Cetto, Federico Thomas	A Wire-Based Active Tracker.	IEEE Trans. Robotics	2008	DBLP DOI BibTeX RDF
29	Fu-Wei Chen, Yi-Yu Liu	Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture.	DATE	2008	DBLP DOI BibTeX RDF
29	Basab Datta, Wayne P. Burleson	Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	sensor, interconnect, temperature, oscillator
29	Narender Hanchate, Nagarajan Ranganathan	Integrated Gate and Wire Sizing at Post Layout Level.	ISVLSI	2007	DBLP DOI BibTeX RDF
29	Yo-An Lim, Yongwon Seo 0003, Jeha Ryu	A Wearable 3-DOF Wire-driven Force Feedback Device.	WHC	2007	DBLP DOI BibTeX RDF
29	Jie-Hui Gong, Hui Zhang 0013, Yiwen Zhang, Jia-Guang Sun 0001	Converting hybrid wire-frames to B-rep models.	Symposium on Solid and Physical Modeling	2007	DBLP DOI BibTeX RDF	2-manifold, Möbius rule, model conversion, solid reconstruction, graph theory
29	Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava 0001, Miodrag Potkonjak	A statistical methodology for wire-length prediction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
29	Chuan Lin 0002, Hai Zhou 0001	Optimal wire retiming without binary search.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
29	Rudolf Ahlswede, Ning Cai 0001	Transmission, Identification and Common Randomness Capacities for Wire-Tape Channels with Secure Feedback from the Decoder.	GTIT-C	2006	DBLP DOI BibTeX RDF
29	Hitoshi Kino, Toshiaki Yahiro, Fumiaki Takemura, Tetsuya Morizono	Adaptive Position Control for Fully Constrained Parallel Wire Driven Systems.	IROS	2006	DBLP DOI BibTeX RDF
29	Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny	Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.	ISCAS	2006	DBLP DOI BibTeX RDF
29	Chuan Lin 0002, Hai Zhou 0001	Wire retiming as fixpoint computation.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
29	Ireri Ibarra-Alvarado, Richard K. Stobart, Rudi Lutz	Software Hazard Analysis for X-by-Wire Applications.	MoDELS (Satellite Events)	2005	DBLP DOI BibTeX RDF
29	Zein Salah, Jasmina Orman, Dirk Bartz	Live-Wire Revisited.	Bildverarbeitung für die Medizin	2005	DBLP DOI BibTeX RDF
29	Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy	Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
29	Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn	Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design.	IPDPS	2005	DBLP DOI BibTeX RDF
29	Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001	Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
29	Huiguang He, Jie Tian 0001, Yao Lin, Ke Lu	A New Interactive Segmentation Scheme Based on Fuzzy Affinity and Live-Wire.	FSKD (1)	2005	DBLP DOI BibTeX RDF
29	Cédric Wilwert, Françoise Simonot-Lion, Yeqiong Song, Françoise Simonot	Quantitative evaluation of the safety of X-by-Wire architecture subject to EMI perturbations.	ETFA	2005	DBLP DOI BibTeX RDF
29	Chuan Lin 0002, Hai Zhou 0001	Wire Retiming for System-on-Chip by Fixpoint Computation.	DATE	2004	DBLP DOI BibTeX RDF
29	Neil Steiner, Peter M. Athanas	An Alternate Wire Database for Xilinx FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
29	Rajeev Balasubramonian	Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures.	ICS	2004	DBLP DOI BibTeX RDF	communication-bound processors, effective address and memory dependence prediction, processor, data prefetch, distributed caches, clustered microarchitectures
29	V. Seth, Min Zhao 0001, Jiang Hu	Exploiting level sensitive latches in wire pipelining.	ICCAD	2004	DBLP DOI BibTeX RDF
29	Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava 0001, Miodrag Potkonjak	Wire-length prediction using statistical techniques.	ICCAD	2004	DBLP DOI BibTeX RDF
29	Chuan Lin 0002, Hai Zhou 0001	Optimal wire retiming without binary search.	ICCAD	2004	DBLP DOI BibTeX RDF
29	Mario R. Casu, Luca Macchiarulo	On-Chip Transparent Wire Pipelining.	ICCD	2004	DBLP DOI BibTeX RDF
29	Hitoshi Kino, Shigeru Yabe, Naoki Honjo, Sadao Kawamura	A Sensor-Actuator Map for Organization of Position Sensor Feedback Control for Multiple Links Structure / Wire Driven System.	AINA (2)	2004	DBLP DOI BibTeX RDF
29	Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia	A practical methodology for early buffer and wire resource allocation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
29	Li-Da Huang, Hung-Ming Chen, D. F. Wong 0001	Global Wire Bus Configuration with Minimum Delay Uncertainty.	DATE	2003	DBLP DOI BibTeX RDF
29	Eli Chiprout	Early electrical wire projections and implications.	SLIP	2003	DBLP DOI BibTeX RDF
29	Enrico Macii, Massimo Poncino, Sabino Salerno	Combining wire swapping and spacing for low-power deep-submicron buses.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	low-power design, physical design, crosstalk, bus encoding
29	Jai Thomas, Jayesh Todi, Asif Paranjpe	Simulation of manufacturing operations: optimization of operations in a steel wire manufacturing company.	WSC	2002	DBLP DOI BibTeX RDF
29	Srinivas Bodapati, Farid N. Najm	Prelayout estimation of individual wire lengths.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
29	Dirk Stroobandt	A priori system-level interconnect prediction: Rent's rule and wire length distribution models.	SLIP	2001	DBLP DOI BibTeX RDF
29	Kristina Ahlström, Jan Torin, Per Johannessen	Design Method for Conceptual Design of By-Wire Control: Two Case Studies.	ICECCS	2001	DBLP DOI BibTeX RDF
29	Youxin Gao, D. F. Wong 0001	Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model.	DATE	2000	DBLP DOI BibTeX RDF
29	Roumen Iankov, Albert Van Bael, Paul Van Houtte	Finite Element Simulation of Residual Stresses in Thermo-coupled Wire Drawing Process.	NAA	2000	DBLP DOI BibTeX RDF
29	Chris C. N. Chu, Martin D. F. Wong	An efficient and optimal algorithm for simultaneous buffer and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
29	Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong	Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
29	Zhong-Fang Jin, Jean-Jacques Laurin, Yvon Savaria, Pierre Garon	A new approach to analyze interconnect delays in RC wire models.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
29	Michael Gunzert, Andreas Nägele	Component-Based Development and Verification of Safety Critical Software for a Brake-by-Wire System with Synchronous Software Components.	PDSE	1999	DBLP DOI BibTeX RDF