Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
36 | Hua Xiang 0001, Kai-Yuan Chao, D. F. Wong 0001 |
ECO algorithms for removing overlaps between power rails and signal wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 67-74, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Rony Kay, Lawrence T. Pileggi |
EWA: efficient wiring-sizing algorithm for signal nets and clock nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1), pp. 40-49, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Elmar Dilger, Thomas Führer, Bernd Müller |
Distributed Fault-Tolerant and Safety-Critical Application in Vehicles - A Time-Triggered Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAFECOMP ![In: Computer Safety, Reliability and Security, 17th International Conference, SAFECOMP'98, Heidelberg, Germany, October 5-7, 1998, Proceedings, pp. 267-283, 1998, Springer, 3-540-65110-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Zhaoyun Xing, Prithviraj Banerjee |
A parallel algorithm for zero skew clock tree routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998, pp. 118-123, 1998, ACM, 1-58113-021-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Reiji Suda, Ryotaro Kamikawai, Yasuo Wada, Willy Hioe, Mutsumi Hosoya, Eiichi Goto |
QFP wiring problem-introduction and analytical considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1), pp. 48-56, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
36 | Shigetoshi Nakatake, Yoji Kajitani |
Channel-driven global routing with consistent placement (extended abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 350-355, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
35 | Jens Lienig, Goeran Jerke, Thorsten Adler |
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 372-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
wire width, wire planning, current-driven routing, Design methodology, electromigration, detailed routing, current density, analog circuit design |
35 | Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang |
A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2), pp. 193-206, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Marcel Brückner, Frank Deinzer, Joachim Denzler |
Temporal Estimation of the 3d Guide-Wire Position Using 2d X-ray Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICCAI (1) ![In: Medical Image Computing and Computer-Assisted Intervention - MICCAI 2009, 12th International Conference, London, UK, September 20-24, 2009, Proceedings, Part I, pp. 386-393, 2009, Springer, 978-3-642-04267-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Jean-Pierre Merlet |
Kinematics of the wire-driven parallel robot MARIONET using linear actuators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2008 IEEE International Conference on Robotics and Automation, ICRA 2008, May 19-23, 2008, Pasadena, California, USA, pp. 3857-3862, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Yong-sheng Cheng, Zhiqiang You, Jishun Kuang |
Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 308-313, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
full scan testing, scan tree, routing complexity, test response data volume, design-for-testability |
35 | Ke Cao, Jiang Hu, Mosong Cheng |
Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(12), pp. 1332-1340, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang |
Novel wire density driven full-chip routing for CMP variation control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 831-838, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong |
Minimizing wire length in floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1744-1753, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Thorsten Zerfaß, Sebastian Mues-Hinterwäller, Dietrich Paulus, Thomas Wittenberg |
Live-Wire Segmentierung für hochaufgelöste Farbbilder mit optimierter Graphensuche. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Bildverarbeitung für die Medizin ![In: Bildverarbeitung für die Medizin 2006, Algorithmen, Systeme, Anwendungen, Proceedings des Workshops vom 19. - 21. März 2006 in Hamburg, pp. 156-160, 2006, Springer, 978-3-540-32136-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili |
Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10), pp. 1637-1643, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong |
Optimal redistribution of white space for wire length minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 412-417, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim |
Wire congestion and thermal aware 3D global placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1131-1134, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Vinita V. Deodhar, Jeffrey A. Davis |
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 592-597, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Dirk Stroobandt |
A priori wire length distribution models with multiterminal nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(1), pp. 35-43, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Sandeep Kumar Goel, Erik Jan Marinissen |
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10738-10741, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Martijn T. Bennebroek |
Validation of wire length distribution models on commercial designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 41, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Saman P. Amarasinghe |
Defying the speed of light: : a spatially-aware compiler for wire-exposed architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIA-PEPM ![In: Proceedings of the ACM SIGPLAN ASIA-PEPM 2002, Asian Symposium on Partial Evaluation and Semantics-Based Program Manipulation, Aizu, Japan, September 12-14, 2002, pp. 70, 2002, ACM, 1-58113-458-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Tanja Alderliesten, Maurits K. Konings, Wiro J. Niessen |
Simulation of Guide Wire Propagation for Minimally Invasive Vascular Interventions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICCAI (2) ![In: Medical Image Computing and Computer-Assisted Intervention - MICCAI 2002, 5th International Conference, Tokyo, Japan, September 25-28, 2002, Proceedings, Part II, pp. 245-252, 2002, Springer, 3-540-44225-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Shirley A. M. Baert, Everine B. van de Kraats, Wiro J. Niessen |
3D Guide Wire Reconstruction from Biplane Image Sequences for 3D Navigation in Endovascular Interventions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICCAI (1) ![In: Medical Image Computing and Computer-Assisted Intervention - MICCAI 2002, 5th International Conference, Tokyo, Japan, September 25-28, 2002, Proceedings, Part I, pp. 404-410, 2002, Springer, 3-540-44224-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky |
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 580-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Mark A. Hillebrand, Thomas Schurger, Peter-Michael Seidel |
How to Half Wire Lengths in the Layout of Cyclic Shifter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 339-344, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Youxin Gao, Martin D. F. Wong |
Wire-sizing optimization with inductance consideration using transmission-line model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12), pp. 1759-1767, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Youxin Gao, Martin D. F. Wong |
Optimal shape function for a bidirectional wire under Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7), pp. 994-999, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Chris C. N. Chu, Martin D. F. Wong |
Greedy wire-sizing is linear time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4), pp. 398-405, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Masahiro Nagamatu, Shakeel Ismail, Torao Yanaru |
A continuous valued iterative algorithm for wire routing problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (1) ![In: Knowledge-Based Intelligent Electronic Systems, 2nd International Conference, KES 1998, Adelaide, South Australia, 21-23 April 1998, Proceedings, Part I, pp. 348-357, 1998, IEEE. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Z. W. Zhong |
Overview of wire bonding using copper wire or insulated wire. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 51(1), pp. 4-12, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
33 | Bahareh Fathi, Laleh Behjat, Logan M. Rakai |
A pre-placement net length estimation technique for mixed-size circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 45-52, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
wire length estimation, placement, physical design, hypergraph clustering |
33 | Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou 0001 |
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 920-925, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining |
33 | Jaskirat Singh, Sachin S. Sapatnekar |
A fast algorithm for power grid design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 70-77, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
power grid design, wire pitch, optimization, locality, macromodel, bipartitioning |
32 | Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer |
Power-delay optimization in VLSI microprocessors by wire spacing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(4), pp. 55:1-55:28, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Wire spacing, power optimization, interconnect optimization, delay-optimization |
32 | Jin-Tai Yan, Zhi-Wei Chen |
Redundant wire insertion for yield improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 409-412, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
redundant wire, routing, yield |
32 | Moi-Tin Chew, Tatt-Huong Tham, Ye Chow Kuang |
Electrical Power Monitoring System Using Thermochron Sensor and 1-Wire Communication Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 549-554, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
electrical power monitoring, silicon themperature sensors, 1-wire data communication, datalogging |
32 | Jing Huang 0001, Mariam Momenzadeh, Fabrizio Lombardi |
On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(2-3), pp. 163-174, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
processing by wire, emerging technologies, defect tolerance, QCA |
32 | Ya-Qing Zheng |
Feedback Linearization Control of a Wire-Driven Parallel Support System in Wind Tunnels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISDA (3) ![In: Proceedings of the Sixth International Conference on Intelligent Systems Design and Applications (ISDA 2006), October 16-18, 2006, Jinan, China, pp. 9-13, 2006, IEEE Computer Society, 0-7695-2528-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
wind tunnel, wire-driven, parallel support system, feedback linearization control |
32 | Bo Hu 0006, Malgorzata Marek-Sadowska |
Wire length prediction based clustering and its application in placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 800-805, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
wire length prediction, clustering, placement |
32 | Paolo Gallina, Giulio Rosati, Aldo Rossi |
3-d.o.f. Wire Driven Planar Haptic Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 32(1), pp. 23-36, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
wire driven systems, haptic interfaces, manipulability, polytopes |
30 | Tsung-Hsien Lee, Ting-Chi Wang |
Robust layer assignment for via optimization in multi-layer global routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 159-166, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimization, computer-aided design, global routing, via, layer assignment |
30 | Edmund Lee 0002, Guy Lemieux, Shahriar Mirabbasi |
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(1), pp. 57-76, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
routing design, FPGA, computer-aided design, interconnect design, FPGA interconnect |
30 | Chaomin Luo, Miguel F. Anjos, Anthony Vannelli |
A nonlinear optimization methodology for VLSI fixed-outline floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comb. Optim. ![In: J. Comb. Optim. 16(4), pp. 378-401, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Circuit layout design, VLSI floorplanning, Facility layout, Combinatorial optimization, Global optimization, Convex programming |
30 | K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas |
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 401-408, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Magdy A. El-Moursy, Eby G. Friedman |
Power characteristics of inductive interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(12), pp. 1295-1306, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif |
A methodology for the simultaneous design of supply and signal networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12), pp. 1614-1624, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan 0005 |
Multilevel global placement with congestion control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4), pp. 395-409, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh |
A Comparison of Asymptotically Scalable Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theory Comput. Syst. ![In: Theory Comput. Syst. 35(2), pp. 129-150, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Chin-Chih Chang, Jason Cong, David Zhigang Pan |
Physical hierarchy generation with routing congestion control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 36-41, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
routing, interconnect, placement, hierarchy, congestion, physical, deep sub-micron |
30 | Steven L. Teig |
The X architecture: not your father's diagonal wiring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 33-37, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang |
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 523-528, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Interconnect-Driven Floorplanning, Performance Optimization |
30 | Paul Kartschoke, Stephen F. Geissler |
Timing Driven Wiring on an Advanced Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 408-413, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Youxin Gao, D. F. Wong 0001 |
A fast and accurate delay estimation method for buffered interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 533-538, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Arifur Rahman, Rafael Reif |
System-level performance evaluation of three-dimensional integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(6), pp. 671-678, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Stuart Goose, Safia Djennane |
WIRE3: Driving Around the Information Super-Highway. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Pers. Ubiquitous Comput. ![In: Pers. Ubiquitous Comput. 6(3), pp. 164-175, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
3-dimensional audio, Voice browsing, WIRE 3, Mobility, Document structure, WIRE |
29 | Jhe-Hong Wang, Chen-Hsien Fan, Chao-Chieh Lan |
A compact rotational manipulator using shape memory alloy wire actuated flexures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2009 IEEE International Conference on Robotics and Automation, ICRA 2009, Kobe, Japan, May 12-17, 2009, pp. 550-555, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Saleem Abdul Hamid, Nabil Simaan |
Design and synthesis of wire-actuated universal-joint wrists for surgical applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2009 IEEE International Conference on Robotics and Automation, ICRA 2009, Kobe, Japan, May 12-17, 2009, pp. 1807-1813, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Juan Andrade-Cetto, Federico Thomas |
A Wire-Based Active Tracker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Robotics ![In: IEEE Trans. Robotics 24(3), pp. 642-651, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Fu-Wei Chen, Yi-Yu Liu |
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 796-799, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Basab Datta, Wayne P. Burleson |
Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 41-46, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
sensor, interconnect, temperature, oscillator |
29 | Narender Hanchate, Nagarajan Ranganathan |
Integrated Gate and Wire Sizing at Post Layout Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 225-232, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Yo-An Lim, Yongwon Seo 0003, Jeha Ryu |
A Wearable 3-DOF Wire-driven Force Feedback Device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WHC ![In: Second Joint EuroHaptics Conference and Symposium on Haptic Interfaces for Virtual Environment and Teleoperator Systems, WHC 2007, Tsukuba, Japan, March 22-24, 2007, pp. 379-384, 2007, IEEE Computer Society, 978-0-7695-2738-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Jie-Hui Gong, Hui Zhang 0013, Yiwen Zhang, Jia-Guang Sun 0001 |
Converting hybrid wire-frames to B-rep models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Symposium on Solid and Physical Modeling ![In: Proceedings of the 2007 ACM Symposium on Solid and Physical Modeling, Beijing, China, June 4-6, 2007, pp. 283-289, 2007, ACM, 978-1-59593-666-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
2-manifold, Möbius rule, model conversion, solid reconstruction, graph theory |
29 | Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava 0001, Miodrag Potkonjak |
A statistical methodology for wire-length prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7), pp. 1327-1336, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Chuan Lin 0002, Hai Zhou 0001 |
Optimal wire retiming without binary search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1577-1588, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Rudolf Ahlswede, Ning Cai 0001 |
Transmission, Identification and Common Randomness Capacities for Wire-Tape Channels with Secure Feedback from the Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GTIT-C ![In: General Theory of Information Transfer and Combinatorics, pp. 258-275, 2006, Springer, 3-540-46244-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Hitoshi Kino, Toshiaki Yahiro, Fumiaki Takemura, Tetsuya Morizono |
Adaptive Position Control for Fully Constrained Parallel Wire Driven Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2006 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2006, October 9-15, 2006, Beijing, China, pp. 79-84, 2006, IEEE, 1-4244-0258-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny |
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Chuan Lin 0002, Hai Zhou 0001 |
Wire retiming as fixpoint computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(12), pp. 1340-1348, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Ireri Ibarra-Alvarado, Richard K. Stobart, Rudi Lutz |
Software Hazard Analysis for X-by-Wire Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MoDELS (Satellite Events) ![In: Satellite Events at the MoDELS 2005 Conference, MoDELS 2005 International Workshops, Doctoral Symposium, Educators Symposium, Montego Bay, Jamaica, October 2-7, 2005, Revised Selected Papers, pp. 341-342, 2005, Springer, 3-540-31780-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Zein Salah, Jasmina Orman, Dirk Bartz |
Live-Wire Revisited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Bildverarbeitung für die Medizin ![In: Bildverarbeitung für die Medizin 2005, Algorithmen - Systeme - Anwendungen, Proceedings des Workshops vom 13.-15. März 2005 in Heidelberg, pp. 158-162, 2005, Springer, 3-540-25052-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy |
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 28-39, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn |
Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001 |
Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 113-116, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Huiguang He, Jie Tian 0001, Yao Lin, Ke Lu |
A New Interactive Segmentation Scheme Based on Fuzzy Affinity and Live-Wire. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSKD (1) ![In: Fuzzy Systems and Knowledge Discovery, Second International Conference, FSKD 2005, Changsha, China, August 27-29, 2005, Proceedings, Part I, pp. 436-443, 2005, Springer, 3-540-28312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Cédric Wilwert, Françoise Simonot-Lion, Yeqiong Song, Françoise Simonot |
Quantitative evaluation of the safety of X-by-Wire architecture subject to EMI perturbations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETFA ![In: Proceedings of 10th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2005, September 19-22, 2005, Catania, Italy, 2005, IEEE, 0-7803-9401-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Chuan Lin 0002, Hai Zhou 0001 |
Wire Retiming for System-on-Chip by Fixpoint Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1092-1097, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Neil Steiner, Peter M. Athanas |
An Alternate Wire Database for Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 336-337, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Rajeev Balasubramonian |
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 18th Annual International Conference on Supercomputing, ICS 2004, Saint Malo, France, June 26 - July 01, 2004, pp. 326-335, 2004, ACM, 1-58113-839-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
communication-bound processors, effective address and memory dependence prediction, processor, data prefetch, distributed caches, clustered microarchitectures |
29 | V. Seth, Min Zhao 0001, Jiang Hu |
Exploiting level sensitive latches in wire pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 283-290, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava 0001, Miodrag Potkonjak |
Wire-length prediction using statistical techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 702-705, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Chuan Lin 0002, Hai Zhou 0001 |
Optimal wire retiming without binary search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 452-458, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Mario R. Casu, Luca Macchiarulo |
On-Chip Transparent Wire Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 160-167, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Hitoshi Kino, Shigeru Yabe, Naoki Honjo, Sadao Kawamura |
A Sensor-Actuator Map for Organization of Position Sensor Feedback Control for Multiple Links Structure / Wire Driven System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA (2) ![In: 18th International Conference on Advanced Information Networking and Applications (AINA 2004), 29-31 March 2004, Fukuoka, Japan, pp. 551-554, 2004, IEEE Computer Society, 0-7695-2051-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia |
A practical methodology for early buffer and wire resource allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5), pp. 573-583, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Li-Da Huang, Hung-Ming Chen, D. F. Wong 0001 |
Global Wire Bus Configuration with Minimum Delay Uncertainty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10050-10055, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Eli Chiprout |
Early electrical wire projections and implications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 95, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Enrico Macii, Massimo Poncino, Sabino Salerno |
Combining wire swapping and spacing for low-power deep-submicron buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 198-202, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low-power design, physical design, crosstalk, bus encoding |
29 | Jai Thomas, Jayesh Todi, Asif Paranjpe |
Simulation of manufacturing operations: optimization of operations in a steel wire manufacturing company. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 34th Winter Simulation Conference: Exploring New Frontiers, San Diego, California, USA, December 8-11, 2002, pp. 1151-1156, 2002, WSC, 0-7803-7615-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Srinivas Bodapati, Farid N. Najm |
Prelayout estimation of individual wire lengths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 943-958, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Dirk Stroobandt |
A priori system-level interconnect prediction: Rent's rule and wire length distribution models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 3-21, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Kristina Ahlström, Jan Torin, Per Johannessen |
Design Method for Conceptual Design of By-Wire Control: Two Case Studies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 7th International Conference on Engineering of Complex Computer Systems (ICECCS 2001), 11-13 June 2001, Skövde, Sweden, pp. 133-143, 2001, IEEE Computer Society, 0-7695-1159-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Youxin Gao, D. F. Wong 0001 |
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 512-516, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Roumen Iankov, Albert Van Bael, Paul Van Houtte |
Finite Element Simulation of Residual Stresses in Thermo-coupled Wire Drawing Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAA ![In: Numerical Analysis and Its Applications, Second International Conference, NAA 2000, Rousse, Bulgaria, June 11-15, 2000, Revised Papers, pp. 423-430, 2000, Springer, 3-540-41814-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Chris C. N. Chu, Martin D. F. Wong |
An efficient and optimal algorithm for simultaneous buffer and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9), pp. 1297-1304, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong |
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7), pp. 1014-1025, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Zhong-Fang Jin, Jean-Jacques Laurin, Yvon Savaria, Pierre Garon |
A new approach to analyze interconnect delays in RC wire models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 246-249, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Michael Gunzert, Andreas Nägele |
Component-Based Development and Verification of Safety Critical Software for a Brake-by-Wire System with Synchronous Software Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDSE ![In: International Symposium on Software Engineering for Parallel and Distributed Systems, PDSE 1999, Los Angeles, California, USA, May 17-18, 1999, pp. 134-, 1999, IEEE Computer Society, 0-7695-0191-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|