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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 592 occurrences of 418 keywords
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Results
Found 2140 publication records. Showing 2129 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
25 | Steve Shao-Shiun Chung |
A charge-based capacitance model of short-channel MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(1), pp. 1-7, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
25 | Lawrence T. Pillage, Xueqing Huang, Ronald A. Rohrer |
AWEsim: Asymptotic Waveform Evaluation for Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 634-637, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
24 | Rossella Blatt, Andrea Bonarini, Elisa Calabró, Matteo Della Torre, Matteo Matteucci, Ugo Pastorino |
Fuzzy k -NN Lung Cancer Identification by an Electronic Nose. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WILF ![In: Applications of Fuzzy Sets Theory, 7th International Workshop on Fuzzy Logic and Applications, WILF 2007, Camogli, Italy, July 7-10, 2007, Proceedings, pp. 261-268, 2007, Springer, 978-3-540-73399-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
E-Nose, Olfactory Signal, Fuzzy k-NN, MOS Sensor Array, Pattern Classification, Electronic Nose, Lung Cancer |
24 | Yukiya Miura |
Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 411-423, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MOS transistors, operation-region model, X-Y zoning method, fault diagnosis, analog circuits |
24 | Sofiene Jelassi, Habib Youssef |
Adaptive playback algorithm for interactive audio streaming over wireless ad-hoc networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the International Conference on Wireless Communications and Mobile Computing, IWCMC 2006, Vancouver, British Columbia, Canada, July 3-6, 2006, pp. 218-226, 2006, ACM, 1-59593-306-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
quality of service (QoS), mobile ad-hoc NETworks (MANET), streaming, mean opinion scores (MOS) |
24 | Dongming Wang 0001, Bican Xia |
Stability analysis of biological systems with real solution classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSAC ![In: Symbolic and Algebraic Computation, International Symposium ISSAC 2005, Beijing, China, July 24-27, 2005, Proceedings, pp. 354-361, 2005, ACM, 1-59593-095-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Cdc2-cyclin B/Wee1, Mos/MEK/p42 MAPK cascade, solution classification, stability, differential equations, equilibrium, polynomial system, biological network, real root |
24 | Nabil J. Sarhan, Chita R. Das |
Caching and Scheduling in NAD-Based Multimedia Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 15(10), pp. 921-933, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Distributed Interval Caching (DIC), Multimedia-on-Demand (MOD), Multi-Objective Scheduling (MOS), Network-Attached Disks (NAD), Batching, Video-on-Demand (VOD) |
24 | Christian Schaefer, Thomas Enderes, Hartmut Ritter, Martina Zitterbart |
Subjective quality assessment for multiplayer real-time games. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NETGAMES ![In: Proceedings of the 1st Workshop on Network and System Support for Games, NETGAMES 2002, Braunschweig, Germany, April 16-17, 2002, 2003, pp. 74-78, 2002, ACM, 1-58113-493-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
gaming, UMTS, mean opinion score (MOS), 3G networks |
24 | Simon Jolly, Atanas N. Parashkevov, Tim McDougall |
Automated equivalence checking of switch level circuits . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 299-304, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
MOS circuits, custom design, switch level analysis, formal verification, VLSI design, equivalence checking |
24 | Stefano Serra Capizzano, Cristina Tablino Possio |
Preliminary Remarks on Multigrid Methods for Circulant Matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAA ![In: Numerical Analysis and Its Applications, Second International Conference, NAA 2000, Rousse, Bulgaria, June 11-15, 2000, Revised Papers, pp. 152-159, 2000, Springer, 3-540-41814-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
two-grid and multigrid iterations, AMS(MOS) Subject Classification: 65F10, 65F15, Circulant matrices |
24 | Georg Heinig |
Fast and Superfast Algorithms for Hankel-Like Matrices Related to Orthogonal Polynominals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAA ![In: Numerical Analysis and Its Applications, Second International Conference, NAA 2000, Rousse, Bulgaria, June 11-15, 2000, Revised Papers, pp. 385-392, 2000, Springer, 3-540-41814-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Hankel matrix, fast algorithm AMS(MOS) Subject Classification: 47B35, 15A09, orthogonal polynomials, 15A23 |
24 | Siu-Long Lei, Xiao-Qing Jin |
Strang-Type Preconditioners for Differential-Algebraic Equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAA ![In: Numerical Analysis and Its Applications, Second International Conference, NAA 2000, Rousse, Bulgaria, June 11-15, 2000, Revised Papers, pp. 505-512, 2000, Springer, 3-540-41814-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
GMRES method, Strang-type block-circulant preconditioner, clustered spectrum, BVMs AMS(MOS) Subject Classifications: 65F10, 65N22, convergence rate, ODEs, 65F15, 65L05, 15A18, DAEs |
24 | Pierluigi Amodio |
Spectral Properties of Circulant Band Matrices Arising in ODE Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAA ![In: Numerical Analysis and Its Applications, Second International Conference, NAA 2000, Rousse, Bulgaria, June 11-15, 2000, Revised Papers, pp. 10-17, 2000, Springer, 3-540-41814-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
linear multistep methods AMS(MOS) subject classification: 65F10, ordinary differential equations, 65F15, 65L20, 65L05, circulant matrices |
24 | Liam P. Maguire, T. Martin McGinnity, L. J. McDaid |
From a Fuzzy Flip-Flop to a MVL Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 294-299, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
MVL flip-flop, MOS implementation, fuzzy reasoning |
24 | Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama |
Quaternary Universal-Literal CAM for Cellular Logic Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 224-229, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
content addressable memory(CAM), universal literal, threshold programming, floating-gate MOS transistor, multiple-valued logic |
24 | A. B. Bhattacharyya, Ram Singh Rana, S. K. Guha, Rajendar Bahl, R. Anand, M. J. Zarabi, P. A. Govindacharyulu, U. Gupta, V. Mohan, Jatin Roy, Amul Atri |
A micropower analog hearing aid on low voltage CMOS digital process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 85-89, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
differential amplifiers, automatic gain control, micropower analog hearing aid, low voltage CMOS digital process, adaptive biasing, MOS translinear loop circuit, degenerating linearising resistor, input differential stage, AGC block, conversion efficiency, 3 micron, 1.0 V, power consumption, CMOS analogue integrated circuits, hearing aids |
24 | Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama |
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 64-71, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic |
24 | Anirudh Devgan |
Accurate device modeling techniques for efficient timing simulation of integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 138-143, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
device modeling techniques, Fast-to-evaluate and Accurate Simplified Transistor, aggressive MOS technologies, FAST models, timing, AGES, circuit analysis computing, integrated circuits, circuit simulators, transient analysis, transistors, transistor, transient simulator, timing simulation, timing simulator, electronic engineering computing, semiconductor device models |
24 | William C. Athas, Nestoras Tzartzanis |
Energy recovery for low-power CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 415-429, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
bootstrap circuits, low-power CMOS, energy-recovery techniques, voltage swing, transition time, MOS device parameters, adder designs, VLSI, mathematical model, bootstrapping, adders, CMOS logic circuits, CMOS logic circuits, power dissipation, integrated circuit modelling, SOI |
22 | Antonio LaTorre, Santiago Muelas, José María Peña Sánchez |
Benchmarking a MOS-based algorithm on the BBOB-2010 noisy function testbed. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO (Companion) ![In: Genetic and Evolutionary Computation Conference, GECCO 2010, Proceedings, Portland, Oregon, USA, July 7-11, 2010, Companion Material, pp. 1725-1730, 2010, ACM, 978-1-4503-0073-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
IPOP-CMA-ES, benchmarking of algorithms, multiple offspring sampling, differential evolution, black-box optimization, continuous optimization |
22 | Mahsa Tahermaram, Mahdi Vadizadeh, A. Eslamzadeh, Morteza Fathipour |
Employing work function enginnering and asymmetric gate oxide in nano-scale source-heterojunction-MOS-transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 196-201, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Andreas Saul |
Simple Optimization Algorithm for MOS-Based Resource Assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 67th IEEE Vehicular Technology Conference, VTC Spring 2008, 11-14 May 2008, Singapore, pp. 1766-1770, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Toru Fujimura, Shigetoshi Nakatake |
Transistor-level programmable MOS analog IC with body biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 153-156, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Varun Aggarwal, Una-May O'Reilly |
Simulation-based reusable posynomial models for MOS transistor parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 69-74, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Xavier Redondo, Jofre Pallares, Francisco Serra-Graells |
A 1.2V 130µA 10-bit MOS-Only Log-Domain Sigma Delta Modulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 17-20, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Olivier Thomas, Marina Reyboz, Marc Belleville |
Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2778-2781, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Stéphane Badel, Yusuf Leblebici |
Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1871-1874, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Ramón González Carvajal, Juan Antonio Gómez Galán, Antonio Jesús Torralba Silgado, Clara Isabel Luján-Martínez, Jaime Ramírez-Angulo, Antonio J. López-Martín |
A Very Linear OTA with V-I Conversion based on Quasi-Floating MOS Resistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 473-476, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Osman Musa Abdulkarim, Maitham Shams |
A symmetric mos current-mode logic universal gate for high speed applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 212-215, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MCML, SCL, VLSI, ASIC |
22 | Rossella Blatt, Andrea Bonarini, Elisa Calabró, Matteo Della Torre, Matteo Matteucci, Ugo Pastorino |
Lung Cancer Identification by an Electronic Nose based on an Array of MOS Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2007, Celebrating 20 years of neural networks, Orlando, Florida, USA, August 12-17, 2007, pp. 1423-1428, 2007, IEEE, 978-1-4244-1379-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Masaaki Fukuhara, Masahiro Yoshida |
Power consumption of a Hamming distance search CAM using neuron MOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Benjamas Tongprasit, Tadashi Shibata |
Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Kuan Zhou, Yifei Luo, Sizhong Chen, Allen Drake, John F. McDonald 0001, Tong Zhang 0002 |
Triple-rail MOS current mode logic for high-speed self-timed pipeline applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Sangho Shin, Kwyro Lee, Sung-Mo Kang |
Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Dong-Shong Liang, Yaw-Hwang Chen, Chun-Min Wen, Chun-Da Tu, Kwang-Jow Gan, Cher-Shiung Tsai |
The Design of MOS-NDR-Based Cellular Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2006, part of the IEEE World Congress on Computational Intelligence, WCCI 2006, Vancouver, BC, Canada, 16-21 July 2006, pp. 1033-1035, 2006, IEEE, 0-7803-9490-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil |
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 188-193, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
MOS current mode circuits: analysis, design, and variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(8), pp. 885-898, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Tin Wai Kwan, Maitham Shams |
Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 23-32, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Tomoyuki Nakayama, Toshihiko Yamasaki, Tadashi Shibata |
A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5365-5368, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Di Long, Xianlong Hong, Sheqin Dong |
Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2999-3002, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Paula López 0001, Matthias Oberst, Harald Neubauer, Johann Hauer, Diego Cabello |
Performance analysis of high-speed MOS transistors with different layout styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3688-3691, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Shahnam Khabiri, Maitham Shams |
A mathematical programming approach to designing MOS current-mode logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2425-2428, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Tin Wai Kwan, Maitham Shams |
Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 301-306, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Stefan Dilhaire, Stéphane Grauby, Sébastien Jorez, Wilfrid Claeys |
Strain energy imaging of a power MOS transistor using speckle interferometry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 53(2), pp. 293-296, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Xiang Lu, Zhuo Li 0001, Wangqi Qiu, D. M. H. Walker, Weiping Shi |
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA, pp. 97-102, 2004, IEEE Computer Society, 0-7695-2320-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim |
Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada, pp. 198-203, 2004, IEEE Computer Society, 0-7695-2130-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Tomoyuki Nakayama, Toshihiko Yamasaki, Tadashi Shibata |
Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 425-428, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
Design and optimization of MOS current mode logic for parameter variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 33-38, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
MCML, optimization, design, automation, variation, technology scaling |
22 | Patricia Giacomelli, Márcio C. Schneider, Carlos Galup-Montoro |
MOSVIEW: A Graphical Tool for MOS Analog Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 43-44, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Stephen Tang, Siva G. Narendra, Vivek De |
Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 199-204, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
bandgap reference, process and temperature compensation, reference current, CMOS |
22 | Alfredo Arnaud, Carlos Galup-Montoro |
Simple noise formulas for MOS analog design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 189-192, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Carlos Sánchez-López, Alejandro Díaz-Sánchez, Esteban Tlelo-Cuautle |
Analog implementation of MOS-translinear Morlet Wavelets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 393-396, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Adrian Leuciuc, Yi Zhang |
A highly linear low-voltage MOS transconductor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 735-738, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Mohab Anis, Mohamed I. Elmasry |
Self-timed MOS current mode logic for digital applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 113-116, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Tae-young Oh, Zhiping Yu, Robert W. Dutton |
AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 326-330, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
AC analysis, thin gate oxide, quantum mechanical correction, threshold voltage shift, transconductace, channel length reduction, density-gradient, quantum confinement, PROPHET, channel doping, transport theory, device parameter extraction, effective oxide thickness, capacitance |
22 | Francisco Serra-Graells |
All-MOS subthreshold log filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 137-140, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Mahmoud Al-Nsour, Hoda S. Abdel-Aty-Zohdy |
MOS fully analog reinforcement neural network chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 237-240, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Jason M. Musicer, Jan M. Rabaey |
MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 102-107, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
CORDIC, digital logic, current mode logic, low-energy design |
22 | Mineo Kaneko |
Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 262-265, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti |
Statistical modeling of MOS transistor mismatch based on the parameters' autocorrelation function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 222-225, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | R. Brannen, Hassan O. Elwan, Mohammed Ismail 0001 |
A simple low-voltage all MOS linear-dB AGC/multiplier circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 318-321, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj |
Modeling of accumulation MOS capacitors for analog design in digital VLSI processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 202-205, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Dominique Python, Christian C. Enz |
An antialiasing filter using complementary MOS transconductors biased in the triode region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 184-187, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Tetsuya Uemura, Pinaki Mazumder |
Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 158-161, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Steve H. Jen, Bing J. Sheu |
A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2), pp. 169-172, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Massimo Conti, Simone Orcioni, Claudio Turchetti, Giovanni Soncini, Nicola Zorzi |
Analytical device modeling for MOS analog IC's based on regularization and Bayesian estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11), pp. 1309-1323, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
22 | Sudhir M. Gowda, Bing J. Sheu |
BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9), pp. 1166-1170, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury |
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4), pp. 482-493, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Aleksandra Pavasovic, Andreas G. Andreou, Charles R. Westgate |
Characterization of subthreshold MOS mismatch in transistors for VLSI systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 8(1), pp. 75-85, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee |
Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 190-194, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Eric Felt, Amit Narayan, Alberto L. Sangiovanni-Vincentelli |
Measurement and modeling of MOS transistor current mismatch in analog IC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 272-277, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Ferenc Kovács, Gábor Hosszú |
A proposed method for dynamic fitting of MOS model parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10), pp. 1503-1507, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Denis Martin, Nicholas C. Rumin |
Delay prediction from resistance-capacitance models of general MOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7), pp. 997-1003, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin |
A recursive technique for computing delays in series-parallel MOS transistor circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5), pp. 589-595, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
22 | Richard Booth 0003, Marvin White |
Simulation of a MOS transistor with spatially nonuniform channel parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12), pp. 1354-1357, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Farid N. Najm, Ibrahim N. Hajj |
The complexity of fault detection in MOS VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9), pp. 995-1001, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | D. Patrick, Colin Lyden |
An event-driven transient simulation algorithm for MOS and bipolar circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 230-234, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Paul J. V. Vandeloo, Willy M. C. Sansen |
Modeling of the MOS transistor for high frequency analog design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(7), pp. 713-723, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Mehmet A. Cirit |
The Meyer model revisited: why is charge not conserved? [MOS transistor]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(10), pp. 1033-1037, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Chung-Ping Wan, Bing J. Sheu |
Temperature dependence modeling for MOS VLSI circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(10), pp. 1065-1073, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Kyeongsoon Cho, Randal E. Bryant |
Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 418-423, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
22 | A. Salz, Mark Horowitz |
IRSIM: An Incremental MOS Switch-Level Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 173-178, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Genhong Ruan, Jirí Vlach, James A. Barby |
Current-limited switch-level timing simulator for MOS logic networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6), pp. 659-667, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
22 | Bing J. Sheu, Wen-Jay Hsu, P. K. Ko |
An MOS transistor charge model for VLSI design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4), pp. 520-527, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
22 | Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman |
SLS-a fast switch-level simulator [for MOS]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8), pp. 838-849, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
22 | Dale E. Hocevar, Paul F. Cox, Ping Yang 0001 |
Parametric yield optimization for MOS circuit blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6), pp. 645-658, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
22 | Foong-Charn Chang, Chin-Fu Chen, Prasad Subramaniam |
An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 282-287, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
22 | Dan Adler |
A Dynamically-Directed Switch Model for MOS Logic Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 506-511, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
22 | William S. Beckett |
MOS circuit models in Network C. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 171-178, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
C |
22 | Luís M. Vidigal, Sani R. Nassif, Stephen W. Director |
CINNAMON: coupled integration and nodal analysis of MOS networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 179-185, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
22 | Gabriele Saucier, Ghislaine Thuau |
Systematic and optimized layout of MOS cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 53-61, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
22 | Tak-Kwong Ng, S. Lennart Johnsson |
Generation of layouts from MOS circuit schematics: a graph theoretic approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 39-45, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
22 | Thomas J. Schaefer |
A transistor-level logic-with-timing simulator for MOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 762-765, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
22 | Mark D. Matson |
Macromodeling of digital MOS VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 141-151, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
17 | Maxim Graubner, Parag S. Mogre, Ralf Steinmetz, Thorsten Lorenzen |
A new QoE model and evaluation method for broadcast audio contribution over IP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOSSDAV ![In: Network and Operating System Support for Digital Audio and Video, 20th International Workshop, NOSSDAV 2010, Amsterdam, The Netherlands, June 2-4, 2010, Proceedings, pp. 57-62, 2010, ACM, 978-1-4503-0043-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
acip, aoip, audio communication, mos, peaq, pemo-q, pqos, qoe, wb-pesq, user satisfaction, quality of experience, qos, e-model |
17 | Chen-Chi Wu, Kuan-Ta Chen, Chun-Ying Huang, Chin-Laung Lei |
An empirical evaluation of VoIP playout buffer dimensioning in Skype, Google talk, and MSN Messenger. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOSSDAV ![In: Network and Operating System Support for Digital Audio and Video, 19th International Workshop, NOSSDAV 2009, Williamsburg, VA, USA. June 3-5, 2009, Proceedings, pp. 97-102, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
mos, VoIP, user satisfaction, quality of experience, e-model, pesq |
17 | Abiodun Iwayemi, Chi Zhou |
VoIP Performance in Multi-radio Mobile Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009, Chengdu, Sichuan, China, 10-12 August 2009, pp. 354-360, 2009, IEEE Computer Society, 978-0-7695-3747-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Mobile VoIP, WiFi, HSDPA, MOS |
17 | Marc Sullivan, James Pratt, Philip T. Kortum |
Practical issues in subjective video quality evaluation: human factors vs. psychophysical image quality evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UXTV ![In: Proceeding of the 1st International Conference on Designing Interactive User Experiences for TV and Video, UXTV 2008, Silicon Valley, California, USA, October 22-24, 2008, pp. 1-4, 2008, 978-1-60558-100-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
mos, subjective video quality |
17 | Adil Raja, Colin Flanagan |
Real-Time, Non-intrusive Speech Quality Estimation: A Signal-Based Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroGP ![In: Genetic Programming, 11th European Conference, EuroGP 2008, Naples, Italy, March 26-28, 2008. Proceedings, pp. 37-48, 2008, Springer, 978-3-540-78670-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Non-Intrusive, Signal-based, MOS, GP |
17 | Il-Gu Jung, Eun-Jin Ko, Hyun-Chul Kang, Gilhaeng Lee |
Voice quality measurement system for telephone service. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSTST ![In: CSTST 2008: Proceedings of the 5th International Conference on Soft Computing as Transdisciplinary Science and Technology, Cergy-Pontoise, France, October 28-31, 2008, pp. 25-30, 2008, ACM, 978-1-60558-046-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
R-factor, SLA (service level agreement), VoIP, MOS, PESQ, PSTN, voice quality |
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