Search results for "MOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Steve Shao-Shiun Chung	A charge-based capacitance model of short-channel MOSFETs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
25	Lawrence T. Pillage, Xueqing Huang, Ronald A. Rohrer	AWEsim: Asymptotic Waveform Evaluation for Timing Analysis.	DAC	1989	DBLP DOI BibTeX RDF
24	Rossella Blatt, Andrea Bonarini, Elisa Calabró, Matteo Della Torre, Matteo Matteucci, Ugo Pastorino	Fuzzy k -NN Lung Cancer Identification by an Electronic Nose.	WILF	2007	DBLP DOI BibTeX RDF	E-Nose, Olfactory Signal, Fuzzy k-NN, MOS Sensor Array, Pattern Classification, Electronic Nose, Lung Cancer
24	Yukiya Miura	Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	MOS transistors, operation-region model, X-Y zoning method, fault diagnosis, analog circuits
24	Sofiene Jelassi, Habib Youssef	Adaptive playback algorithm for interactive audio streaming over wireless ad-hoc networks.	IWCMC	2006	DBLP DOI BibTeX RDF	quality of service (QoS), mobile ad-hoc NETworks (MANET), streaming, mean opinion scores (MOS)
24	Dongming Wang 0001, Bican Xia	Stability analysis of biological systems with real solution classification.	ISSAC	2005	DBLP DOI BibTeX RDF	Cdc2-cyclin B/Wee1, Mos/MEK/p42 MAPK cascade, solution classification, stability, differential equations, equilibrium, polynomial system, biological network, real root
24	Nabil J. Sarhan, Chita R. Das	Caching and Scheduling in NAD-Based Multimedia Servers.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	Distributed Interval Caching (DIC), Multimedia-on-Demand (MOD), Multi-Objective Scheduling (MOS), Network-Attached Disks (NAD), Batching, Video-on-Demand (VOD)
24	Christian Schaefer, Thomas Enderes, Hartmut Ritter, Martina Zitterbart	Subjective quality assessment for multiplayer real-time games.	NETGAMES	2002	DBLP DOI BibTeX RDF	gaming, UMTS, mean opinion score (MOS), 3G networks
24	Simon Jolly, Atanas N. Parashkevov, Tim McDougall	Automated equivalence checking of switch level circuits .	DAC	2002	DBLP DOI BibTeX RDF	MOS circuits, custom design, switch level analysis, formal verification, VLSI design, equivalence checking
24	Stefano Serra Capizzano, Cristina Tablino Possio	Preliminary Remarks on Multigrid Methods for Circulant Matrices.	NAA	2000	DBLP DOI BibTeX RDF	two-grid and multigrid iterations, AMS(MOS) Subject Classification: 65F10, 65F15, Circulant matrices
24	Georg Heinig	Fast and Superfast Algorithms for Hankel-Like Matrices Related to Orthogonal Polynominals.	NAA	2000	DBLP DOI BibTeX RDF	Hankel matrix, fast algorithm AMS(MOS) Subject Classification: 47B35, 15A09, orthogonal polynomials, 15A23
24	Siu-Long Lei, Xiao-Qing Jin	Strang-Type Preconditioners for Differential-Algebraic Equations.	NAA	2000	DBLP DOI BibTeX RDF	GMRES method, Strang-type block-circulant preconditioner, clustered spectrum, BVMs AMS(MOS) Subject Classifications: 65F10, 65N22, convergence rate, ODEs, 65F15, 65L05, 15A18, DAEs
24	Pierluigi Amodio	Spectral Properties of Circulant Band Matrices Arising in ODE Methods.	NAA	2000	DBLP DOI BibTeX RDF	linear multistep methods AMS(MOS) subject classification: 65F10, ordinary differential equations, 65F15, 65L20, 65L05, circulant matrices
24	Liam P. Maguire, T. Martin McGinnity, L. J. McDaid	From a Fuzzy Flip-Flop to a MVL Flip-Flop.	ISMVL	1999	DBLP DOI BibTeX RDF	MVL flip-flop, MOS implementation, fuzzy reasoning
24	Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama	Quaternary Universal-Literal CAM for Cellular Logic Image Processing.	ISMVL	1996	DBLP DOI BibTeX RDF	content addressable memory(CAM), universal literal, threshold programming, floating-gate MOS transistor, multiple-valued logic
24	A. B. Bhattacharyya, Ram Singh Rana, S. K. Guha, Rajendar Bahl, R. Anand, M. J. Zarabi, P. A. Govindacharyulu, U. Gupta, V. Mohan, Jatin Roy, Amul Atri	A micropower analog hearing aid on low voltage CMOS digital process.	VLSI Design	1996	DBLP DOI BibTeX RDF	differential amplifiers, automatic gain control, micropower analog hearing aid, low voltage CMOS digital process, adaptive biasing, MOS translinear loop circuit, degenerating linearising resistor, input differential stage, AGC block, conversion efficiency, 3 micron, 1.0 V, power consumption, CMOS analogue integrated circuits, hearing aids
24	Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama	Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic
24	Anirudh Devgan	Accurate device modeling techniques for efficient timing simulation of integrated circuits.	ICCD	1995	DBLP DOI BibTeX RDF	device modeling techniques, Fast-to-evaluate and Accurate Simplified Transistor, aggressive MOS technologies, FAST models, timing, AGES, circuit analysis computing, integrated circuits, circuit simulators, transient analysis, transistors, transistor, transient simulator, timing simulation, timing simulator, electronic engineering computing, semiconductor device models
24	William C. Athas, Nestoras Tzartzanis	Energy recovery for low-power CMOS.	ARVLSI	1995	DBLP DOI BibTeX RDF	bootstrap circuits, low-power CMOS, energy-recovery techniques, voltage swing, transition time, MOS device parameters, adder designs, VLSI, mathematical model, bootstrapping, adders, CMOS logic circuits, CMOS logic circuits, power dissipation, integrated circuit modelling, SOI
22	Antonio LaTorre, Santiago Muelas, José María Peña Sánchez	Benchmarking a MOS-based algorithm on the BBOB-2010 noisy function testbed.	GECCO (Companion)	2010	DBLP DOI BibTeX RDF	IPOP-CMA-ES, benchmarking of algorithms, multiple offspring sampling, differential evolution, black-box optimization, continuous optimization
22	Mahsa Tahermaram, Mahdi Vadizadeh, A. Eslamzadeh, Morteza Fathipour	Employing work function enginnering and asymmetric gate oxide in nano-scale source-heterojunction-MOS-transistor.	EIT	2009	DBLP DOI BibTeX RDF
22	Andreas Saul	Simple Optimization Algorithm for MOS-Based Resource Assignment.	VTC Spring	2008	DBLP DOI BibTeX RDF
22	Toru Fujimura, Shigetoshi Nakatake	Transistor-level programmable MOS analog IC with body biasing.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Varun Aggarwal, Una-May O'Reilly	Simulation-based reusable posynomial models for MOS transistor parameters.	DATE	2007	DBLP DOI BibTeX RDF
22	Xavier Redondo, Jofre Pallares, Francisco Serra-Graells	A 1.2V 130µA 10-bit MOS-Only Log-Domain Sigma Delta Modulator.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Olivier Thomas, Marina Reyboz, Marc Belleville	Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Stéphane Badel, Yusuf Leblebici	Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Ramón González Carvajal, Juan Antonio Gómez Galán, Antonio Jesús Torralba Silgado, Clara Isabel Luján-Martínez, Jaime Ramírez-Angulo, Antonio J. López-Martín	A Very Linear OTA with V-I Conversion based on Quasi-Floating MOS Resistor.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Osman Musa Abdulkarim, Maitham Shams	A symmetric mos current-mode logic universal gate for high speed applications.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	MCML, SCL, VLSI, ASIC
22	Rossella Blatt, Andrea Bonarini, Elisa Calabró, Matteo Della Torre, Matteo Matteucci, Ugo Pastorino	Lung Cancer Identification by an Electronic Nose based on an Array of MOS Sensors.	IJCNN	2007	DBLP DOI BibTeX RDF
22	Masaaki Fukuhara, Masahiro Yoshida	Power consumption of a Hamming distance search CAM using neuron MOS transistors.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Benjamas Tongprasit, Tadashi Shibata	Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Kuan Zhou, Yifei Luo, Sizhong Chen, Allen Drake, John F. McDonald 0001, Tong Zhang 0002	Triple-rail MOS current mode logic for high-speed self-timed pipeline applications.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Sangho Shin, Kwyro Lee, Sung-Mo Kang	Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Dong-Shong Liang, Yaw-Hwang Chen, Chun-Min Wen, Chun-Da Tu, Kwang-Jow Gan, Cher-Shiung Tsai	The Design of MOS-NDR-Based Cellular Neural Network.	IJCNN	2006	DBLP DOI BibTeX RDF
22	Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil	Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
22	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	MOS current mode circuits: analysis, design, and variability.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
22	Tin Wai Kwan, Maitham Shams	Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic.	ASYNC	2005	DBLP DOI BibTeX RDF
22	Tomoyuki Nakayama, Toshihiko Yamasaki, Tadashi Shibata	A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
22	Di Long, Xianlong Hong, Sheqin Dong	Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
22	Paula López 0001, Matthias Oberst, Harald Neubauer, Johann Hauer, Diego Cabello	Performance analysis of high-speed MOS transistors with different layout styles.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
22	Shahnam Khabiri, Maitham Shams	A mathematical programming approach to designing MOS current-mode logic circuits.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
22	Tin Wai Kwan, Maitham Shams	Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic.	VLSI Design	2005	DBLP DOI BibTeX RDF
22	Stefan Dilhaire, Stéphane Grauby, Sébastien Jorez, Wilfrid Claeys	Strain energy imaging of a power MOS transistor using speckle interferometry.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
22	Xiang Lu, Zhuo Li 0001, Wangqi Qiu, D. M. H. Walker, Weiping Shi	A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.	MTV	2004	DBLP DOI BibTeX RDF
22	Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim	Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit.	ISMVL	2004	DBLP DOI BibTeX RDF
22	Tomoyuki Nakayama, Toshihiko Yamasaki, Tadashi Shibata	Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
22	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	Design and optimization of MOS current mode logic for parameter variations.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	MCML, optimization, design, automation, variation, technology scaling
22	Patricia Giacomelli, Márcio C. Schneider, Carlos Galup-Montoro	MOSVIEW: A Graphical Tool for MOS Analog Design.	MSE	2003	DBLP DOI BibTeX RDF
22	Stephen Tang, Siva G. Narendra, Vivek De	Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation.	ISLPED	2003	DBLP DOI BibTeX RDF	bandgap reference, process and temperature compensation, reference current, CMOS
22	Alfredo Arnaud, Carlos Galup-Montoro	Simple noise formulas for MOS analog design.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
22	Carlos Sánchez-López, Alejandro Díaz-Sánchez, Esteban Tlelo-Cuautle	Analog implementation of MOS-translinear Morlet Wavelets.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
22	Adrian Leuciuc, Yi Zhang	A highly linear low-voltage MOS transconductor.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
22	Mohab Anis, Mohamed I. Elmasry	Self-timed MOS current mode logic for digital applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
22	Tae-young Oh, Zhiping Yu, Robert W. Dutton	AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections.	ISQED	2002	DBLP DOI BibTeX RDF	AC analysis, thin gate oxide, quantum mechanical correction, threshold voltage shift, transconductace, channel length reduction, density-gradient, quantum confinement, PROPHET, channel doping, transport theory, device parameter extraction, effective oxide thickness, capacitance
22	Francisco Serra-Graells	All-MOS subthreshold log filters.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
22	Mahmoud Al-Nsour, Hoda S. Abdel-Aty-Zohdy	MOS fully analog reinforcement neural network chip.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
22	Jason M. Musicer, Jan M. Rabaey	MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments.	ISLPED	2000	DBLP DOI BibTeX RDF	CORDIC, digital logic, current mode logic, low-energy design
22	Mineo Kaneko	Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
22	Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti	Statistical modeling of MOS transistor mismatch based on the parameters' autocorrelation function.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
22	R. Brannen, Hassan O. Elwan, Mohammed Ismail 0001	A simple low-voltage all MOS linear-dB AGC/multiplier circuit.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
22	Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj	Modeling of accumulation MOS capacitors for analog design in digital VLSI processes.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
22	Dominique Python, Christian C. Enz	An antialiasing filter using complementary MOS transconductors biased in the triode region.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
22	Tetsuya Uemura, Pinaki Mazumder	Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
22	Steve H. Jen, Bing J. Sheu	A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
22	Massimo Conti, Simone Orcioni, Claudio Turchetti, Giovanni Soncini, Nicola Zorzi	Analytical device modeling for MOS analog IC's based on regularization and Bayesian estimation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
22	Sudhir M. Gowda, Bing J. Sheu	BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
22	Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury	Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
22	Aleksandra Pavasovic, Andreas G. Andreou, Charles R. Westgate	Characterization of subthreshold MOS mismatch in transistors for VLSI systems.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
22	Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee	Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics.	ICCAD	1994	DBLP DOI BibTeX RDF
22	Eric Felt, Amit Narayan, Alberto L. Sangiovanni-Vincentelli	Measurement and modeling of MOS transistor current mismatch in analog IC's.	ICCAD	1994	DBLP DOI BibTeX RDF
22	Ferenc Kovács, Gábor Hosszú	A proposed method for dynamic fitting of MOS model parameters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
22	Denis Martin, Nicholas C. Rumin	Delay prediction from resistance-capacitance models of general MOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
22	Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin	A recursive technique for computing delays in series-parallel MOS transistor circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
22	Richard Booth 0003, Marvin White	Simulation of a MOS transistor with spatially nonuniform channel parameters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
22	Farid N. Najm, Ibrahim N. Hajj	The complexity of fault detection in MOS VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
22	D. Patrick, Colin Lyden	An event-driven transient simulation algorithm for MOS and bipolar circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF
22	Paul J. V. Vandeloo, Willy M. C. Sansen	Modeling of the MOS transistor for high frequency analog design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
22	Mehmet A. Cirit	The Meyer model revisited: why is charge not conserved? [MOS transistor].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
22	Chung-Ping Wan, Bing J. Sheu	Temperature dependence modeling for MOS VLSI circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
22	Kyeongsoon Cho, Randal E. Bryant	Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation.	DAC	1989	DBLP DOI BibTeX RDF
22	A. Salz, Mark Horowitz	IRSIM: An Incremental MOS Switch-Level Simulator.	DAC	1989	DBLP DOI BibTeX RDF
22	Genhong Ruan, Jirí Vlach, James A. Barby	Current-limited switch-level timing simulator for MOS logic networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
22	Bing J. Sheu, Wen-Jay Hsu, P. K. Ko	An MOS transistor charge model for VLSI design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
22	Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman	SLS-a fast switch-level simulator [for MOS].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
22	Dale E. Hocevar, Paul F. Cox, Ping Yang 0001	Parametric yield optimization for MOS circuit blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
22	Foong-Charn Chang, Chin-Fu Chen, Prasad Subramaniam	An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits.	DAC	1988	DBLP BibTeX RDF
22	Dan Adler	A Dynamically-Directed Switch Model for MOS Logic Simulation.	DAC	1988	DBLP BibTeX RDF
22	William S. Beckett	MOS circuit models in Network C.	DAC	1986	DBLP DOI BibTeX RDF	C
22	Luís M. Vidigal, Sani R. Nassif, Stephen W. Director	CINNAMON: coupled integration and nodal analysis of MOS networks.	DAC	1986	DBLP DOI BibTeX RDF
22	Gabriele Saucier, Ghislaine Thuau	Systematic and optimized layout of MOS cells.	DAC	1985	DBLP DOI BibTeX RDF
22	Tak-Kwong Ng, S. Lennart Johnsson	Generation of layouts from MOS circuit schematics: a graph theoretic approach.	DAC	1985	DBLP DOI BibTeX RDF
22	Thomas J. Schaefer	A transistor-level logic-with-timing simulator for MOS circuits.	DAC	1985	DBLP DOI BibTeX RDF
22	Mark D. Matson	Macromodeling of digital MOS VLSI Circuits.	DAC	1985	DBLP DOI BibTeX RDF
17	Maxim Graubner, Parag S. Mogre, Ralf Steinmetz, Thorsten Lorenzen	A new QoE model and evaluation method for broadcast audio contribution over IP.	NOSSDAV	2010	DBLP DOI BibTeX RDF	acip, aoip, audio communication, mos, peaq, pemo-q, pqos, qoe, wb-pesq, user satisfaction, quality of experience, qos, e-model
17	Chen-Chi Wu, Kuan-Ta Chen, Chun-Ying Huang, Chin-Laung Lei	An empirical evaluation of VoIP playout buffer dimensioning in Skype, Google talk, and MSN Messenger.	NOSSDAV	2009	DBLP DOI BibTeX RDF	mos, VoIP, user satisfaction, quality of experience, e-model, pesq
17	Abiodun Iwayemi, Chi Zhou	VoIP Performance in Multi-radio Mobile Devices.	ISPA	2009	DBLP DOI BibTeX RDF	Mobile VoIP, WiFi, HSDPA, MOS
17	Marc Sullivan, James Pratt, Philip T. Kortum	Practical issues in subjective video quality evaluation: human factors vs. psychophysical image quality evaluation.	UXTV	2008	DBLP DOI BibTeX RDF	mos, subjective video quality
17	Adil Raja, Colin Flanagan	Real-Time, Non-intrusive Speech Quality Estimation: A Signal-Based Model.	EuroGP	2008	DBLP DOI BibTeX RDF	Non-Intrusive, Signal-based, MOS, GP
17	Il-Gu Jung, Eun-Jin Ko, Hyun-Chul Kang, Gilhaeng Lee	Voice quality measurement system for telephone service.	CSTST	2008	DBLP DOI BibTeX RDF	R-factor, SLA (service level agreement), VoIP, MOS, PESQ, PSTN, voice quality