Search results for "Microarchitecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Eric Rotenberg, James E. Smith 0001	Control Independence in Trace Processors.	MICRO	1999	DBLP DOI BibTeX RDF
26	Aurobindo Dasgupta, Ramesh Karri	High-reliability, low-energy microarchitecture synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
26	Omar Hammami	Performance Impacts of Superscalar Microarchitecture on SOM Execution.	Annual Simulation Symposium	1998	DBLP DOI BibTeX RDF
26	Soner Önder, Rajiv Gupta 0001	Automatic Generation of Microarchitecture Simulators.	ICCL	1998	DBLP DOI BibTeX RDF
26	Kevin J. Nowka, H. Peter Hofstee	Circuits and Microarchitecture for Gigahertz VLSI Designs.	ARVLSI	1997	DBLP DOI BibTeX RDF
26	Teresa L. Johnson, Matthew C. Merten, Wen-mei W. Hwu	Run-Time Spatial Locality Detection and Optimization.	MICRO	1997	DBLP DOI BibTeX RDF	prefetching, data cache, cache management, spatial locality, block size
26	Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith 0001	Trace Processors.	MICRO	1997	DBLP DOI BibTeX RDF	trace processors, multiscalar processors, next trace prediction, selective reissuing, context-based value prediction, trace cache
26	Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin	Performance-driven interconnection optimization for microarchitecture synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
26	Colin C. Charlton, D. Jackson, Paul H. Leng	A functional model of clocked microarchitectures.	MICRO	1989	DBLP DOI BibTeX RDF
26	Ashok Singhal, Yale N. Patt	Implementing a Prolog machine with multiple functional units.	MICRO	1988	DBLP BibTeX RDF	Prolog
25	Timothy M. Jones 0001, Michael F. P. O'Boyle, Jaume Abella 0001, Antonio González 0001, Oguz Ergin	Exploring the limits of early register release: Exploiting compiler analysis.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	compiler, energy efficiency, Low-power design, microarchitecture, register file
25	Pedro Chaparro, José González 0002, Qiong Cai, Greg Chrysler	Dynamic thermal management using thin-film thermoelectric cooling.	ISLPED	2009	DBLP DOI BibTeX RDF	thermal control, thin-film thermoelectric cooling, low-power, microarchitecture, dynamic thermal management
25	David H. Albonesi	Standing on Solid Ground.	IEEE Micro	2007	DBLP DOI BibTeX RDF	interconnects for multicore chips, special-purpose chips, debugging, human-computer interface, microarchitecture, programmability
25	Tingting Sha, Milo M. K. Martin, Amir Roth	NoSQ: Store-Load Communication without a Store Queue.	IEEE Micro	2007	DBLP DOI BibTeX RDF	microarchitecture, RISC, pipeline processors, VLIW architectures, CISC
25	Niranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam	Mechanisms for bounding vulnerabilities of processor structures.	ISCA	2007	DBLP DOI BibTeX RDF	redundant threading, microarchitecture, transient faults
25	Ahmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar, Steven Wereley, Stephen C. Jacobson	Aquacore: a programmable architecture for microfluidics.	ISCA	2007	DBLP DOI BibTeX RDF	fluidic, fluidic microarchitecture, programmable lab on a chip, microfluidics, instruction set
25	Robert P. Colwell	The Pentium Chronicles: Introduction.	Computer	2006	DBLP DOI BibTeX RDF	Professional conduct, P6 microarchitecture, Project management, Microprocessors
25	Michael J. Schulte, John Glossner, Sanjay Jinturkar, Mayan Moudgill, Suman Mamidi, Stamatis Vassiliadis	A Low-Power Multithreaded Processor for Software Defined Radio.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	low power, wireless communication, computer architecture, multithreading, microarchitecture, Software Defined Radio, processor design
25	Angshuman Parashar, Anand Sivasubramaniam, Sudhanva Gurumurthi	SlicK: slice-based locality exploitation for efficient redundant multithreading.	ASPLOS	2006	DBLP DOI BibTeX RDF	backward slice extraction, redundant threading, microarchitecture, transient faults
25	Benjamin C. Lee, David M. Brooks	Accurate and efficient regression modeling for microarchitectural performance and power prediction.	ASPLOS	2006	DBLP DOI BibTeX RDF	simulation, statistics, regression, inference, microarchitecture
25	Pradip Bose	Designing microprocessors with robust functionality and performance.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Reliability-aware microarchitecture, power-efficient design, microprocessor design
25	James Burns, Jean-Luc Gaudiot	Area and System Clock Effects on SMT/CMP Throughput.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	layout area estimation, microarchitecture trade off, processor architecture, SMT
25	Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González 0001, José Duato	On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	intercluster communication, instruction steering, complexity, on-chip interconnects, Clustered microarchitecture
25	Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero	A Comprehensive Analysis of Indirect Branch Prediction.	ISHPC	2002	DBLP DOI BibTeX RDF	indirect branch, Multi-Stage Cascaded Predictor, branch prediction, microarchitecture, Branch Target Buffer
25	George Sery, Shekhar Borkar, Vivek De	Life is CMOS: why chase the life after?	DAC	2002	DBLP DOI BibTeX RDF	leakage control, microarchitecture, technology scaling
25	Lieven Eeckhout, Koen De Bosschere, Henk Neefs	On the Feasibility of Fixed-Length Block Structured Architectures.	ACAC	2000	DBLP DOI BibTeX RDF	block structured architecture, performance evaluation, microarchitecture
25	Michael Bolotski, Thomas Simon, Carlin Vieri, Rajeevan Amirtharajah, Thomas F. Knight Jr.	Abacus: a 1024 processor 8 ns SIMD array.	ARVLSI	1995	DBLP DOI BibTeX RDF	bit-slice computers, Abacus, SIMD array, reconfigurable bit-parallel array, system-level design issues, real-time early vision processing, bit-slice processing element, 8 ns, real-time systems, computer vision, VLSI, parallel architectures, reconfigurable architectures, microarchitecture, VLSI implementation, communication primitives
25	Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor	A comparative evaluation of software techniques to hide memory latency.	HICSS (1)	1995	DBLP DOI BibTeX RDF	comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches
19	Sara S. Baghsorkhi, Matthieu Delahaye, Sanjay J. Patel, William D. Gropp, Wen-mei W. Hwu	An adaptive performance modeling tool for GPU architectures.	PPoPP	2010	DBLP DOI BibTeX RDF	parallel programming, analytical model, performance estimation, gpu
19	Sung-Boem Park, Anne Bracy, Hong Wang 0003, Subhasish Mitra	BLoG: post-silicon bug localization in processors using bug localization graphs.	DAC	2010	DBLP DOI BibTeX RDF	IFRA, BLoG, silicon debug, post-silicon validation
19	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001	A mechanistic performance model for superscalar out-of-order processors.	ACM Trans. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling
19	Dmitry G. Korzun, Andrei V. Gurtov	A local equilibrium model for P2P resource ranking.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
19	Bill Lin 0001, Jun (Jim) Xu, Nan Hua, Hao Wang 0006, Haiquan (Chuck) Zhao	A randomized interleaved DRAM architecture for the maintenance of exact statistics counters.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
19	Sipat Triukose, Zhihua Wen, Michael Rabinovich	Content delivery networks: how big is big enough?	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
19	Alma Riska, Erik Riedel	Evaluation of disk-level workloads at different time scales.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
19	Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong, Tor M. Aamodt	Analyzing CUDA workloads using a detailed GPU simulator.	ISPASS	2009	DBLP DOI BibTeX RDF
19	Gabriel H. Loh	A modular 3d processor for flexible product design and technology migration.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	modular, superscalar, 3d-integration
19	Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi	PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.	VLSI Design	2008	DBLP DOI BibTeX RDF
19	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Exploration and Customization of FPGA-Based Soft Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
19	Gilberto Contreras, Margaret Martonosi, Jinzhang Peng, Guei-Yuan Lueh, Roy Ju	The XTREM power and performance simulator for the Intel XScale core: Design and experiences.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	Intel XScale technology, Java, Power modeling, power measurements
19	Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang	The Implementation and Evaluation of a Low-Power Clock Distribution Network Based on EPIC.	NPC	2007	DBLP DOI BibTeX RDF
19	Kenneth Hoste, Aashish Phansalkar, Lieven Eeckhout, Andy Georges, Lizy Kurian John, Koen De Bosschere	Performance prediction based on inherent program similarity.	PACT	2006	DBLP DOI BibTeX RDF	inherent program behavior, performance modeling, workload characterization
19	Miquel Pericàs, Adrián Cristal, Rubén González 0001, Daniel A. Jiménez, Mateo Valero	A decoupled KILO-instruction processor.	HPCA	2006	DBLP DOI BibTeX RDF
19	José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López	Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions.	Euro-Par	2006	DBLP DOI BibTeX RDF
19	Krisztián Flautner	Cutting across layers of abstraction: : removing obstacles from the advancement of embedded systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	typical-case operation, embedded systems, low power, signal processing
19	Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John	Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks.	IISWC	2006	DBLP DOI BibTeX RDF
19	Arvind Krishnaswamy, Rajiv Gupta 0001	Dynamic coalescing for 16-bit instructions.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	16-bit Thumb ISA, 32-bit ARM ISA, AX instructions, instruction coalescing, performance, energy, Embedded processor, code size
19	Peter Petrov, Alex Orailoglu	A reprogrammable customization framework for efficient branch resolution in embedded processors.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	Branch resolution, pipeline organization
19	Nigel C. Paver, Moinul H. Khan, Bradley C. Aldrich, Christopher D. Emmons	Accelerating Mobile Video: A 64-Bit SIMD Architecture for Handheld Applications.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	architecture, SIMD, SOC, multi-media, wireless video
19	Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy	Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
19	Miquel Pericàs, Adrián Cristal, Rubén González 0001, Daniel A. Jiménez	Chained In-Order/Out-of-Order DoubleCore Architecture.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
19	Stamatis Vassiliadis, Stephan Wong, Georgi Gaydadjiev, Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte	The MOLEN Polymorphic Processor.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Custom computing machines, reconfigurable microcode, polymorphic processors, FPGA, reconfigurable processors, firmware
19	Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan	An analysis of a resource efficient checkpoint architecture.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	checkpoint architecture, high-performance computing, Computer architecture, scalable architecture
19	Lieven Eeckhout	Efficient architectural design of high performance microprocessors.	ISPASS	2004	DBLP DOI BibTeX RDF
19	Ashutosh S. Dhodapkar, James E. Smith 0001	Tuning Reconfigurable Microarchitectures for Power Efficiency.	IPDPS	2004	DBLP DOI BibTeX RDF
19	Emil Talpes, Diana Marculescu	Impact of technology scaling on energy aware execution cache-based microarchitectures.	ISLPED	2004	DBLP DOI BibTeX RDF
19	Amaury Darsch, André Seznec	IATO: A Flexible EPIC Simulation Environment.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
19	Yale N. Patt	The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won't Look Like?	HiPC	2003	DBLP DOI BibTeX RDF
19	Weiping Liao, Lei He 0001	Coupled Power and Thermal Simulation with Active Cooling.	PACS	2003	DBLP DOI BibTeX RDF
19	Roni Rosner, Yoav Almog, Micha Moffie, Naftali Schwartz, Avi Mendelson	PARROT: Power Awareness Through Selective Dynamically Optimized Traces.	PACS	2003	DBLP DOI BibTeX RDF
19	Mondira Deb Pant, Pankaj Pant, D. Scott Wills	On-chip decoupling capacitor optimization using architectural level prediction.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
19	Siddharth Rele, Santosh Pande, Soner Önder, Rajiv Gupta 0001	Optimizing Static Power Dissipation by Functional Units in Superscalar Processors.	CC	2002	DBLP DOI BibTeX RDF
19	Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith 0001, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas	Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.	PACS	2002	DBLP DOI BibTeX RDF
19	Alex Pajuelo, Antonio González 0001, Mateo Valero	Speculative Dynamic Vectorization.	ISCA	2002	DBLP DOI BibTeX RDF	Speculative dynamic vectorization, wide buses, speculative data computation, control independence, vector instructions
19	Zhenyu Tang, Lei He 0001, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa	Instruction Prediction for Step Power Reduction.	ISQED	2001	DBLP DOI BibTeX RDF
19	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Dynamically allocating processor resources between nearby and distant ILP.	ISCA	2001	DBLP DOI BibTeX RDF
19	Jayanth Gummaraju, Manoj Franklin	Branch Prediction in Multi-Threaded Processors.	IEEE PACT	2000	DBLP DOI BibTeX RDF
19	Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He 0001	Ramp Up/Down Functional Unit to Reduce Step Power.	PACS	2000	DBLP DOI BibTeX RDF
19	Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger	Clock rate versus IPC: the end of the road for conventional microarchitectures.	ISCA	2000	DBLP DOI BibTeX RDF
19	Alex Orailoglu	On-Line Fault Resilience Through Gracefully Degradable ASICs.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	fault tolerant ICs, reconfigurable ASICs, high level synthesis, on-line test, graceful degradation
19	Subbarao Palacharla, Norman P. Jouppi, James E. Smith 0001	Complexity-Effective Superscalar Processors.	ISCA	1997	DBLP DOI BibTeX RDF
17	Esteban Garzón, Robert Hanhan, Marco Lanuzza, Adam Teman, Leonid Yavits	FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture.	IEEE Access	2024	DBLP DOI BibTeX RDF
17	Chen Bai, Qi Sun 0002, Jianwang Zhai, Yuzhe Ma, Bei Yu 0001, Martin D. F. Wong	BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration.	ACM Trans. Design Autom. Electr. Syst.	2024	DBLP DOI BibTeX RDF
17	Leah Hoffmann	Achievement in Microarchitecture.	Commun. ACM	2024	DBLP DOI BibTeX RDF
17	Odysseas Chatzopoulos, George Papadimitriou 0001, Vasileios Karakostas, Dimitris Gizopoulos	Gem5-MARVEL: Microarchitecture-Level Resilience Analysis of Heterogeneous SoC Architectures.	HPCA	2024	DBLP DOI BibTeX RDF
17	Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu 0001, Martin D. F. Wong	Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning.	AAAI	2024	DBLP DOI BibTeX RDF
17	Justin Feng, Fatemeh Arkannezhad, Christopher Ryu, Enoch Huang, Siddhant Gupta, Nader Sehatbakhsh	Simulating Our Way to Safer Software: A Tale of Integrating Microarchitecture Simulation and Leakage Estimation Modeling.	IEEE Comput. Archit. Lett.	2023	DBLP DOI BibTeX RDF
17	R. Sivaramakrishnan, G. Senthilkumar	A Deep Learning Framework for Microarchitecture Independent Workload Characterization Technique for Multi-core Asymmetric Embedded Systems.	SN Comput. Sci.	2023	DBLP DOI BibTeX RDF
17	Emil Talpes, Debjit Das Sarma, Douglas Williams, Sahil Arora, Thomas Kunjan, Benjamin Floering, Ankit Jalote, Christopher Hsiong, Chandrasekhar Poorna, Vaidehi Samant, John Sicilia, Anantha Kumar Nivarti, Raghuvir Ramachandran, Tim C. Fischer, Ben Herzberg, Bill McGee, Ganesh Venkataramanan, Pete Banon	The Microarchitecture of DOJO, Tesla's Exa-Scale Computer.	IEEE Micro	2023	DBLP DOI BibTeX RDF
17	Hyerean Jang, Youngjoo Shin	MicroCFI: Microarchitecture-Level Control-Flow Restrictions for Spectre Mitigation.	IEEE Access	2023	DBLP DOI BibTeX RDF
17	Ngoc-Son Pham, Taeweon Suh	Optimization of Microarchitecture and Dataflow for Sparse Tensor CNN Acceleration.	IEEE Access	2023	DBLP DOI BibTeX RDF
17	Bruno Sá, Luca Valente, José Martins, Davide Rossi, Luca Benini, Sandro Pinto 0001	CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
17	Jianwang Zhai, Yici Cai	Microarchitecture Design Space Exploration via Pareto-Driven Active Learning.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
17	Ajay Krishna Ananda Kumar, Sami Alsalamin, Hussam Amrouch, Andreas Gerstlauer	Machine Learning-Based Microarchitecture- Level Power Modeling of CPUs.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
17	Serkan Dereli, Asiye Rümeysa Ünsal	A new microarchitecture hardware proposal for the use of the improved template matching method in face similarity detection.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
17	Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou 0001, Bei Yu 0001	McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
17	Thomas Chamelot, Damien Couroussé, Karine Heydemann	MAFIA: Protecting the Microarchitecture of Embedded Systems Against Fault Injection Attacks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
17	Yufeng Zhou, Alan L. Cox, Sandhya Dwarkadas, Xiaowan Dong	The Impact of Page Size and Microarchitecture on Instruction Address Translation Overhead.	ACM Trans. Archit. Code Optim.	2023	DBLP DOI BibTeX RDF
17	Zhaoyang Zhang, Jinwu Chen, Xi Chen, An Guo, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xingyu Pu, Shengnan He, Xin Si, Jun Yang 0006	From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits.	Sci. China Inf. Sci.	2023	DBLP DOI BibTeX RDF
17	Qiang Li, Jun Tao 0001, Jun Han 0003	SPARK: An automatic Score-Power-Area efficient RISC-V processor microarchitecture SeeKer.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
17	Bruno Sá, Luca Valente, José Martins, Davide Rossi, Luca Benini, Sandro Pinto 0001	CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration.	CoRR	2023	DBLP DOI BibTeX RDF
17	Thomas Chamelot, Damien Couroussé, Karine Heydemann	MAFIA: Protecting the Microarchitecture of Embedded Systems Against Fault Injection Attacks.	CoRR	2023	DBLP DOI BibTeX RDF
17	Mark Ermolov, Dmitry Sklyarov, Maxim Goryachy	Undocumented x86 instructions to control the CPU at the microarchitecture level in modern Intel processors.	J. Comput. Virol. Hacking Tech.	2023	DBLP DOI BibTeX RDF
17	Jingweijia Tan, Qixiang Wang, Kaige Yan, Xiaohui Wei, Xin Fu	Saca-FI: A microarchitecture-level fault injection framework for reliability analysis of systolic array based CNN accelerator.	Future Gener. Comput. Syst.	2023	DBLP DOI BibTeX RDF
17	Mila Anastasova, Reza Azarderakhsh, Mehran Mozaffari Kermani, Lubjana Beshaj	Time-Efficient Finite Field Microarchitecture Design for Curve448 and Ed448 on Cortex-M4.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
17	Thomas Chamelot, Damien Couroussé, Karine Heydemann	MAFIA: Protecting the Microarchitecture of Embedded Systems Against Fault Injection Attacks.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
17	Styliani Tompazi, Ioannis Tsiokanos, Jesús Martínez del Rincón, Georgios Karakonstantis	Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning.	IEEE Des. Test	2023	DBLP DOI BibTeX RDF
17	Xiaohui Wei, Changbao Zhou, Hengshan Yue, Joey Tianyi Zhou	TC-SEPM: Characterizing soft error resilience of CNNs on Tensor Cores from program and microarchitecture perspectives.	J. Syst. Archit.	2023	DBLP DOI BibTeX RDF
17	Hongwei Cui, Yujie Cui, Honglan Zhan, Shuhao Liang, Xianhua Liu 0001, Chun Yang, Xu Cheng 0001	MBAPIS: Multi-Level Behavior Analysis Guided Program Interval Selection for Microarchitecture Studies.	PACT	2023	DBLP DOI BibTeX RDF
17	Cairui She, Liwei Chen, Gang Shi	DPFCFI: A Hardware-Based Forward Control-Flow Integrity for Architecture and Microarchitecture.	ISPA/BDCloud/SocialCom/SustainCom	2023	DBLP DOI BibTeX RDF