Search results for "netlist"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Peter B. Reintjes	AUNT: A Universal Netlist Translator.	J. Log. Program.	1990	DBLP DOI BibTeX RDF
21	Wolfgang Meier	Hierarchical Netlist Extraction and Design Rule Check.	Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme	1990	DBLP DOI BibTeX RDF
21	Sandeep Aranake, Anil Dikshit, A. Arun	An edge based netlist extractor for IC layouts.	ICCD	1990	DBLP DOI BibTeX RDF
21	Larry G. Jones	Fast incremental netlist compilation of hierarchical schematics.	ICCAD	1989	DBLP DOI BibTeX RDF
21	C. C. Chen, S.-L. Chow	The Layout Synthesizer: An Automatic Netlist-to-Layout System.	DAC	1989	DBLP DOI BibTeX RDF
21	Larry G. Jones	Fast Online/Offline Netlist Compilation of Hierarchical Schematics.	DAC	1989	DBLP DOI BibTeX RDF
21	Peter B. Reintjes	AUNT: A Universal Netlist Translator.	SLP	1987	DBLP BibTeX RDF
21	J. Doug Tygar, Ron Ellickson	Efficient netlist comparison using hierarchy and randomization.	DAC	1985	DBLP DOI BibTeX RDF
19	Peter A. Jamieson, Kenneth B. Kent	Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, verilog hdl
19	Seungwhun Paik, Sangmin Kim, Youngsoo Shin	Wakeup synthesis and its buffered tree construction for power gating circuit designs.	ISLPED	2010	DBLP DOI BibTeX RDF	wakeup synthesis, leakage, power gating
19	Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li 0001, Gi-Joon Nam, Charles B. Winn	Detecting tangled logic structures in VLSI netlists.	DAC	2010	DBLP DOI BibTeX RDF	congestion prediction, rent rule, tangled logic, clustering
19	Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour	Towards automated ECOs in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	pst, optimization, fpga, boolean satisfiability, resynthesis
19	Corneliu Rusu, Lacrimioara Grama, Jarmo Takala	SPICE Simulation of Analog Filters: A Method for Designing Digital Filters.	EUROCAST	2009	DBLP DOI BibTeX RDF	analog filter, SPICE, digital filter
19	Yun Du, Yangshuo Ding, Yujie Chen, Zhiqiang Gao	IP protection platform based on watermarking technique.	ISQED	2009	DBLP DOI BibTeX RDF
19	Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001	High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.	ISMVL	2008	DBLP DOI BibTeX RDF	multiple-valued logic circuits, arithmetic circuits, high-level design, circuit synthesis
19	Jyotirmoy Ghosh, Siddhartha Mukhopadhyay, Amit Patra, Barry Culpepper, Tawen Mei	A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts.	VLSI Design	2008	DBLP DOI BibTeX RDF
19	Sabyasachi Das, Sunil P. Khatri	An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products.	VLSI Design	2008	DBLP DOI BibTeX RDF
19	Wenyi Feng, Jonathan W. Greene	Post-Placement Interconnect Entropy.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
19	Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Node Mergers in the Presence of Don't Cares.	ASP-DAC	2007	DBLP DOI BibTeX RDF
19	Jin Guo 0001, Antonis Papanikolaou, Francky Catthoor	Topology exploration for energy efficient intra-tile communication.	ASP-DAC	2007	DBLP DOI BibTeX RDF
19	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	VCEGAR: Verilog CounterExample Guided Abstraction Refinement.	TACAS	2007	DBLP DOI BibTeX RDF
19	Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen	Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
19	Wenyi Feng, Jonathan W. Greene	Post-placement interconnect entropy.	FPGA	2006	DBLP DOI BibTeX RDF
19	Jin Guo 0001, Antonis Papanikolaou, Pol Marchal, Francky Catthoor	Physical design implementation of segmented buses to reduce communication energy.	ASP-DAC	2006	DBLP DOI BibTeX RDF
19	Shweta Shah, Nazanin Mansouri, Adrián Núñez-Aldana	Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
19	Wenyi Feng, Jonathan W. Greene	Post-placement interconnect entropy: how many configuration bits does a programmable logic device need?	SLIP	2006	DBLP DOI BibTeX RDF	switching requirement, FPGAs, lower bound, entropy, interconnect, placement, rent's rule, programmable interconnect
19	Padmini Gopalakrishnan, Xin Li 0001, Lawrence T. Pileggi	Architecture-aware FPGA placement using metric embedding.	DAC	2006	DBLP DOI BibTeX RDF	FPGAs, placement, metric embedding
19	Viresh Paruthi, Christian Jacobi 0002, Kai Weber 0001	Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting.	CHARME	2005	DBLP DOI BibTeX RDF
19	Qinghua Liu, Malgorzata Marek-Sadowska	A congestion-driven placement framework with local congestion prediction.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	cell padding, congestion prediction, placement migration
19	Ivan Blunno, Luciano Lavagno	Designing an asynchronous microcontroller using Pipefitter.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
19	Hai Zhou 0001, Chuan Lin 0002	Retiming for wire pipelining in system-on-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
19	Bo Hu 0006, Malgorzata Marek-Sadowska	Fine granularity clustering-based placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
19	Sotiris Bantas, Yorgos Koutsoyannopoulos, Apostolos Liapis	An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain.	DATE	2004	DBLP DOI BibTeX RDF
19	Laurent Arditi, Gérard Berry, Michael Kishinevsky	Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs.	FMCAD	2004	DBLP DOI BibTeX RDF
19	Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz	An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	phase abstraction, automatic abstraction, CTL model checking, level-sensitive latch, bisimulation, model reduction
19	Yongseok Cheon, Seokjin Lee, Martin D. F. Wong	Stable Multiway Circuit Partitioning for ECO.	ICCAD	2003	DBLP DOI BibTeX RDF	Stable circuit partitioning, incremental partitioning, engineering change order, similarity cost, placement
19	Lei Yang 0019, C.-J. Richard Shi	FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
19	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Bounding the efforts on congestion optimization for physical synthesis.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	optimization, logic synthesis, physical design, technology mapping, routing congestion
19	Michael D. Hutton, Jonathan Rose, Derek G. Corneil	Automatic generation of synthetic sequential benchmark circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
19	Min Ouyang, Michel Toulouse, Krishnaiyan Thulasiraman, Fred W. Glover, Jitender S. Deogun	Multilevel cooperative search for the circuit/hypergraphpartitioning problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
19	Ivan Blunno, Luciano Lavagno	Designing an Asynchronous Microcontroller Using Pipefitter.	ICCD	2002	DBLP DOI BibTeX RDF
19	J. A. López, Ginés Doménech, R. Ruiz, Tom J. Kazmierski	Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
19	Haifeng Zhou, Zhenghui Lin, Wei Cao	Research on VHDL RTL Synthesis System.	DELTA	2002	DBLP DOI BibTeX RDF	VHDL RTL synthesis, ambiguous grammar, language level optimization, inference, formal semantics, parser
19	Satnam Singh, Philip James-Roxby	Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits.	FPL	2001	DBLP DOI BibTeX RDF
19	Wolfgang Günther 0001, Rolf Drechsler	Performance Driven Optimization for MUX based FPGAs.	VLSI Design	2001	DBLP DOI BibTeX RDF
19	Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl	Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
19	Joachim Pistorius, Edmée Legai, Michel Minoux	PartGen: a generator of very large circuits to benchmark thepartitioning of FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
19	Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy	Enhanced untestable path analysis using edge graphs.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	untestable path analysis, edge graphs, partial path sensitization, edge graph, logic testing, logic circuits, logic circuits, path delay fault testing
19	Abhijit Das	On the Transistor Sizing Problem.	VLSI Design	2000	DBLP DOI BibTeX RDF	Timing Analysis, Timing Optimization, Transistor Sizing, Delay Constraint
19	Per Arne Karlsen, Per Torstein Røine	A Timing Verifier and Timing Profiler for Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
19	Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang	A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning.	ASP-DAC	1999	DBLP DOI BibTeX RDF
19	Avinash K. Gautam, V. Visvanathan, S. K. Nandy 0001	Automatic Generation of Tree Multipliers Using Placement-Driven Netlists.	ICCD	1999	DBLP DOI BibTeX RDF
19	Michael D. Hutton, Jonathan Rose	Applications of clone circuits to issues in physical-design.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
19	Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh	Potential-NRG: Placement with Incomplete Data.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
19	Valeria Bertacco, Maurizio Damiani	The disjunctive decomposition of logic functions.	ICCAD	1997	DBLP DOI BibTeX RDF	disjunctive decomposition, combinational logic optimization
19	Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu	Large scale circuit partitioning with loose/stable net removal and signal flow based clustering.	ICCAD	1997	DBLP DOI BibTeX RDF
19	Bogdan G. Arsintescu	A Method for Analog Circuits Visualization.	ICCD	1996	DBLP DOI BibTeX RDF	Analog circuits visualization, Design verification tools, Computer aided design for analog circuits
19	Timothy Kam, P. A. Subrahmanyam	Comparing layouts with HDL models: a formal verification technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
19	Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng	Technology mapping of timed circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits
19	Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain	Extraction of finite state machines from transistor netlists by symbolic simulation.	ICCD	1995	DBLP DOI BibTeX RDF	finite state machine extraction, transistor netlists, clock level finite state machines, gate level representation, circuit clocking, output timing, simulation patterns, next state, output function, equivalent FSM, static storage structures, time multiplexed inputs, time multiplexed outputs, finite state machines, logic design, logic CAD, circuit analysis computing, FSMs, symbolic simulation, symbolic simulator, Ordered Binary Decision Diagrams
19	Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran	On the intrinsic Rent parameter and spectra-based partitioning methodologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
19	Georg Pelz, Uli Roettcher	Pattern matching and refinement hybrid approach to circuit comparison.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
19	Nishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu	HS: a hierarchical search package for CAD data.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
19	Stephen Walters	Computer-Aided Prototyping for ASIC-Based Systems.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
19	Magdy S. Abadir, Jack Ferguson	An improved layout verification algorithm (LAVA).	EURO-DAC	1990	DBLP DOI BibTeX RDF
19	Robi Dutta, Maurice Marks, Craig Morrissey, Ravi Rao, Lee Sapiro	A flexible hierarchical 3-D module assembler.	EURO-DAC	1990	DBLP DOI BibTeX RDF
19	Daniel Fischer, Yossi Levhari, Gadi Singer	NETHDL: abstraction of schematics to high-level HDL.	EURO-DAC	1990	DBLP DOI BibTeX RDF
19	Cyrus Bamji, Jonathan Allen	GRASP: A Grammar-based Schematic Parser.	DAC	1989	DBLP DOI BibTeX RDF
10	Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann	Automatic generation of hierarchical placement rules for analog integrated circuits.	ISPD	2010	DBLP DOI BibTeX RDF	hierarchical placement rules, constraints, placement, analog integrated circuits
10	Charles J. Alpert, Zhuo Li 0001, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez	What makes a design difficult to route.	ISPD	2010	DBLP DOI BibTeX RDF	congestion driven physical synthesis, routing
10	Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan	TSV stress aware timing analysis with applications to 3D-IC layout optimization.	DAC	2010	DBLP DOI BibTeX RDF	mobility variation, timing analysis, stress, TSV, 3DIC
10	Paul Zuber, Petr Dobrovolný, Miguel Miranda	A holistic approach for statistical SRAM analysis.	DAC	2010	DBLP DOI BibTeX RDF	statistical SRAM analysis, process variability, yield prediction
10	Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang	An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
10	Yongfeng Feng, H. Alan Mantooth	Algorithms for Automatic Model Topology Formulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
10	Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira	Generating realistic stimuli for accurate power grid analysis.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	stimuli generation, simulation, verification, Power grid, ground bounce, voltage drop
10	Martin Rozkovec, Ondrej Novák	Structural test of programmed FPGA circuits.	DDECS	2009	DBLP DOI BibTeX RDF
10	Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda	Measurement of power supply noise tolerance of self-timed processor.	DDECS	2009	DBLP DOI BibTeX RDF
10	Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton	SmartOpt: an industrial strength framework for logic synthesis.	FPGA	2009	DBLP DOI BibTeX RDF	abc, blif, edge flow, smartopt, fpga, interface, technology mapping
10	Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang	A metal-only-ECO solver for input-slew and output-loading violations.	ISPD	2009	DBLP DOI BibTeX RDF	input skew violation, output loading, buffer insertion, eco
10	Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer	On improving optimization effectiveness in interconnect-driven physical synthesis.	ISPD	2009	DBLP DOI BibTeX RDF	routing, interconnect, physical synthesis, circuit optimization, vlsi
10	Loïc Lagadec, Damien Picard	Software-like debugging methodology for reconfigurable platforms.	IPDPS	2009	DBLP DOI BibTeX RDF
10	Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner 0001, Jürgen Becker 0001	FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.	ARC	2009	DBLP DOI BibTeX RDF	design assurance, bitstream debugging, security, FPGA, Reconfigurable Computing, design verification, EDA tools
10	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Timing-driven N-way decomposition.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	logic design, decomposition, timing optimization
10	Raghuram Srinivasan, Harold W. Carter	A taylor series methodology for analyzing the effects of process variation on circuit operation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	circuit simulation
10	Pritha Banerjee 0001, Megha Sangtani, Susmita Sur-Kolay	Floorplanning for Partial Reconfiguration in FPGAs.	VLSI Design	2009	DBLP DOI BibTeX RDF
10	Jackey Z. Yan, Natarajan Viswanathan, Chris Chu	Handling complexities in modern large-scale mixed-size placement.	DAC	2009	DBLP DOI BibTeX RDF	incremental placement, mixed-size design, floorplanning
10	Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, David Z. Pan	O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration.	DAC	2009	DBLP DOI BibTeX RDF	low power nanophotonic integration, optical routing, integer linear programming
10	Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco	Event-driven gate-level simulation with GP-GPUs.	DAC	2009	DBLP DOI BibTeX RDF	gate-level simulation, general purpose graphics processing unit (GP-GPU), high-performance simulation
10	Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal	A high-level clustering algorithm targeting dual Vdd FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	clustering, field programmable gate arrays, partitioning, placement, voltage scaling, Dynamic power
10	Daniel Ziener, Jürgen Teich	Power Signature Watermarking of IP Cores for FPGAs.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	IPP, FPGA, watermarking, signature, power analysis, IP cores
10	Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll	Design flow for embedded FPGAs based on a flexible architecture template.	DATE	2008	DBLP DOI BibTeX RDF
10	Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber 0001, Christian Jacobi 0002, Matthias Pflanz	Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof.	ASP-DAC	2008	DBLP DOI BibTeX RDF
10	Jie Hao, Silong Peng	HJ-hPl: Hierarchical Mixed-Size Placement Algorithm with Priori Wirelength Estimation.	ICYCS	2008	DBLP DOI BibTeX RDF
10	Pradeep Fernando, Hariharan Sankaran, Srinivas Katkoori, Didier Keymeulen, Adrian Stoica, Ricardo Salem Zebulum, Rajeshuni Ramesham	A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine.	IPDPS	2008	DBLP DOI BibTeX RDF
10	Qiang Ma 0002, Evangeline F. Y. Young	Network flow-based power optimization under timing constraints in MSV-driven floorplanning.	ICCAD	2008	DBLP DOI BibTeX RDF
10	Amit Agarwal, Jason Cong, Brian Tagiku	Fault tolerant placement and defect reconfiguration for nano-FPGAs.	ICCAD	2008	DBLP DOI BibTeX RDF
10	Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes	Improving SAT-based Combinational Equivalence Checking through circuit preprocessing.	ICCD	2008	DBLP DOI BibTeX RDF
10	Sz-Cheng Huang, Jie-Hong Roland Jiang	A dynamic accuracy-refinement approach to timing-driven technology mapping.	ICCD	2008	DBLP DOI BibTeX RDF
10	Andrea Pellegrini, Kypros Constantinides, Dan Zhang 0004, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin	CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework.	ICCD	2008	DBLP DOI BibTeX RDF
10	Likun Xia, Ian M. Bell, Antony J. Wilkinson	A novel approach for automated model generation.	ISCAS	2008	DBLP DOI BibTeX RDF