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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 16149 publication records. Showing 16145 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
34 | Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen |
Timing- and crosstalk-driven area routing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes |
Fast and accurate timing characterization using functionalinformation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Alejandro Hevia, Marcos A. Kiwi |
Strength of Two Data Encryption Standard Implementations under Timing Attacks. |
LATIN |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Vighneswara Row Mokkarala, Antony Fan, Ravi Apte |
A unified approach to simulation and timing verification at the functional level. |
DAC |
1985 |
DBLP DOI BibTeX RDF |
|
34 | Seyed-Abdollah Aftabjahani, Linda S. Milor |
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Variation-Aware Timing Models, Standard Cells, Statistical Timing Analysis |
34 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process |
34 | Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai |
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
latch-based design, time borrowing, timing budgeting, static timing analysis, Cycle stealing |
34 | Supratik Chakraborty, Rajeev Murgai |
Layout-Driven Timing Optimization by Generalized De Morgan Transform. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
layout-driven optimization, in-place circuit optimization, DeMorgan transformation, deep sub-micron design, Timing optimization, timing closure |
34 | Eduard Cerny, Fen Jin |
Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
Interface verification, interface controllers, relational interval arithmetic, constraint logic programming, timing verification, timing diagrams |
34 | Wendy Belluomini, Chris J. Myers |
Efficient Timing Analysis Algorithms for Timed State Space Exploration. |
ASYNC |
1997 |
DBLP DOI BibTeX RDF |
timing analysis algorithms, timed state space exploration, timed circuit synthesis, geometric regions, computational complexity, timing, asynchronous circuits, partial orders |
34 | Peter A. Walker, Sumit Ghosh |
On the Nature and Inadequacies of Transport Timing Delay Constructs in VHDL Descriptions. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
timing constructs, simulation of hardware descriptions, discrete event simulation, VHDL, Digital simulation, logic Simulation, Timing semantics |
34 | Anmol Mathur, Kuang-Chien Chen, C. L. Liu 0001 |
Re-engineering of timing constrained placements for regular architectures. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems re-engineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging |
34 | Ajay J. Daga, William P. Birmingham |
A symbolic-simulation approach to the timing verification of interacting FSMs. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
symbolic-simulation approach, interacting FSMs, timing verifier, complex sequential circuit verification, combinational paths, inherently modular nature, symbolic simulation verification methodology, formal verification, logic testing, finite state machines, finite state machines, sequential circuits, circuit analysis computing, timing verification |
34 | David Hung-Chang Du, S. H. Yen, Subbarao Ghanta |
On the General False Path Problem in Timing Analysis. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
Graph Theory, Timing Analysis, Logic Simulation, VLSI circuit, Timing Verification, False path |
33 | Mongkol Ekpanyapong, Xin Zhao 0001, Sung Kyu Lim |
An Efficient Computation of Statistically Critical Sequential Paths Under Retiming. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Xinyuan Wang 0005, Douglas S. Reeves |
Robust correlation of encrypted attack traffic through stepping stones by manipulation of interpacket delays. |
CCS |
2003 |
DBLP DOI BibTeX RDF |
intrusion tracing, robustness, correlation, stepping stones |
33 | Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye |
A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
gate delay model, variability, static timing analysis, statistical timing analysis |
32 | Yoshitaka Nagami, Daisuke Miyamoto, Hiroaki Hazeyama, Youki Kadobayashi |
An Independent Evaluation of Web Timing Attack and its Countermeasure. |
ARES |
2008 |
DBLP DOI BibTeX RDF |
Web Timing Attack, Countermeasure, Web Application Security |
32 | Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto |
Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
principal component analysis, gaussianization, power supply noise, statistical timing analysis |
32 | Tien Nhut Ho, Vishy Karri |
Fuzzy Expert System to Estimate Ignition Timing for Hydrogen Car. |
ISNN (2) |
2008 |
DBLP DOI BibTeX RDF |
Hydrogen powered car, Ignition timing, Ignition advance, Hydrogen engine tuning, Fuzzy expert system |
32 | Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
On the role of timing masking in reliable logic circuit design. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
timing, soft errors, SEUs |
32 | Joel Coffman, Christopher A. Healy, Frank Mueller 0001, David B. Whalley |
Generalizing parametric timing analysis. |
LCTES |
2007 |
DBLP DOI BibTeX RDF |
parametric timing analysis, worst-case execution time (WCET) analysis |
32 | Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou 0001, Kip Killpack |
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
modeling, crosstalk, static timing analysis |
32 | Kunhyuk Kang, Bipul C. Paul, Kaushik Roy 0001 |
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
Process variation, spatial correlation, statistical timing analysis |
32 | Yao-Song Shen, Hongfeng Gao, Haishan Yao |
Spike Timing-Dependent Synaptic Plasticity in Visual Cortex: A Modeling Study. |
J. Comput. Neurosci. |
2005 |
DBLP DOI BibTeX RDF |
spike timing-dependent synaptic plasticity, two-point stimuli, orientation shifts, visual cortex |
32 | Albert Mo Kim Cheng, Hsiu-yen Tsai |
A Graph-Based Approach for Timing Analysis and Refinement of OPS5 Knowledge-Based Systems. |
IEEE Trans. Knowl. Data Eng. |
2004 |
DBLP DOI BibTeX RDF |
real-time systems, expert systems, Timing analysis, response time, rule-based systems, production systems, OPS5, KBS |
32 | Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou |
Incremental physical resynthesis for timing optimization. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
FPGA, placement, logic synthesis, timing optimization |
32 | Jia Xu |
On Inspection and Verification of Software with Timing Requirements. |
IEEE Trans. Software Eng. |
2003 |
DBLP DOI BibTeX RDF |
current practices, preruntime scheduling, verification, Real-time, complexity, predictability, software, code, inspection, software structures, restrictions, timing requirements |
32 | Julien Cathalo, François Koeune, Jean-Jacques Quisquater |
A New Type of Timing Attack: Application to GPS. |
CHES |
2003 |
DBLP DOI BibTeX RDF |
GPS, Side-Channel Attacks, Timing Attacks, Identification Schemes |
32 | Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah |
Statistical timing for parametric yield prediction of digital integrated circuits. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
statistical timing, yield prediction |
32 | Christopher A. Healy, David B. Whalley |
Automatic Detection and Exploitation of Branch Constraints for Timing Analysis. |
IEEE Trans. Software Eng. |
2002 |
DBLP DOI BibTeX RDF |
best-case execution time, branch constraints, Real-time systems, timing analysis, worst-case execution time, infeasible paths |
32 | Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers |
Automatic Derivation of Timing Constraints by Failure Analysis. |
CAV |
2002 |
DBLP DOI BibTeX RDF |
Trace theoretic verification, Timing constraints, Failure analysis, Timed circuits |
32 | John A. Clark, Jeremy L. Jacob |
Fault Injection and a Timing Channel on an Analysis Technique. |
EUROCRYPT |
2002 |
DBLP DOI BibTeX RDF |
Heuristic Optimisation, identification schemes, timing channels |
32 | Shane Sendall, Alfred Strohmeier |
Specifying Concurrent System Behavior and Timing Constraints Using OCL and UML. |
UML |
2001 |
DBLP DOI BibTeX RDF |
Software System Specification, Unified Modeling Language (UML), Concurrent Programming, Timing Constraints, Object Constraint Language (OCL), Pre- and Postcondition |
32 | Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng |
Dynamic Timing Analysis Considering Power Supply Noise Effects. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
dynamic timing analysis, input pattern dependent, power supply noise, deep submicron designs |
32 | Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai |
A Timing-Driven Block Placer Based on Sequence Pair Model. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
timing-driven, building block placement, sequence pair, simulated annealing algorithm |
32 | Satoshi Yamane |
Formal Timing Verification Techniques for Distributed System . |
FTDCS |
1995 |
DBLP DOI BibTeX RDF |
language inclusion algorithm, formal specification, timing verification, timed automaton |
32 | Vicki H. Allan, Robert A. Mueller |
Compaction with General Timing. |
IEEE Trans. Software Eng. |
1988 |
DBLP DOI BibTeX RDF |
general synchronous timing, microcode generation systems, branch delays, volatile registers, microoperations, multiple microinstructions, clocked microarchitectures, compilers, synchronisation, program compilers, microprogramming, target architecture, data-dependency graphs |
32 | Val Pevzner, Andrew A. Kennings, Andy Fox |
Physical optimization for FPGAs using post-placement topology rewriting. |
ISPD |
2009 |
DBLP DOI BibTeX RDF |
fpga, timing optimization, physical synthesis |
32 | Shinya Umeno |
Event order abstraction for parametric real-time system verification. |
EMSOFT |
2008 |
DBLP DOI BibTeX RDF |
automatic timing synthesis, counter-example guided abstraction refinement (cegar), event-based approach, parametric verification |
32 | Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia |
Hippocrates: First-Do-No-Harm Detailed Placement. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
synthesis optimizations, Hippocrates, first-do-no-harm detailed placement, pin-based timing constraint, electrical constraints, reduced wire-length |
32 | Ayose Falcón, Paolo Faraboschi, Daniel Ortega |
Combining Simulation and Virtualization through Dynamic Sampling. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
code caching, dynamic sampling, fast timing simulation, virtual machines, virtualization |
32 | Edwin Naroska, Rung-Ji Shang, Feipei Lai, Uwe Schwiegelshohn |
Hybrid Parallel Circuit Simulation Approaches. |
IEEE PACT |
2000 |
DBLP DOI BibTeX RDF |
parallel timing simulation, cycle-based simulation, circuit simulation, workstation cluster |
32 | Wael M. Elseaidy |
Static and dynamic analysis of real-time systems. |
ACM Southeast Regional Conference |
1992 |
DBLP DOI BibTeX RDF |
SUP-INF procedure, Spec U/L bounds, deterministic timing tools, negative cycle, positive cycle, program U/L bounds, Real-time, theorem proving, real-time logic |
31 | Takashi Enami, Masanori Hashimoto, Takashi Sato |
Decoupling capacitance allocation for timing with statistical noise model and timing analysis. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen |
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Mariagrazia Graziano, Cristiano Forzan, Davide Pandini |
Power Supply Selective Mapping for Accurate Timing Analysis. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Chun-Yu Chuang, Wai-Kei Mak |
Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Ryan Fung, Vaughn Betz, William Chow |
Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Bao Liu 0001 |
Signal Probability Based Statistical Timing Analysis. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Jun-Kuei Zeng, Chung-Ping Chen |
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Jan Gustafsson, Björn Lisper, Markus Schordan, Christian Ferdinand, Peter Gliwa, Marek Jersak, Guillem Bernat |
ALL-TIMES - A European Project on Integrating Timing Technology. |
ISoLA |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Ruiming Chen, Lizheng Zhang, Vladimir Zolotov, Chandu Visweswariah, Jinjun Xiong |
Static timing: Back to our roots. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu |
Adjustment-based modeling for statistical static timing analysis with high dimension of variability. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Tao Luo 0002, David A. Papa, Zhuo Li 0001, Chin Ngai Sze, Charles J. Alpert, David Z. Pan |
Pyramids: an efficient computational geometry-based approach for timing-driven placement. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Muzhou Shao |
Fast Timing Update under the Effect of IR Drop. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani |
0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Yasamin Mostofi, Donald C. Cox |
A robust timing synchronization design in OFDM systems - part II: high-mobility cases. |
IEEE Trans. Wirel. Commun. |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Jingxian Wu 0001, Yahong Rosa Zheng, Khaled Ben Letaief, Chengshan Xiao |
On the error performance of wireless systems with frequency selective fading and receiver timing phase offset. |
IEEE Trans. Wirel. Commun. |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Kai Yang, Kwang-Ting Cheng |
Silicon Debug for Timing Errors. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu 0002, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng |
Efficient Timing Analysis With Known False Paths Using Biclique Covering. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Mohamed Marey, Heidi Steendam |
Analysis of the Narrowband Interference Effect on OFDM Timing Synchronization. |
IEEE Trans. Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury, Lothar Thiele, Unmesh D. Bordoloi, Cem Derdiyok |
Cache-Aware Timing Analysis of Streaming Applications. |
ECRTS |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Yongjian Tang, Hans Hegt, Arthur H. M. van Roermund, Konstantinos Doris, Joost Briaire |
Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Mami Noguchi, Takekazu Kato |
Geometric and Timing Calibration for Unsynchronized Cameras Using Trajectories of a Moving Marker. |
WACV |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Ratnakar Goyal, Sachin Shrivastava, Harindranath Parameswaran, Parveen Khurana |
Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Kai Yang, Kwang-Ting Cheng |
Timing-reasoning-based delay fault diagnosis. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Dipankar Das 0002, Rajeev Kumar 0004, P. P. Chakrabarti 0001 |
Timing Verification of UML Activity Diagram Based Code Block Level Models for Real Time Multiprocessor System-on-Chip Applications. |
APSEC |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Claude Helmstetter, Florence Maraninchi, Laurent Maillet-Contoz |
Test Coverage for Loose Timing Annotations. |
FMICS/PDMC |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee |
Timing-constrained yield-driven wire sizing for critical area minimization. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Di Wu 0017, Jiang Hu, Min Zhao 0001, Rabi N. Mahapatra |
Timing driven track routing considering coupling capacitance. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Gunilla Widén-Wulff, Elisabeth Davenport |
Information Sharing and Timing: Findings from Two Finnish Organizations. |
CoLIS |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Keoncheol Shin, Taewhan Kim |
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Frank Mueller 0001 |
Timing Analysis: In Search of Multiple Paradigms. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Donna Nakano, Erric Solomon |
Task oriented visual interface for debugging timing problems in hardware design. |
AVI |
2004 |
DBLP DOI BibTeX RDF |
cognitive model of users, information visualization, visual interface design |
30 | Ryan Fung, Vaughn Betz, William Chow |
Simultaneous short-path and long-path timing optimization for FPGAs. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
30 | You-Chang Ko, Eui-Seok Hwang, Jeong-Shik Dong, Hyong-Woo Lee, Choong-Ho Cho |
Throughput Analysis of ETSI BRAN HIPERLAN/2 MAC Protocol Taking Guard Timing Spaces into Consideration. (PDF / PS) |
PWC |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Puneet Gupta 0001, Andrew B. Kahng, Stefanus Mantik |
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
30 | António Casimiro, Paulo Veríssimo |
Generic Timing Fault Tolerance using a Timely Computing Base. |
DSN |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Carl J. Mauer, Mark D. Hill, David A. Wood 0001 |
Full-system timing-first simulation. |
SIGMETRICS |
2002 |
DBLP DOI BibTeX RDF |
|
30 | I-De Huang, Sandeep K. Gupta 0001, Melvin A. Breuer |
Accurate and Efficient Static Timing Analysis with Crosstalk. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Alexander Marquardt, Vaughn Betz, Jonathan Rose |
Timing-driven placement for FPGAs. |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Chung-Sheng Li, Kumar N. Sivarajan, David G. Messerschmitt |
Statistical analysis of timing rules for high-speed synchronous VLSI systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng |
POSET timing and its application to the synthesis and verification of gate-level timed circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Jacob White 0001, Jacob Avidan, Ibrahim Abe M. Elfadel, D. F. Wong 0001 |
Advances in transistor timing, simulation, and optimization (tutorial abstract). |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh |
TIGER: an efficient timing-driven global router for gate array and standard cell layout design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
30 | Anmol Mathur, Kuang-Chien Chen, C. L. Liu 0001 |
Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. |
FPGA |
1995 |
DBLP DOI BibTeX RDF |
|
30 | Hagit Attiya, Taly Djerassi-Shintel |
Time Bounds for Decision Problems in the Presence of Timing Uncertainty and Failures. |
WDAG |
1993 |
DBLP DOI BibTeX RDF |
|
30 | James R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi |
A stochastic jitter model for analyzing digital timing-recovery circuits. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
delay-locked loop (DLL), mean-time-between-failures (MTBF), timing margins, timing recovery circuits, Markov chain, stochastic model, jitter, bit-error-rate (BER) |
30 | Renaud Jolivet, Alexander Rauch, Hans-Rudolf Lüscher, Wulfram Gerstner |
Predicting spike timing of neocortical pyramidal neurons by simple threshold models. |
J. Comput. Neurosci. |
2006 |
DBLP DOI BibTeX RDF |
Spike Response Model, Stochastic input, Spike-timing reliability, Predicting spike timing, Adapting threshold |
30 | Ali Dasdan, Ivan Hom |
Handling inverted temperature dependence in static timing analysis. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
timing corners, voltage dependence, Static timing analysis, temperature dependence |
30 | Xuandong Li, Johan Lilius |
Checking compositions of UML sequence diagrams for timing inconsistency. |
APSEC |
2000 |
DBLP DOI BibTeX RDF |
UML sequence diagram composition checking, timing inconsistency checking, real-time systems specification, system behaviour scenarios, high-level graphs, real-time systems, model checking, Unified Modeling Language, formal verification, graphs, timing, specification languages, sequences, diagrams, object interactions |
30 | Stanislav Polonsky, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Pia N. Sanda |
Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
imaging circuit analysis, IBM G6 microprocessor, non-invasive backside timing, Picosecond Imaging Circuit Analysis, waveform extraction, integrated circuit testing, timing analysis, race condition, circuit switching, integrated memory circuits, hazards and race conditions, L1 cache |
30 | Håkan Sundell, Philippas Tsigas |
Space efficient wait-free buffer sharing in multiprocessor real-time systems based on timing information. |
RTCSA |
2000 |
DBLP DOI BibTeX RDF |
space-efficient wait-free algorithm, real-time multiprocessor systems, deadline guarantees, nonblocking algorithms, unbounded time-stamps, time-stamp bounding, concurrent read/write operations, real-time systems, protocol, data structures, data structures, timing, multiprocessing systems, mutual exclusion, blocking, buffer storage, timing information, shared buffer, memory protocols |
30 | Rung-Bin Lin, Meng-Chiou Wu |
A New Statistical Approach to Timing Analysis of VLSI Circuits. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
Statistical timing anylysis, longest path delay, path correlation, timing simulation |
30 | Hakan Yalcin, John P. Hayes, Karem A. Sakallah |
An approximate timing analysis method for datapath circuits. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
Approximate timing analysis, conditional delay matrix, delay calculation, hierarchical timing models, signal propagation conditions |
30 | Ayman I. Kayssi |
Macromodeling C- and RC-loaded CMOS inverters for timing analysis. |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
RC-loaded CMOS inverters, C-loaded CMOS inverters, series-resistor shunt-capacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling |
30 | Tong Gao, Hachem Moussa, I-Ling Yen, Farokh B. Bastani, Jun-Jang Jeng |
Service Composition for Real-Time Assurance. |
COMPSAC |
2008 |
DBLP DOI BibTeX RDF |
Real-Time assurance, Specification and analysis, Service Composition |
30 | Paul K. Rodman |
Forest vs. trees: where's the slack? |
DAC |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Mukund Sivaraman, Andrzej J. Strojwas |
Primitive path delay faults: identification and their use in timinganalysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
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